14baa9922SRussell King /* 24baa9922SRussell King * arch/arm/include/asm/cache.h 34baa9922SRussell King */ 44baa9922SRussell King #ifndef __ASMARM_CACHE_H 54baa9922SRussell King #define __ASMARM_CACHE_H 64baa9922SRussell King 7910a17e5SKirill A. Shutemov #define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT 84baa9922SRussell King #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 94baa9922SRussell King 10eb5f4ca9SMartin Fuzzey /* 11eb5f4ca9SMartin Fuzzey * Memory returned by kmalloc() may be used for DMA, so we must make 12eb5f4ca9SMartin Fuzzey * sure that all such allocations are cache aligned. Otherwise, 13eb5f4ca9SMartin Fuzzey * unrelated code may cause parts of the buffer to be read into the 14eb5f4ca9SMartin Fuzzey * cache before the transfer is done, causing old data to be seen by 15eb5f4ca9SMartin Fuzzey * the CPU. 16eb5f4ca9SMartin Fuzzey */ 17a6eb9fe1SFUJITA Tomonori #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 18eb5f4ca9SMartin Fuzzey 19eb5f4ca9SMartin Fuzzey /* 20eb5f4ca9SMartin Fuzzey * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. 21eb5f4ca9SMartin Fuzzey */ 22eb5f4ca9SMartin Fuzzey #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 23eb5f4ca9SMartin Fuzzey #define ARCH_SLAB_MINALIGN 8 24eb5f4ca9SMartin Fuzzey #endif 25eb5f4ca9SMartin Fuzzey 264baa9922SRussell King #endif 27