1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * arch/arm/include/asm/assembler.h 4 * 5 * Copyright (C) 1996-2000 Russell King 6 * 7 * This file contains arm architecture specific defines 8 * for the different processors. 9 * 10 * Do not include any C declarations in this file - it is included by 11 * assembler source. 12 */ 13 #ifndef __ASM_ASSEMBLER_H__ 14 #define __ASM_ASSEMBLER_H__ 15 16 #ifndef __ASSEMBLY__ 17 #error "Only include this from assembly code" 18 #endif 19 20 #include <asm/ptrace.h> 21 #include <asm/opcodes-virt.h> 22 #include <asm/asm-offsets.h> 23 #include <asm/page.h> 24 #include <asm/thread_info.h> 25 #include <asm/uaccess-asm.h> 26 27 #define IOMEM(x) (x) 28 29 /* 30 * Endian independent macros for shifting bytes within registers. 31 */ 32 #ifndef __ARMEB__ 33 #define lspull lsr 34 #define lspush lsl 35 #define get_byte_0 lsl #0 36 #define get_byte_1 lsr #8 37 #define get_byte_2 lsr #16 38 #define get_byte_3 lsr #24 39 #define put_byte_0 lsl #0 40 #define put_byte_1 lsl #8 41 #define put_byte_2 lsl #16 42 #define put_byte_3 lsl #24 43 #else 44 #define lspull lsl 45 #define lspush lsr 46 #define get_byte_0 lsr #24 47 #define get_byte_1 lsr #16 48 #define get_byte_2 lsr #8 49 #define get_byte_3 lsl #0 50 #define put_byte_0 lsl #24 51 #define put_byte_1 lsl #16 52 #define put_byte_2 lsl #8 53 #define put_byte_3 lsl #0 54 #endif 55 56 /* Select code for any configuration running in BE8 mode */ 57 #ifdef CONFIG_CPU_ENDIAN_BE8 58 #define ARM_BE8(code...) code 59 #else 60 #define ARM_BE8(code...) 61 #endif 62 63 /* 64 * Data preload for architectures that support it 65 */ 66 #if __LINUX_ARM_ARCH__ >= 5 67 #define PLD(code...) code 68 #else 69 #define PLD(code...) 70 #endif 71 72 /* 73 * This can be used to enable code to cacheline align the destination 74 * pointer when bulk writing to memory. Experiments on StrongARM and 75 * XScale didn't show this a worthwhile thing to do when the cache is not 76 * set to write-allocate (this would need further testing on XScale when WA 77 * is used). 78 * 79 * On Feroceon there is much to gain however, regardless of cache mode. 80 */ 81 #ifdef CONFIG_CPU_FEROCEON 82 #define CALGN(code...) code 83 #else 84 #define CALGN(code...) 85 #endif 86 87 #define IMM12_MASK 0xfff 88 89 /* the frame pointer used for stack unwinding */ 90 ARM( fpreg .req r11 ) 91 THUMB( fpreg .req r7 ) 92 93 /* 94 * Enable and disable interrupts 95 */ 96 #if __LINUX_ARM_ARCH__ >= 6 97 .macro disable_irq_notrace 98 cpsid i 99 .endm 100 101 .macro enable_irq_notrace 102 cpsie i 103 .endm 104 #else 105 .macro disable_irq_notrace 106 msr cpsr_c, #PSR_I_BIT | SVC_MODE 107 .endm 108 109 .macro enable_irq_notrace 110 msr cpsr_c, #SVC_MODE 111 .endm 112 #endif 113 114 #if __LINUX_ARM_ARCH__ < 7 115 .macro dsb, args 116 mcr p15, 0, r0, c7, c10, 4 117 .endm 118 119 .macro isb, args 120 mcr p15, 0, r0, c7, c5, 4 121 .endm 122 #endif 123 124 .macro asm_trace_hardirqs_off, save=1 125 #if defined(CONFIG_TRACE_IRQFLAGS) 126 .if \save 127 stmdb sp!, {r0-r3, ip, lr} 128 .endif 129 bl trace_hardirqs_off 130 .if \save 131 ldmia sp!, {r0-r3, ip, lr} 132 .endif 133 #endif 134 .endm 135 136 .macro asm_trace_hardirqs_on, cond=al, save=1 137 #if defined(CONFIG_TRACE_IRQFLAGS) 138 /* 139 * actually the registers should be pushed and pop'd conditionally, but 140 * after bl the flags are certainly clobbered 141 */ 142 .if \save 143 stmdb sp!, {r0-r3, ip, lr} 144 .endif 145 bl\cond trace_hardirqs_on 146 .if \save 147 ldmia sp!, {r0-r3, ip, lr} 148 .endif 149 #endif 150 .endm 151 152 .macro disable_irq, save=1 153 disable_irq_notrace 154 asm_trace_hardirqs_off \save 155 .endm 156 157 .macro enable_irq 158 asm_trace_hardirqs_on 159 enable_irq_notrace 160 .endm 161 /* 162 * Save the current IRQ state and disable IRQs. Note that this macro 163 * assumes FIQs are enabled, and that the processor is in SVC mode. 164 */ 165 .macro save_and_disable_irqs, oldcpsr 166 #ifdef CONFIG_CPU_V7M 167 mrs \oldcpsr, primask 168 #else 169 mrs \oldcpsr, cpsr 170 #endif 171 disable_irq 172 .endm 173 174 .macro save_and_disable_irqs_notrace, oldcpsr 175 #ifdef CONFIG_CPU_V7M 176 mrs \oldcpsr, primask 177 #else 178 mrs \oldcpsr, cpsr 179 #endif 180 disable_irq_notrace 181 .endm 182 183 /* 184 * Restore interrupt state previously stored in a register. We don't 185 * guarantee that this will preserve the flags. 186 */ 187 .macro restore_irqs_notrace, oldcpsr 188 #ifdef CONFIG_CPU_V7M 189 msr primask, \oldcpsr 190 #else 191 msr cpsr_c, \oldcpsr 192 #endif 193 .endm 194 195 .macro restore_irqs, oldcpsr 196 tst \oldcpsr, #PSR_I_BIT 197 asm_trace_hardirqs_on cond=eq 198 restore_irqs_notrace \oldcpsr 199 .endm 200 201 /* 202 * Assembly version of "adr rd, BSYM(sym)". This should only be used to 203 * reference local symbols in the same assembly file which are to be 204 * resolved by the assembler. Other usage is undefined. 205 */ 206 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 207 .macro badr\c, rd, sym 208 #ifdef CONFIG_THUMB2_KERNEL 209 adr\c \rd, \sym + 1 210 #else 211 adr\c \rd, \sym 212 #endif 213 .endm 214 .endr 215 216 /* 217 * Get current thread_info. 218 */ 219 .macro get_thread_info, rd 220 /* thread_info is the first member of struct task_struct */ 221 get_current \rd 222 .endm 223 224 /* 225 * Increment/decrement the preempt count. 226 */ 227 #ifdef CONFIG_PREEMPT_COUNT 228 .macro inc_preempt_count, ti, tmp 229 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 230 add \tmp, \tmp, #1 @ increment it 231 str \tmp, [\ti, #TI_PREEMPT] 232 .endm 233 234 .macro dec_preempt_count, ti, tmp 235 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 236 sub \tmp, \tmp, #1 @ decrement it 237 str \tmp, [\ti, #TI_PREEMPT] 238 .endm 239 #else 240 .macro inc_preempt_count, ti, tmp 241 .endm 242 243 .macro dec_preempt_count, ti, tmp 244 .endm 245 #endif 246 247 #define USERL(l, x...) \ 248 9999: x; \ 249 .pushsection __ex_table,"a"; \ 250 .align 3; \ 251 .long 9999b,l; \ 252 .popsection 253 254 #define USER(x...) USERL(9001f, x) 255 256 #ifdef CONFIG_SMP 257 #define ALT_SMP(instr...) \ 258 9998: instr 259 /* 260 * Note: if you get assembler errors from ALT_UP() when building with 261 * CONFIG_THUMB2_KERNEL, you almost certainly need to use 262 * ALT_SMP( W(instr) ... ) 263 */ 264 #define ALT_UP(instr...) \ 265 .pushsection ".alt.smp.init", "a" ;\ 266 .align 2 ;\ 267 .long 9998b - . ;\ 268 9997: instr ;\ 269 .if . - 9997b == 2 ;\ 270 nop ;\ 271 .endif ;\ 272 .if . - 9997b != 4 ;\ 273 .error "ALT_UP() content must assemble to exactly 4 bytes";\ 274 .endif ;\ 275 .popsection 276 #define ALT_UP_B(label) \ 277 .pushsection ".alt.smp.init", "a" ;\ 278 .align 2 ;\ 279 .long 9998b - . ;\ 280 W(b) . + (label - 9998b) ;\ 281 .popsection 282 #else 283 #define ALT_SMP(instr...) 284 #define ALT_UP(instr...) instr 285 #define ALT_UP_B(label) b label 286 #endif 287 288 /* 289 * this_cpu_offset - load the per-CPU offset of this CPU into 290 * register 'rd' 291 */ 292 .macro this_cpu_offset, rd:req 293 #ifdef CONFIG_SMP 294 ALT_SMP(mrc p15, 0, \rd, c13, c0, 4) 295 #ifdef CONFIG_CPU_V6 296 ALT_UP_B(.L1_\@) 297 .L0_\@: 298 .subsection 1 299 .L1_\@: ldr_va \rd, __per_cpu_offset 300 b .L0_\@ 301 .previous 302 #endif 303 #else 304 mov \rd, #0 305 #endif 306 .endm 307 308 /* 309 * set_current - store the task pointer of this CPU's current task 310 */ 311 .macro set_current, rn:req, tmp:req 312 #if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP) 313 9998: mcr p15, 0, \rn, c13, c0, 3 @ set TPIDRURO register 314 #ifdef CONFIG_CPU_V6 315 ALT_UP_B(.L0_\@) 316 .subsection 1 317 .L0_\@: str_va \rn, __current, \tmp 318 b .L1_\@ 319 .previous 320 .L1_\@: 321 #endif 322 #else 323 str_va \rn, __current, \tmp 324 #endif 325 .endm 326 327 /* 328 * get_current - load the task pointer of this CPU's current task 329 */ 330 .macro get_current, rd:req 331 #if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP) 332 9998: mrc p15, 0, \rd, c13, c0, 3 @ get TPIDRURO register 333 #ifdef CONFIG_CPU_V6 334 ALT_UP_B(.L0_\@) 335 .subsection 1 336 .L0_\@: ldr_va \rd, __current 337 b .L1_\@ 338 .previous 339 .L1_\@: 340 #endif 341 #else 342 ldr_va \rd, __current 343 #endif 344 .endm 345 346 /* 347 * reload_current - reload the task pointer of this CPU's current task 348 * into the TLS register 349 */ 350 .macro reload_current, t1:req, t2:req 351 #if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP) 352 #ifdef CONFIG_CPU_V6 353 ALT_SMP(nop) 354 ALT_UP_B(.L0_\@) 355 #endif 356 ldr_this_cpu \t1, __entry_task, \t1, \t2 357 mcr p15, 0, \t1, c13, c0, 3 @ store in TPIDRURO 358 .L0_\@: 359 #endif 360 .endm 361 362 /* 363 * Instruction barrier 364 */ 365 .macro instr_sync 366 #if __LINUX_ARM_ARCH__ >= 7 367 isb 368 #elif __LINUX_ARM_ARCH__ == 6 369 mcr p15, 0, r0, c7, c5, 4 370 #endif 371 .endm 372 373 /* 374 * SMP data memory barrier 375 */ 376 .macro smp_dmb mode 377 #ifdef CONFIG_SMP 378 #if __LINUX_ARM_ARCH__ >= 7 379 .ifeqs "\mode","arm" 380 ALT_SMP(dmb ish) 381 .else 382 ALT_SMP(W(dmb) ish) 383 .endif 384 #elif __LINUX_ARM_ARCH__ == 6 385 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 386 #else 387 #error Incompatible SMP platform 388 #endif 389 .ifeqs "\mode","arm" 390 ALT_UP(nop) 391 .else 392 ALT_UP(W(nop)) 393 .endif 394 #endif 395 .endm 396 397 #if defined(CONFIG_CPU_V7M) 398 /* 399 * setmode is used to assert to be in svc mode during boot. For v7-M 400 * this is done in __v7m_setup, so setmode can be empty here. 401 */ 402 .macro setmode, mode, reg 403 .endm 404 #elif defined(CONFIG_THUMB2_KERNEL) 405 .macro setmode, mode, reg 406 mov \reg, #\mode 407 msr cpsr_c, \reg 408 .endm 409 #else 410 .macro setmode, mode, reg 411 msr cpsr_c, #\mode 412 .endm 413 #endif 414 415 /* 416 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is 417 * a scratch register for the macro to overwrite. 418 * 419 * This macro is intended for forcing the CPU into SVC mode at boot time. 420 * you cannot return to the original mode. 421 */ 422 .macro safe_svcmode_maskall reg:req 423 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M) 424 mrs \reg , cpsr 425 eor \reg, \reg, #HYP_MODE 426 tst \reg, #MODE_MASK 427 bic \reg , \reg , #MODE_MASK 428 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE 429 THUMB( orr \reg , \reg , #PSR_T_BIT ) 430 bne 1f 431 orr \reg, \reg, #PSR_A_BIT 432 badr lr, 2f 433 msr spsr_cxsf, \reg 434 __MSR_ELR_HYP(14) 435 __ERET 436 1: msr cpsr_c, \reg 437 2: 438 #else 439 /* 440 * workaround for possibly broken pre-v6 hardware 441 * (akita, Sharp Zaurus C-1000, PXA270-based) 442 */ 443 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg 444 #endif 445 .endm 446 447 /* 448 * STRT/LDRT access macros with ARM and Thumb-2 variants 449 */ 450 #ifdef CONFIG_THUMB2_KERNEL 451 452 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 453 9999: 454 .if \inc == 1 455 \instr\()b\t\cond\().w \reg, [\ptr, #\off] 456 .elseif \inc == 4 457 \instr\t\cond\().w \reg, [\ptr, #\off] 458 .else 459 .error "Unsupported inc macro argument" 460 .endif 461 462 .pushsection __ex_table,"a" 463 .align 3 464 .long 9999b, \abort 465 .popsection 466 .endm 467 468 .macro usracc, instr, reg, ptr, inc, cond, rept, abort 469 @ explicit IT instruction needed because of the label 470 @ introduced by the USER macro 471 .ifnc \cond,al 472 .if \rept == 1 473 itt \cond 474 .elseif \rept == 2 475 ittt \cond 476 .else 477 .error "Unsupported rept macro argument" 478 .endif 479 .endif 480 481 @ Slightly optimised to avoid incrementing the pointer twice 482 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 483 .if \rept == 2 484 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 485 .endif 486 487 add\cond \ptr, #\rept * \inc 488 .endm 489 490 #else /* !CONFIG_THUMB2_KERNEL */ 491 492 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 493 .rept \rept 494 9999: 495 .if \inc == 1 496 \instr\()b\t\cond \reg, [\ptr], #\inc 497 .elseif \inc == 4 498 \instr\t\cond \reg, [\ptr], #\inc 499 .else 500 .error "Unsupported inc macro argument" 501 .endif 502 503 .pushsection __ex_table,"a" 504 .align 3 505 .long 9999b, \abort 506 .popsection 507 .endr 508 .endm 509 510 #endif /* CONFIG_THUMB2_KERNEL */ 511 512 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 513 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 514 .endm 515 516 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 517 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 518 .endm 519 520 /* Utility macro for declaring string literals */ 521 .macro string name:req, string 522 .type \name , #object 523 \name: 524 .asciz "\string" 525 .size \name , . - \name 526 .endm 527 528 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 529 .macro ret\c, reg 530 #if __LINUX_ARM_ARCH__ < 6 531 mov\c pc, \reg 532 #else 533 .ifeqs "\reg", "lr" 534 bx\c \reg 535 .else 536 mov\c pc, \reg 537 .endif 538 #endif 539 .endm 540 .endr 541 542 .macro ret.w, reg 543 ret \reg 544 #ifdef CONFIG_THUMB2_KERNEL 545 nop 546 #endif 547 .endm 548 549 .macro bug, msg, line 550 #ifdef CONFIG_THUMB2_KERNEL 551 1: .inst 0xde02 552 #else 553 1: .inst 0xe7f001f2 554 #endif 555 #ifdef CONFIG_DEBUG_BUGVERBOSE 556 .pushsection .rodata.str, "aMS", %progbits, 1 557 2: .asciz "\msg" 558 .popsection 559 .pushsection __bug_table, "aw" 560 .align 2 561 .word 1b, 2b 562 .hword \line 563 .popsection 564 #endif 565 .endm 566 567 #ifdef CONFIG_KPROBES 568 #define _ASM_NOKPROBE(entry) \ 569 .pushsection "_kprobe_blacklist", "aw" ; \ 570 .balign 4 ; \ 571 .long entry; \ 572 .popsection 573 #else 574 #define _ASM_NOKPROBE(entry) 575 #endif 576 577 .macro __adldst_l, op, reg, sym, tmp, c 578 .if __LINUX_ARM_ARCH__ < 7 579 ldr\c \tmp, .La\@ 580 .subsection 1 581 .align 2 582 .La\@: .long \sym - .Lpc\@ 583 .previous 584 .else 585 .ifnb \c 586 THUMB( ittt \c ) 587 .endif 588 movw\c \tmp, #:lower16:\sym - .Lpc\@ 589 movt\c \tmp, #:upper16:\sym - .Lpc\@ 590 .endif 591 592 #ifndef CONFIG_THUMB2_KERNEL 593 .set .Lpc\@, . + 8 // PC bias 594 .ifc \op, add 595 add\c \reg, \tmp, pc 596 .else 597 \op\c \reg, [pc, \tmp] 598 .endif 599 #else 600 .Lb\@: add\c \tmp, \tmp, pc 601 /* 602 * In Thumb-2 builds, the PC bias depends on whether we are currently 603 * emitting into a .arm or a .thumb section. The size of the add opcode 604 * above will be 2 bytes when emitting in Thumb mode and 4 bytes when 605 * emitting in ARM mode, so let's use this to account for the bias. 606 */ 607 .set .Lpc\@, . + (. - .Lb\@) 608 609 .ifnc \op, add 610 \op\c \reg, [\tmp] 611 .endif 612 #endif 613 .endm 614 615 /* 616 * mov_l - move a constant value or [relocated] address into a register 617 */ 618 .macro mov_l, dst:req, imm:req, cond 619 .if __LINUX_ARM_ARCH__ < 7 620 ldr\cond \dst, =\imm 621 .else 622 movw\cond \dst, #:lower16:\imm 623 movt\cond \dst, #:upper16:\imm 624 .endif 625 .endm 626 627 /* 628 * adr_l - adr pseudo-op with unlimited range 629 * 630 * @dst: destination register 631 * @sym: name of the symbol 632 * @cond: conditional opcode suffix 633 */ 634 .macro adr_l, dst:req, sym:req, cond 635 __adldst_l add, \dst, \sym, \dst, \cond 636 .endm 637 638 /* 639 * ldr_l - ldr <literal> pseudo-op with unlimited range 640 * 641 * @dst: destination register 642 * @sym: name of the symbol 643 * @cond: conditional opcode suffix 644 */ 645 .macro ldr_l, dst:req, sym:req, cond 646 __adldst_l ldr, \dst, \sym, \dst, \cond 647 .endm 648 649 /* 650 * str_l - str <literal> pseudo-op with unlimited range 651 * 652 * @src: source register 653 * @sym: name of the symbol 654 * @tmp: mandatory scratch register 655 * @cond: conditional opcode suffix 656 */ 657 .macro str_l, src:req, sym:req, tmp:req, cond 658 __adldst_l str, \src, \sym, \tmp, \cond 659 .endm 660 661 .macro __ldst_va, op, reg, tmp, sym, cond, offset 662 #if __LINUX_ARM_ARCH__ >= 7 || \ 663 !defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \ 664 (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS)) 665 mov_l \tmp, \sym, \cond 666 #else 667 /* 668 * Avoid a literal load, by emitting a sequence of ADD/LDR instructions 669 * with the appropriate relocations. The combined sequence has a range 670 * of -/+ 256 MiB, which should be sufficient for the core kernel and 671 * for modules loaded into the module region. 672 */ 673 .globl \sym 674 .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym 675 .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym 676 .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym 677 .L0_\@: sub\cond \tmp, pc, #8 - \offset 678 .L1_\@: sub\cond \tmp, \tmp, #4 - \offset 679 .L2_\@: 680 #endif 681 \op\cond \reg, [\tmp, #\offset] 682 .endm 683 684 /* 685 * ldr_va - load a 32-bit word from the virtual address of \sym 686 */ 687 .macro ldr_va, rd:req, sym:req, cond, tmp, offset=0 688 .ifnb \tmp 689 __ldst_va ldr, \rd, \tmp, \sym, \cond, \offset 690 .else 691 __ldst_va ldr, \rd, \rd, \sym, \cond, \offset 692 .endif 693 .endm 694 695 /* 696 * str_va - store a 32-bit word to the virtual address of \sym 697 */ 698 .macro str_va, rn:req, sym:req, tmp:req, cond 699 __ldst_va str, \rn, \tmp, \sym, \cond, 0 700 .endm 701 702 /* 703 * ldr_this_cpu_armv6 - Load a 32-bit word from the per-CPU variable 'sym', 704 * without using a temp register. Supported in ARM mode 705 * only. 706 */ 707 .macro ldr_this_cpu_armv6, rd:req, sym:req 708 this_cpu_offset \rd 709 .globl \sym 710 .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym 711 .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym 712 .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym 713 add \rd, \rd, pc 714 .L0_\@: sub \rd, \rd, #4 715 .L1_\@: sub \rd, \rd, #0 716 .L2_\@: ldr \rd, [\rd, #4] 717 .endm 718 719 /* 720 * ldr_this_cpu - Load a 32-bit word from the per-CPU variable 'sym' 721 * into register 'rd', which may be the stack pointer, 722 * using 't1' and 't2' as general temp registers. These 723 * are permitted to overlap with 'rd' if != sp 724 */ 725 .macro ldr_this_cpu, rd:req, sym:req, t1:req, t2:req 726 #ifndef CONFIG_SMP 727 ldr_va \rd, \sym, tmp=\t1 728 #elif __LINUX_ARM_ARCH__ >= 7 || \ 729 !defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \ 730 (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS)) 731 this_cpu_offset \t1 732 mov_l \t2, \sym 733 ldr \rd, [\t1, \t2] 734 #else 735 ldr_this_cpu_armv6 \rd, \sym 736 #endif 737 .endm 738 739 /* 740 * rev_l - byte-swap a 32-bit value 741 * 742 * @val: source/destination register 743 * @tmp: scratch register 744 */ 745 .macro rev_l, val:req, tmp:req 746 .if __LINUX_ARM_ARCH__ < 6 747 eor \tmp, \val, \val, ror #16 748 bic \tmp, \tmp, #0x00ff0000 749 mov \val, \val, ror #8 750 eor \val, \val, \tmp, lsr #8 751 .else 752 rev \val, \val 753 .endif 754 .endm 755 756 .if __LINUX_ARM_ARCH__ < 6 757 .set .Lrev_l_uses_tmp, 1 758 .else 759 .set .Lrev_l_uses_tmp, 0 760 .endif 761 762 /* 763 * bl_r - branch and link to register 764 * 765 * @dst: target to branch to 766 * @c: conditional opcode suffix 767 */ 768 .macro bl_r, dst:req, c 769 .if __LINUX_ARM_ARCH__ < 6 770 mov\c lr, pc 771 mov\c pc, \dst 772 .else 773 blx\c \dst 774 .endif 775 .endm 776 777 #endif /* __ASM_ASSEMBLER_H__ */ 778