1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * arch/arm/include/asm/assembler.h 4 * 5 * Copyright (C) 1996-2000 Russell King 6 * 7 * This file contains arm architecture specific defines 8 * for the different processors. 9 * 10 * Do not include any C declarations in this file - it is included by 11 * assembler source. 12 */ 13 #ifndef __ASM_ASSEMBLER_H__ 14 #define __ASM_ASSEMBLER_H__ 15 16 #ifndef __ASSEMBLY__ 17 #error "Only include this from assembly code" 18 #endif 19 20 #include <asm/ptrace.h> 21 #include <asm/opcodes-virt.h> 22 #include <asm/asm-offsets.h> 23 #include <asm/page.h> 24 #include <asm/thread_info.h> 25 #include <asm/uaccess-asm.h> 26 27 #define IOMEM(x) (x) 28 29 /* 30 * Endian independent macros for shifting bytes within registers. 31 */ 32 #ifndef __ARMEB__ 33 #define lspull lsr 34 #define lspush lsl 35 #define get_byte_0 lsl #0 36 #define get_byte_1 lsr #8 37 #define get_byte_2 lsr #16 38 #define get_byte_3 lsr #24 39 #define put_byte_0 lsl #0 40 #define put_byte_1 lsl #8 41 #define put_byte_2 lsl #16 42 #define put_byte_3 lsl #24 43 #else 44 #define lspull lsl 45 #define lspush lsr 46 #define get_byte_0 lsr #24 47 #define get_byte_1 lsr #16 48 #define get_byte_2 lsr #8 49 #define get_byte_3 lsl #0 50 #define put_byte_0 lsl #24 51 #define put_byte_1 lsl #16 52 #define put_byte_2 lsl #8 53 #define put_byte_3 lsl #0 54 #endif 55 56 /* Select code for any configuration running in BE8 mode */ 57 #ifdef CONFIG_CPU_ENDIAN_BE8 58 #define ARM_BE8(code...) code 59 #else 60 #define ARM_BE8(code...) 61 #endif 62 63 /* 64 * Data preload for architectures that support it 65 */ 66 #if __LINUX_ARM_ARCH__ >= 5 67 #define PLD(code...) code 68 #else 69 #define PLD(code...) 70 #endif 71 72 /* 73 * This can be used to enable code to cacheline align the destination 74 * pointer when bulk writing to memory. Experiments on StrongARM and 75 * XScale didn't show this a worthwhile thing to do when the cache is not 76 * set to write-allocate (this would need further testing on XScale when WA 77 * is used). 78 * 79 * On Feroceon there is much to gain however, regardless of cache mode. 80 */ 81 #ifdef CONFIG_CPU_FEROCEON 82 #define CALGN(code...) code 83 #else 84 #define CALGN(code...) 85 #endif 86 87 #define IMM12_MASK 0xfff 88 89 /* 90 * Enable and disable interrupts 91 */ 92 #if __LINUX_ARM_ARCH__ >= 6 93 .macro disable_irq_notrace 94 cpsid i 95 .endm 96 97 .macro enable_irq_notrace 98 cpsie i 99 .endm 100 #else 101 .macro disable_irq_notrace 102 msr cpsr_c, #PSR_I_BIT | SVC_MODE 103 .endm 104 105 .macro enable_irq_notrace 106 msr cpsr_c, #SVC_MODE 107 .endm 108 #endif 109 110 .macro asm_trace_hardirqs_off, save=1 111 #if defined(CONFIG_TRACE_IRQFLAGS) 112 .if \save 113 stmdb sp!, {r0-r3, ip, lr} 114 .endif 115 bl trace_hardirqs_off 116 .if \save 117 ldmia sp!, {r0-r3, ip, lr} 118 .endif 119 #endif 120 .endm 121 122 .macro asm_trace_hardirqs_on, cond=al, save=1 123 #if defined(CONFIG_TRACE_IRQFLAGS) 124 /* 125 * actually the registers should be pushed and pop'd conditionally, but 126 * after bl the flags are certainly clobbered 127 */ 128 .if \save 129 stmdb sp!, {r0-r3, ip, lr} 130 .endif 131 bl\cond trace_hardirqs_on 132 .if \save 133 ldmia sp!, {r0-r3, ip, lr} 134 .endif 135 #endif 136 .endm 137 138 .macro disable_irq, save=1 139 disable_irq_notrace 140 asm_trace_hardirqs_off \save 141 .endm 142 143 .macro enable_irq 144 asm_trace_hardirqs_on 145 enable_irq_notrace 146 .endm 147 /* 148 * Save the current IRQ state and disable IRQs. Note that this macro 149 * assumes FIQs are enabled, and that the processor is in SVC mode. 150 */ 151 .macro save_and_disable_irqs, oldcpsr 152 #ifdef CONFIG_CPU_V7M 153 mrs \oldcpsr, primask 154 #else 155 mrs \oldcpsr, cpsr 156 #endif 157 disable_irq 158 .endm 159 160 .macro save_and_disable_irqs_notrace, oldcpsr 161 #ifdef CONFIG_CPU_V7M 162 mrs \oldcpsr, primask 163 #else 164 mrs \oldcpsr, cpsr 165 #endif 166 disable_irq_notrace 167 .endm 168 169 /* 170 * Restore interrupt state previously stored in a register. We don't 171 * guarantee that this will preserve the flags. 172 */ 173 .macro restore_irqs_notrace, oldcpsr 174 #ifdef CONFIG_CPU_V7M 175 msr primask, \oldcpsr 176 #else 177 msr cpsr_c, \oldcpsr 178 #endif 179 .endm 180 181 .macro restore_irqs, oldcpsr 182 tst \oldcpsr, #PSR_I_BIT 183 asm_trace_hardirqs_on cond=eq 184 restore_irqs_notrace \oldcpsr 185 .endm 186 187 /* 188 * Assembly version of "adr rd, BSYM(sym)". This should only be used to 189 * reference local symbols in the same assembly file which are to be 190 * resolved by the assembler. Other usage is undefined. 191 */ 192 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 193 .macro badr\c, rd, sym 194 #ifdef CONFIG_THUMB2_KERNEL 195 adr\c \rd, \sym + 1 196 #else 197 adr\c \rd, \sym 198 #endif 199 .endm 200 .endr 201 202 /* 203 * Get current thread_info. 204 */ 205 .macro get_thread_info, rd 206 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT ) 207 THUMB( mov \rd, sp ) 208 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT ) 209 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT 210 .endm 211 212 /* 213 * Increment/decrement the preempt count. 214 */ 215 #ifdef CONFIG_PREEMPT_COUNT 216 .macro inc_preempt_count, ti, tmp 217 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 218 add \tmp, \tmp, #1 @ increment it 219 str \tmp, [\ti, #TI_PREEMPT] 220 .endm 221 222 .macro dec_preempt_count, ti, tmp 223 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 224 sub \tmp, \tmp, #1 @ decrement it 225 str \tmp, [\ti, #TI_PREEMPT] 226 .endm 227 228 .macro dec_preempt_count_ti, ti, tmp 229 get_thread_info \ti 230 dec_preempt_count \ti, \tmp 231 .endm 232 #else 233 .macro inc_preempt_count, ti, tmp 234 .endm 235 236 .macro dec_preempt_count, ti, tmp 237 .endm 238 239 .macro dec_preempt_count_ti, ti, tmp 240 .endm 241 #endif 242 243 #define USERL(l, x...) \ 244 9999: x; \ 245 .pushsection __ex_table,"a"; \ 246 .align 3; \ 247 .long 9999b,l; \ 248 .popsection 249 250 #define USER(x...) USERL(9001f, x) 251 252 #ifdef CONFIG_SMP 253 #define ALT_SMP(instr...) \ 254 9998: instr 255 /* 256 * Note: if you get assembler errors from ALT_UP() when building with 257 * CONFIG_THUMB2_KERNEL, you almost certainly need to use 258 * ALT_SMP( W(instr) ... ) 259 */ 260 #define ALT_UP(instr...) \ 261 .pushsection ".alt.smp.init", "a" ;\ 262 .align 2 ;\ 263 .long 9998b - . ;\ 264 9997: instr ;\ 265 .if . - 9997b == 2 ;\ 266 nop ;\ 267 .endif ;\ 268 .if . - 9997b != 4 ;\ 269 .error "ALT_UP() content must assemble to exactly 4 bytes";\ 270 .endif ;\ 271 .popsection 272 #define ALT_UP_B(label) \ 273 .pushsection ".alt.smp.init", "a" ;\ 274 .align 2 ;\ 275 .long 9998b - . ;\ 276 W(b) . + (label - 9998b) ;\ 277 .popsection 278 #else 279 #define ALT_SMP(instr...) 280 #define ALT_UP(instr...) instr 281 #define ALT_UP_B(label) b label 282 #endif 283 284 /* 285 * Instruction barrier 286 */ 287 .macro instr_sync 288 #if __LINUX_ARM_ARCH__ >= 7 289 isb 290 #elif __LINUX_ARM_ARCH__ == 6 291 mcr p15, 0, r0, c7, c5, 4 292 #endif 293 .endm 294 295 /* 296 * SMP data memory barrier 297 */ 298 .macro smp_dmb mode 299 #ifdef CONFIG_SMP 300 #if __LINUX_ARM_ARCH__ >= 7 301 .ifeqs "\mode","arm" 302 ALT_SMP(dmb ish) 303 .else 304 ALT_SMP(W(dmb) ish) 305 .endif 306 #elif __LINUX_ARM_ARCH__ == 6 307 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 308 #else 309 #error Incompatible SMP platform 310 #endif 311 .ifeqs "\mode","arm" 312 ALT_UP(nop) 313 .else 314 ALT_UP(W(nop)) 315 .endif 316 #endif 317 .endm 318 319 #if defined(CONFIG_CPU_V7M) 320 /* 321 * setmode is used to assert to be in svc mode during boot. For v7-M 322 * this is done in __v7m_setup, so setmode can be empty here. 323 */ 324 .macro setmode, mode, reg 325 .endm 326 #elif defined(CONFIG_THUMB2_KERNEL) 327 .macro setmode, mode, reg 328 mov \reg, #\mode 329 msr cpsr_c, \reg 330 .endm 331 #else 332 .macro setmode, mode, reg 333 msr cpsr_c, #\mode 334 .endm 335 #endif 336 337 /* 338 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is 339 * a scratch register for the macro to overwrite. 340 * 341 * This macro is intended for forcing the CPU into SVC mode at boot time. 342 * you cannot return to the original mode. 343 */ 344 .macro safe_svcmode_maskall reg:req 345 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M) 346 mrs \reg , cpsr 347 eor \reg, \reg, #HYP_MODE 348 tst \reg, #MODE_MASK 349 bic \reg , \reg , #MODE_MASK 350 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE 351 THUMB( orr \reg , \reg , #PSR_T_BIT ) 352 bne 1f 353 orr \reg, \reg, #PSR_A_BIT 354 badr lr, 2f 355 msr spsr_cxsf, \reg 356 __MSR_ELR_HYP(14) 357 __ERET 358 1: msr cpsr_c, \reg 359 2: 360 #else 361 /* 362 * workaround for possibly broken pre-v6 hardware 363 * (akita, Sharp Zaurus C-1000, PXA270-based) 364 */ 365 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg 366 #endif 367 .endm 368 369 /* 370 * STRT/LDRT access macros with ARM and Thumb-2 variants 371 */ 372 #ifdef CONFIG_THUMB2_KERNEL 373 374 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 375 9999: 376 .if \inc == 1 377 \instr\()b\t\cond\().w \reg, [\ptr, #\off] 378 .elseif \inc == 4 379 \instr\t\cond\().w \reg, [\ptr, #\off] 380 .else 381 .error "Unsupported inc macro argument" 382 .endif 383 384 .pushsection __ex_table,"a" 385 .align 3 386 .long 9999b, \abort 387 .popsection 388 .endm 389 390 .macro usracc, instr, reg, ptr, inc, cond, rept, abort 391 @ explicit IT instruction needed because of the label 392 @ introduced by the USER macro 393 .ifnc \cond,al 394 .if \rept == 1 395 itt \cond 396 .elseif \rept == 2 397 ittt \cond 398 .else 399 .error "Unsupported rept macro argument" 400 .endif 401 .endif 402 403 @ Slightly optimised to avoid incrementing the pointer twice 404 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 405 .if \rept == 2 406 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 407 .endif 408 409 add\cond \ptr, #\rept * \inc 410 .endm 411 412 #else /* !CONFIG_THUMB2_KERNEL */ 413 414 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 415 .rept \rept 416 9999: 417 .if \inc == 1 418 \instr\()b\t\cond \reg, [\ptr], #\inc 419 .elseif \inc == 4 420 \instr\t\cond \reg, [\ptr], #\inc 421 .else 422 .error "Unsupported inc macro argument" 423 .endif 424 425 .pushsection __ex_table,"a" 426 .align 3 427 .long 9999b, \abort 428 .popsection 429 .endr 430 .endm 431 432 #endif /* CONFIG_THUMB2_KERNEL */ 433 434 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 435 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 436 .endm 437 438 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 439 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 440 .endm 441 442 /* Utility macro for declaring string literals */ 443 .macro string name:req, string 444 .type \name , #object 445 \name: 446 .asciz "\string" 447 .size \name , . - \name 448 .endm 449 450 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 451 .macro ret\c, reg 452 #if __LINUX_ARM_ARCH__ < 6 453 mov\c pc, \reg 454 #else 455 .ifeqs "\reg", "lr" 456 bx\c \reg 457 .else 458 mov\c pc, \reg 459 .endif 460 #endif 461 .endm 462 .endr 463 464 .macro ret.w, reg 465 ret \reg 466 #ifdef CONFIG_THUMB2_KERNEL 467 nop 468 #endif 469 .endm 470 471 .macro bug, msg, line 472 #ifdef CONFIG_THUMB2_KERNEL 473 1: .inst 0xde02 474 #else 475 1: .inst 0xe7f001f2 476 #endif 477 #ifdef CONFIG_DEBUG_BUGVERBOSE 478 .pushsection .rodata.str, "aMS", %progbits, 1 479 2: .asciz "\msg" 480 .popsection 481 .pushsection __bug_table, "aw" 482 .align 2 483 .word 1b, 2b 484 .hword \line 485 .popsection 486 #endif 487 .endm 488 489 #ifdef CONFIG_KPROBES 490 #define _ASM_NOKPROBE(entry) \ 491 .pushsection "_kprobe_blacklist", "aw" ; \ 492 .balign 4 ; \ 493 .long entry; \ 494 .popsection 495 #else 496 #define _ASM_NOKPROBE(entry) 497 #endif 498 499 .macro __adldst_l, op, reg, sym, tmp, c 500 .if __LINUX_ARM_ARCH__ < 7 501 ldr\c \tmp, .La\@ 502 .subsection 1 503 .align 2 504 .La\@: .long \sym - .Lpc\@ 505 .previous 506 .else 507 .ifnb \c 508 THUMB( ittt \c ) 509 .endif 510 movw\c \tmp, #:lower16:\sym - .Lpc\@ 511 movt\c \tmp, #:upper16:\sym - .Lpc\@ 512 .endif 513 514 #ifndef CONFIG_THUMB2_KERNEL 515 .set .Lpc\@, . + 8 // PC bias 516 .ifc \op, add 517 add\c \reg, \tmp, pc 518 .else 519 \op\c \reg, [pc, \tmp] 520 .endif 521 #else 522 .Lb\@: add\c \tmp, \tmp, pc 523 /* 524 * In Thumb-2 builds, the PC bias depends on whether we are currently 525 * emitting into a .arm or a .thumb section. The size of the add opcode 526 * above will be 2 bytes when emitting in Thumb mode and 4 bytes when 527 * emitting in ARM mode, so let's use this to account for the bias. 528 */ 529 .set .Lpc\@, . + (. - .Lb\@) 530 531 .ifnc \op, add 532 \op\c \reg, [\tmp] 533 .endif 534 #endif 535 .endm 536 537 /* 538 * mov_l - move a constant value or [relocated] address into a register 539 */ 540 .macro mov_l, dst:req, imm:req 541 .if __LINUX_ARM_ARCH__ < 7 542 ldr \dst, =\imm 543 .else 544 movw \dst, #:lower16:\imm 545 movt \dst, #:upper16:\imm 546 .endif 547 .endm 548 549 /* 550 * adr_l - adr pseudo-op with unlimited range 551 * 552 * @dst: destination register 553 * @sym: name of the symbol 554 * @cond: conditional opcode suffix 555 */ 556 .macro adr_l, dst:req, sym:req, cond 557 __adldst_l add, \dst, \sym, \dst, \cond 558 .endm 559 560 /* 561 * ldr_l - ldr <literal> pseudo-op with unlimited range 562 * 563 * @dst: destination register 564 * @sym: name of the symbol 565 * @cond: conditional opcode suffix 566 */ 567 .macro ldr_l, dst:req, sym:req, cond 568 __adldst_l ldr, \dst, \sym, \dst, \cond 569 .endm 570 571 /* 572 * str_l - str <literal> pseudo-op with unlimited range 573 * 574 * @src: source register 575 * @sym: name of the symbol 576 * @tmp: mandatory scratch register 577 * @cond: conditional opcode suffix 578 */ 579 .macro str_l, src:req, sym:req, tmp:req, cond 580 __adldst_l str, \src, \sym, \tmp, \cond 581 .endm 582 583 /* 584 * rev_l - byte-swap a 32-bit value 585 * 586 * @val: source/destination register 587 * @tmp: scratch register 588 */ 589 .macro rev_l, val:req, tmp:req 590 .if __LINUX_ARM_ARCH__ < 6 591 eor \tmp, \val, \val, ror #16 592 bic \tmp, \tmp, #0x00ff0000 593 mov \val, \val, ror #8 594 eor \val, \val, \tmp, lsr #8 595 .else 596 rev \val, \val 597 .endif 598 .endm 599 600 #endif /* __ASM_ASSEMBLER_H__ */ 601