xref: /openbmc/linux/arch/arm/include/asm/assembler.h (revision 9a2b51b6) 
1 /*
2  *  arch/arm/include/asm/assembler.h
3  *
4  *  Copyright (C) 1996-2000 Russell King
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  *  This file contains arm architecture specific defines
11  *  for the different processors.
12  *
13  *  Do not include any C declarations in this file - it is included by
14  *  assembler source.
15  */
16 #ifndef __ASM_ASSEMBLER_H__
17 #define __ASM_ASSEMBLER_H__
18 
19 #ifndef __ASSEMBLY__
20 #error "Only include this from assembly code"
21 #endif
22 
23 #include <asm/ptrace.h>
24 #include <asm/domain.h>
25 #include <asm/opcodes-virt.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/page.h>
28 #include <asm/thread_info.h>
29 
30 #define IOMEM(x)	(x)
31 
32 /*
33  * Endian independent macros for shifting bytes within registers.
34  */
35 #ifndef __ARMEB__
36 #define lspull          lsr
37 #define lspush          lsl
38 #define get_byte_0      lsl #0
39 #define get_byte_1	lsr #8
40 #define get_byte_2	lsr #16
41 #define get_byte_3	lsr #24
42 #define put_byte_0      lsl #0
43 #define put_byte_1	lsl #8
44 #define put_byte_2	lsl #16
45 #define put_byte_3	lsl #24
46 #else
47 #define lspull          lsl
48 #define lspush          lsr
49 #define get_byte_0	lsr #24
50 #define get_byte_1	lsr #16
51 #define get_byte_2	lsr #8
52 #define get_byte_3      lsl #0
53 #define put_byte_0	lsl #24
54 #define put_byte_1	lsl #16
55 #define put_byte_2	lsl #8
56 #define put_byte_3      lsl #0
57 #endif
58 
59 /* Select code for any configuration running in BE8 mode */
60 #ifdef CONFIG_CPU_ENDIAN_BE8
61 #define ARM_BE8(code...) code
62 #else
63 #define ARM_BE8(code...)
64 #endif
65 
66 /*
67  * Data preload for architectures that support it
68  */
69 #if __LINUX_ARM_ARCH__ >= 5
70 #define PLD(code...)	code
71 #else
72 #define PLD(code...)
73 #endif
74 
75 /*
76  * This can be used to enable code to cacheline align the destination
77  * pointer when bulk writing to memory.  Experiments on StrongARM and
78  * XScale didn't show this a worthwhile thing to do when the cache is not
79  * set to write-allocate (this would need further testing on XScale when WA
80  * is used).
81  *
82  * On Feroceon there is much to gain however, regardless of cache mode.
83  */
84 #ifdef CONFIG_CPU_FEROCEON
85 #define CALGN(code...) code
86 #else
87 #define CALGN(code...)
88 #endif
89 
90 /*
91  * Enable and disable interrupts
92  */
93 #if __LINUX_ARM_ARCH__ >= 6
94 	.macro	disable_irq_notrace
95 	cpsid	i
96 	.endm
97 
98 	.macro	enable_irq_notrace
99 	cpsie	i
100 	.endm
101 #else
102 	.macro	disable_irq_notrace
103 	msr	cpsr_c, #PSR_I_BIT | SVC_MODE
104 	.endm
105 
106 	.macro	enable_irq_notrace
107 	msr	cpsr_c, #SVC_MODE
108 	.endm
109 #endif
110 
111 	.macro asm_trace_hardirqs_off
112 #if defined(CONFIG_TRACE_IRQFLAGS)
113 	stmdb   sp!, {r0-r3, ip, lr}
114 	bl	trace_hardirqs_off
115 	ldmia	sp!, {r0-r3, ip, lr}
116 #endif
117 	.endm
118 
119 	.macro asm_trace_hardirqs_on_cond, cond
120 #if defined(CONFIG_TRACE_IRQFLAGS)
121 	/*
122 	 * actually the registers should be pushed and pop'd conditionally, but
123 	 * after bl the flags are certainly clobbered
124 	 */
125 	stmdb   sp!, {r0-r3, ip, lr}
126 	bl\cond	trace_hardirqs_on
127 	ldmia	sp!, {r0-r3, ip, lr}
128 #endif
129 	.endm
130 
131 	.macro asm_trace_hardirqs_on
132 	asm_trace_hardirqs_on_cond al
133 	.endm
134 
135 	.macro disable_irq
136 	disable_irq_notrace
137 	asm_trace_hardirqs_off
138 	.endm
139 
140 	.macro enable_irq
141 	asm_trace_hardirqs_on
142 	enable_irq_notrace
143 	.endm
144 /*
145  * Save the current IRQ state and disable IRQs.  Note that this macro
146  * assumes FIQs are enabled, and that the processor is in SVC mode.
147  */
148 	.macro	save_and_disable_irqs, oldcpsr
149 #ifdef CONFIG_CPU_V7M
150 	mrs	\oldcpsr, primask
151 #else
152 	mrs	\oldcpsr, cpsr
153 #endif
154 	disable_irq
155 	.endm
156 
157 	.macro	save_and_disable_irqs_notrace, oldcpsr
158 	mrs	\oldcpsr, cpsr
159 	disable_irq_notrace
160 	.endm
161 
162 /*
163  * Restore interrupt state previously stored in a register.  We don't
164  * guarantee that this will preserve the flags.
165  */
166 	.macro	restore_irqs_notrace, oldcpsr
167 #ifdef CONFIG_CPU_V7M
168 	msr	primask, \oldcpsr
169 #else
170 	msr	cpsr_c, \oldcpsr
171 #endif
172 	.endm
173 
174 	.macro restore_irqs, oldcpsr
175 	tst	\oldcpsr, #PSR_I_BIT
176 	asm_trace_hardirqs_on_cond eq
177 	restore_irqs_notrace \oldcpsr
178 	.endm
179 
180 /*
181  * Get current thread_info.
182  */
183 	.macro	get_thread_info, rd
184  ARM(	mov	\rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT	)
185  THUMB(	mov	\rd, sp			)
186  THUMB(	lsr	\rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT	)
187 	mov	\rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT
188 	.endm
189 
190 /*
191  * Increment/decrement the preempt count.
192  */
193 #ifdef CONFIG_PREEMPT_COUNT
194 	.macro	inc_preempt_count, ti, tmp
195 	ldr	\tmp, [\ti, #TI_PREEMPT]	@ get preempt count
196 	add	\tmp, \tmp, #1			@ increment it
197 	str	\tmp, [\ti, #TI_PREEMPT]
198 	.endm
199 
200 	.macro	dec_preempt_count, ti, tmp
201 	ldr	\tmp, [\ti, #TI_PREEMPT]	@ get preempt count
202 	sub	\tmp, \tmp, #1			@ decrement it
203 	str	\tmp, [\ti, #TI_PREEMPT]
204 	.endm
205 
206 	.macro	dec_preempt_count_ti, ti, tmp
207 	get_thread_info \ti
208 	dec_preempt_count \ti, \tmp
209 	.endm
210 #else
211 	.macro	inc_preempt_count, ti, tmp
212 	.endm
213 
214 	.macro	dec_preempt_count, ti, tmp
215 	.endm
216 
217 	.macro	dec_preempt_count_ti, ti, tmp
218 	.endm
219 #endif
220 
221 #define USER(x...)				\
222 9999:	x;					\
223 	.pushsection __ex_table,"a";		\
224 	.align	3;				\
225 	.long	9999b,9001f;			\
226 	.popsection
227 
228 #ifdef CONFIG_SMP
229 #define ALT_SMP(instr...)					\
230 9998:	instr
231 /*
232  * Note: if you get assembler errors from ALT_UP() when building with
233  * CONFIG_THUMB2_KERNEL, you almost certainly need to use
234  * ALT_SMP( W(instr) ... )
235  */
236 #define ALT_UP(instr...)					\
237 	.pushsection ".alt.smp.init", "a"			;\
238 	.long	9998b						;\
239 9997:	instr							;\
240 	.if . - 9997b != 4					;\
241 		.error "ALT_UP() content must assemble to exactly 4 bytes";\
242 	.endif							;\
243 	.popsection
244 #define ALT_UP_B(label)					\
245 	.equ	up_b_offset, label - 9998b			;\
246 	.pushsection ".alt.smp.init", "a"			;\
247 	.long	9998b						;\
248 	W(b)	. + up_b_offset					;\
249 	.popsection
250 #else
251 #define ALT_SMP(instr...)
252 #define ALT_UP(instr...) instr
253 #define ALT_UP_B(label) b label
254 #endif
255 
256 /*
257  * Instruction barrier
258  */
259 	.macro	instr_sync
260 #if __LINUX_ARM_ARCH__ >= 7
261 	isb
262 #elif __LINUX_ARM_ARCH__ == 6
263 	mcr	p15, 0, r0, c7, c5, 4
264 #endif
265 	.endm
266 
267 /*
268  * SMP data memory barrier
269  */
270 	.macro	smp_dmb mode
271 #ifdef CONFIG_SMP
272 #if __LINUX_ARM_ARCH__ >= 7
273 	.ifeqs "\mode","arm"
274 	ALT_SMP(dmb	ish)
275 	.else
276 	ALT_SMP(W(dmb)	ish)
277 	.endif
278 #elif __LINUX_ARM_ARCH__ == 6
279 	ALT_SMP(mcr	p15, 0, r0, c7, c10, 5)	@ dmb
280 #else
281 #error Incompatible SMP platform
282 #endif
283 	.ifeqs "\mode","arm"
284 	ALT_UP(nop)
285 	.else
286 	ALT_UP(W(nop))
287 	.endif
288 #endif
289 	.endm
290 
291 #if defined(CONFIG_CPU_V7M)
292 	/*
293 	 * setmode is used to assert to be in svc mode during boot. For v7-M
294 	 * this is done in __v7m_setup, so setmode can be empty here.
295 	 */
296 	.macro	setmode, mode, reg
297 	.endm
298 #elif defined(CONFIG_THUMB2_KERNEL)
299 	.macro	setmode, mode, reg
300 	mov	\reg, #\mode
301 	msr	cpsr_c, \reg
302 	.endm
303 #else
304 	.macro	setmode, mode, reg
305 	msr	cpsr_c, #\mode
306 	.endm
307 #endif
308 
309 /*
310  * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
311  * a scratch register for the macro to overwrite.
312  *
313  * This macro is intended for forcing the CPU into SVC mode at boot time.
314  * you cannot return to the original mode.
315  */
316 .macro safe_svcmode_maskall reg:req
317 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
318 	mrs	\reg , cpsr
319 	eor	\reg, \reg, #HYP_MODE
320 	tst	\reg, #MODE_MASK
321 	bic	\reg , \reg , #MODE_MASK
322 	orr	\reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
323 THUMB(	orr	\reg , \reg , #PSR_T_BIT	)
324 	bne	1f
325 	orr	\reg, \reg, #PSR_A_BIT
326 	adr	lr, BSYM(2f)
327 	msr	spsr_cxsf, \reg
328 	__MSR_ELR_HYP(14)
329 	__ERET
330 1:	msr	cpsr_c, \reg
331 2:
332 #else
333 /*
334  * workaround for possibly broken pre-v6 hardware
335  * (akita, Sharp Zaurus C-1000, PXA270-based)
336  */
337 	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
338 #endif
339 .endm
340 
341 /*
342  * STRT/LDRT access macros with ARM and Thumb-2 variants
343  */
344 #ifdef CONFIG_THUMB2_KERNEL
345 
346 	.macro	usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
347 9999:
348 	.if	\inc == 1
349 	\instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
350 	.elseif	\inc == 4
351 	\instr\cond\()\t\().w \reg, [\ptr, #\off]
352 	.else
353 	.error	"Unsupported inc macro argument"
354 	.endif
355 
356 	.pushsection __ex_table,"a"
357 	.align	3
358 	.long	9999b, \abort
359 	.popsection
360 	.endm
361 
362 	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort
363 	@ explicit IT instruction needed because of the label
364 	@ introduced by the USER macro
365 	.ifnc	\cond,al
366 	.if	\rept == 1
367 	itt	\cond
368 	.elseif	\rept == 2
369 	ittt	\cond
370 	.else
371 	.error	"Unsupported rept macro argument"
372 	.endif
373 	.endif
374 
375 	@ Slightly optimised to avoid incrementing the pointer twice
376 	usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
377 	.if	\rept == 2
378 	usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
379 	.endif
380 
381 	add\cond \ptr, #\rept * \inc
382 	.endm
383 
384 #else	/* !CONFIG_THUMB2_KERNEL */
385 
386 	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
387 	.rept	\rept
388 9999:
389 	.if	\inc == 1
390 	\instr\cond\()b\()\t \reg, [\ptr], #\inc
391 	.elseif	\inc == 4
392 	\instr\cond\()\t \reg, [\ptr], #\inc
393 	.else
394 	.error	"Unsupported inc macro argument"
395 	.endif
396 
397 	.pushsection __ex_table,"a"
398 	.align	3
399 	.long	9999b, \abort
400 	.popsection
401 	.endr
402 	.endm
403 
404 #endif	/* CONFIG_THUMB2_KERNEL */
405 
406 	.macro	strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
407 	usracc	str, \reg, \ptr, \inc, \cond, \rept, \abort
408 	.endm
409 
410 	.macro	ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
411 	usracc	ldr, \reg, \ptr, \inc, \cond, \rept, \abort
412 	.endm
413 
414 /* Utility macro for declaring string literals */
415 	.macro	string name:req, string
416 	.type \name , #object
417 \name:
418 	.asciz "\string"
419 	.size \name , . - \name
420 	.endm
421 
422 	.macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
423 #ifndef CONFIG_CPU_USE_DOMAINS
424 	adds	\tmp, \addr, #\size - 1
425 	sbcccs	\tmp, \tmp, \limit
426 	bcs	\bad
427 #endif
428 	.endm
429 
430 #endif /* __ASM_ASSEMBLER_H__ */
431