1 /* 2 * arch/arm/include/asm/assembler.h 3 * 4 * Copyright (C) 1996-2000 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This file contains arm architecture specific defines 11 * for the different processors. 12 * 13 * Do not include any C declarations in this file - it is included by 14 * assembler source. 15 */ 16 #ifndef __ASM_ASSEMBLER_H__ 17 #define __ASM_ASSEMBLER_H__ 18 19 #ifndef __ASSEMBLY__ 20 #error "Only include this from assembly code" 21 #endif 22 23 #include <asm/ptrace.h> 24 #include <asm/domain.h> 25 26 #define IOMEM(x) (x) 27 28 /* 29 * Endian independent macros for shifting bytes within registers. 30 */ 31 #ifndef __ARMEB__ 32 #define pull lsr 33 #define push lsl 34 #define get_byte_0 lsl #0 35 #define get_byte_1 lsr #8 36 #define get_byte_2 lsr #16 37 #define get_byte_3 lsr #24 38 #define put_byte_0 lsl #0 39 #define put_byte_1 lsl #8 40 #define put_byte_2 lsl #16 41 #define put_byte_3 lsl #24 42 #else 43 #define pull lsl 44 #define push lsr 45 #define get_byte_0 lsr #24 46 #define get_byte_1 lsr #16 47 #define get_byte_2 lsr #8 48 #define get_byte_3 lsl #0 49 #define put_byte_0 lsl #24 50 #define put_byte_1 lsl #16 51 #define put_byte_2 lsl #8 52 #define put_byte_3 lsl #0 53 #endif 54 55 /* 56 * Data preload for architectures that support it 57 */ 58 #if __LINUX_ARM_ARCH__ >= 5 59 #define PLD(code...) code 60 #else 61 #define PLD(code...) 62 #endif 63 64 /* 65 * This can be used to enable code to cacheline align the destination 66 * pointer when bulk writing to memory. Experiments on StrongARM and 67 * XScale didn't show this a worthwhile thing to do when the cache is not 68 * set to write-allocate (this would need further testing on XScale when WA 69 * is used). 70 * 71 * On Feroceon there is much to gain however, regardless of cache mode. 72 */ 73 #ifdef CONFIG_CPU_FEROCEON 74 #define CALGN(code...) code 75 #else 76 #define CALGN(code...) 77 #endif 78 79 /* 80 * Enable and disable interrupts 81 */ 82 #if __LINUX_ARM_ARCH__ >= 6 83 .macro disable_irq_notrace 84 cpsid i 85 .endm 86 87 .macro enable_irq_notrace 88 cpsie i 89 .endm 90 #else 91 .macro disable_irq_notrace 92 msr cpsr_c, #PSR_I_BIT | SVC_MODE 93 .endm 94 95 .macro enable_irq_notrace 96 msr cpsr_c, #SVC_MODE 97 .endm 98 #endif 99 100 .macro asm_trace_hardirqs_off 101 #if defined(CONFIG_TRACE_IRQFLAGS) 102 stmdb sp!, {r0-r3, ip, lr} 103 bl trace_hardirqs_off 104 ldmia sp!, {r0-r3, ip, lr} 105 #endif 106 .endm 107 108 .macro asm_trace_hardirqs_on_cond, cond 109 #if defined(CONFIG_TRACE_IRQFLAGS) 110 /* 111 * actually the registers should be pushed and pop'd conditionally, but 112 * after bl the flags are certainly clobbered 113 */ 114 stmdb sp!, {r0-r3, ip, lr} 115 bl\cond trace_hardirqs_on 116 ldmia sp!, {r0-r3, ip, lr} 117 #endif 118 .endm 119 120 .macro asm_trace_hardirqs_on 121 asm_trace_hardirqs_on_cond al 122 .endm 123 124 .macro disable_irq 125 disable_irq_notrace 126 asm_trace_hardirqs_off 127 .endm 128 129 .macro enable_irq 130 asm_trace_hardirqs_on 131 enable_irq_notrace 132 .endm 133 /* 134 * Save the current IRQ state and disable IRQs. Note that this macro 135 * assumes FIQs are enabled, and that the processor is in SVC mode. 136 */ 137 .macro save_and_disable_irqs, oldcpsr 138 mrs \oldcpsr, cpsr 139 disable_irq 140 .endm 141 142 .macro save_and_disable_irqs_notrace, oldcpsr 143 mrs \oldcpsr, cpsr 144 disable_irq_notrace 145 .endm 146 147 /* 148 * Restore interrupt state previously stored in a register. We don't 149 * guarantee that this will preserve the flags. 150 */ 151 .macro restore_irqs_notrace, oldcpsr 152 msr cpsr_c, \oldcpsr 153 .endm 154 155 .macro restore_irqs, oldcpsr 156 tst \oldcpsr, #PSR_I_BIT 157 asm_trace_hardirqs_on_cond eq 158 restore_irqs_notrace \oldcpsr 159 .endm 160 161 #define USER(x...) \ 162 9999: x; \ 163 .pushsection __ex_table,"a"; \ 164 .align 3; \ 165 .long 9999b,9001f; \ 166 .popsection 167 168 #ifdef CONFIG_SMP 169 #define ALT_SMP(instr...) \ 170 9998: instr 171 /* 172 * Note: if you get assembler errors from ALT_UP() when building with 173 * CONFIG_THUMB2_KERNEL, you almost certainly need to use 174 * ALT_SMP( W(instr) ... ) 175 */ 176 #define ALT_UP(instr...) \ 177 .pushsection ".alt.smp.init", "a" ;\ 178 .long 9998b ;\ 179 9997: instr ;\ 180 .if . - 9997b != 4 ;\ 181 .error "ALT_UP() content must assemble to exactly 4 bytes";\ 182 .endif ;\ 183 .popsection 184 #define ALT_UP_B(label) \ 185 .equ up_b_offset, label - 9998b ;\ 186 .pushsection ".alt.smp.init", "a" ;\ 187 .long 9998b ;\ 188 W(b) . + up_b_offset ;\ 189 .popsection 190 #else 191 #define ALT_SMP(instr...) 192 #define ALT_UP(instr...) instr 193 #define ALT_UP_B(label) b label 194 #endif 195 196 /* 197 * Instruction barrier 198 */ 199 .macro instr_sync 200 #if __LINUX_ARM_ARCH__ >= 7 201 isb 202 #elif __LINUX_ARM_ARCH__ == 6 203 mcr p15, 0, r0, c7, c5, 4 204 #endif 205 .endm 206 207 /* 208 * SMP data memory barrier 209 */ 210 .macro smp_dmb mode 211 #ifdef CONFIG_SMP 212 #if __LINUX_ARM_ARCH__ >= 7 213 .ifeqs "\mode","arm" 214 ALT_SMP(dmb) 215 .else 216 ALT_SMP(W(dmb)) 217 .endif 218 #elif __LINUX_ARM_ARCH__ == 6 219 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 220 #else 221 #error Incompatible SMP platform 222 #endif 223 .ifeqs "\mode","arm" 224 ALT_UP(nop) 225 .else 226 ALT_UP(W(nop)) 227 .endif 228 #endif 229 .endm 230 231 #ifdef CONFIG_THUMB2_KERNEL 232 .macro setmode, mode, reg 233 mov \reg, #\mode 234 msr cpsr_c, \reg 235 .endm 236 #else 237 .macro setmode, mode, reg 238 msr cpsr_c, #\mode 239 .endm 240 #endif 241 242 /* 243 * STRT/LDRT access macros with ARM and Thumb-2 variants 244 */ 245 #ifdef CONFIG_THUMB2_KERNEL 246 247 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 248 9999: 249 .if \inc == 1 250 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] 251 .elseif \inc == 4 252 \instr\cond\()\t\().w \reg, [\ptr, #\off] 253 .else 254 .error "Unsupported inc macro argument" 255 .endif 256 257 .pushsection __ex_table,"a" 258 .align 3 259 .long 9999b, \abort 260 .popsection 261 .endm 262 263 .macro usracc, instr, reg, ptr, inc, cond, rept, abort 264 @ explicit IT instruction needed because of the label 265 @ introduced by the USER macro 266 .ifnc \cond,al 267 .if \rept == 1 268 itt \cond 269 .elseif \rept == 2 270 ittt \cond 271 .else 272 .error "Unsupported rept macro argument" 273 .endif 274 .endif 275 276 @ Slightly optimised to avoid incrementing the pointer twice 277 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 278 .if \rept == 2 279 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 280 .endif 281 282 add\cond \ptr, #\rept * \inc 283 .endm 284 285 #else /* !CONFIG_THUMB2_KERNEL */ 286 287 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 288 .rept \rept 289 9999: 290 .if \inc == 1 291 \instr\cond\()b\()\t \reg, [\ptr], #\inc 292 .elseif \inc == 4 293 \instr\cond\()\t \reg, [\ptr], #\inc 294 .else 295 .error "Unsupported inc macro argument" 296 .endif 297 298 .pushsection __ex_table,"a" 299 .align 3 300 .long 9999b, \abort 301 .popsection 302 .endr 303 .endm 304 305 #endif /* CONFIG_THUMB2_KERNEL */ 306 307 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 308 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 309 .endm 310 311 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 312 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 313 .endm 314 315 /* Utility macro for declaring string literals */ 316 .macro string name:req, string 317 .type \name , #object 318 \name: 319 .asciz "\string" 320 .size \name , . - \name 321 .endm 322 323 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req 324 #ifndef CONFIG_CPU_USE_DOMAINS 325 adds \tmp, \addr, #\size - 1 326 sbcccs \tmp, \tmp, \limit 327 bcs \bad 328 #endif 329 .endm 330 331 #endif /* __ASM_ASSEMBLER_H__ */ 332