1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * arch/arm/include/asm/assembler.h 4 * 5 * Copyright (C) 1996-2000 Russell King 6 * 7 * This file contains arm architecture specific defines 8 * for the different processors. 9 * 10 * Do not include any C declarations in this file - it is included by 11 * assembler source. 12 */ 13 #ifndef __ASM_ASSEMBLER_H__ 14 #define __ASM_ASSEMBLER_H__ 15 16 #ifndef __ASSEMBLY__ 17 #error "Only include this from assembly code" 18 #endif 19 20 #include <asm/ptrace.h> 21 #include <asm/opcodes-virt.h> 22 #include <asm/asm-offsets.h> 23 #include <asm/page.h> 24 #include <asm/thread_info.h> 25 #include <asm/uaccess-asm.h> 26 27 #define IOMEM(x) (x) 28 29 /* 30 * Endian independent macros for shifting bytes within registers. 31 */ 32 #ifndef __ARMEB__ 33 #define lspull lsr 34 #define lspush lsl 35 #define get_byte_0 lsl #0 36 #define get_byte_1 lsr #8 37 #define get_byte_2 lsr #16 38 #define get_byte_3 lsr #24 39 #define put_byte_0 lsl #0 40 #define put_byte_1 lsl #8 41 #define put_byte_2 lsl #16 42 #define put_byte_3 lsl #24 43 #else 44 #define lspull lsl 45 #define lspush lsr 46 #define get_byte_0 lsr #24 47 #define get_byte_1 lsr #16 48 #define get_byte_2 lsr #8 49 #define get_byte_3 lsl #0 50 #define put_byte_0 lsl #24 51 #define put_byte_1 lsl #16 52 #define put_byte_2 lsl #8 53 #define put_byte_3 lsl #0 54 #endif 55 56 /* Select code for any configuration running in BE8 mode */ 57 #ifdef CONFIG_CPU_ENDIAN_BE8 58 #define ARM_BE8(code...) code 59 #else 60 #define ARM_BE8(code...) 61 #endif 62 63 /* 64 * Data preload for architectures that support it 65 */ 66 #if __LINUX_ARM_ARCH__ >= 5 67 #define PLD(code...) code 68 #else 69 #define PLD(code...) 70 #endif 71 72 /* 73 * This can be used to enable code to cacheline align the destination 74 * pointer when bulk writing to memory. Experiments on StrongARM and 75 * XScale didn't show this a worthwhile thing to do when the cache is not 76 * set to write-allocate (this would need further testing on XScale when WA 77 * is used). 78 * 79 * On Feroceon there is much to gain however, regardless of cache mode. 80 */ 81 #ifdef CONFIG_CPU_FEROCEON 82 #define CALGN(code...) code 83 #else 84 #define CALGN(code...) 85 #endif 86 87 #define IMM12_MASK 0xfff 88 89 /* the frame pointer used for stack unwinding */ 90 ARM( fpreg .req r11 ) 91 THUMB( fpreg .req r7 ) 92 93 /* 94 * Enable and disable interrupts 95 */ 96 #if __LINUX_ARM_ARCH__ >= 6 97 .macro disable_irq_notrace 98 cpsid i 99 .endm 100 101 .macro enable_irq_notrace 102 cpsie i 103 .endm 104 #else 105 .macro disable_irq_notrace 106 msr cpsr_c, #PSR_I_BIT | SVC_MODE 107 .endm 108 109 .macro enable_irq_notrace 110 msr cpsr_c, #SVC_MODE 111 .endm 112 #endif 113 114 .macro asm_trace_hardirqs_off, save=1 115 #if defined(CONFIG_TRACE_IRQFLAGS) 116 .if \save 117 stmdb sp!, {r0-r3, ip, lr} 118 .endif 119 bl trace_hardirqs_off 120 .if \save 121 ldmia sp!, {r0-r3, ip, lr} 122 .endif 123 #endif 124 .endm 125 126 .macro asm_trace_hardirqs_on, cond=al, save=1 127 #if defined(CONFIG_TRACE_IRQFLAGS) 128 /* 129 * actually the registers should be pushed and pop'd conditionally, but 130 * after bl the flags are certainly clobbered 131 */ 132 .if \save 133 stmdb sp!, {r0-r3, ip, lr} 134 .endif 135 bl\cond trace_hardirqs_on 136 .if \save 137 ldmia sp!, {r0-r3, ip, lr} 138 .endif 139 #endif 140 .endm 141 142 .macro disable_irq, save=1 143 disable_irq_notrace 144 asm_trace_hardirqs_off \save 145 .endm 146 147 .macro enable_irq 148 asm_trace_hardirqs_on 149 enable_irq_notrace 150 .endm 151 /* 152 * Save the current IRQ state and disable IRQs. Note that this macro 153 * assumes FIQs are enabled, and that the processor is in SVC mode. 154 */ 155 .macro save_and_disable_irqs, oldcpsr 156 #ifdef CONFIG_CPU_V7M 157 mrs \oldcpsr, primask 158 #else 159 mrs \oldcpsr, cpsr 160 #endif 161 disable_irq 162 .endm 163 164 .macro save_and_disable_irqs_notrace, oldcpsr 165 #ifdef CONFIG_CPU_V7M 166 mrs \oldcpsr, primask 167 #else 168 mrs \oldcpsr, cpsr 169 #endif 170 disable_irq_notrace 171 .endm 172 173 /* 174 * Restore interrupt state previously stored in a register. We don't 175 * guarantee that this will preserve the flags. 176 */ 177 .macro restore_irqs_notrace, oldcpsr 178 #ifdef CONFIG_CPU_V7M 179 msr primask, \oldcpsr 180 #else 181 msr cpsr_c, \oldcpsr 182 #endif 183 .endm 184 185 .macro restore_irqs, oldcpsr 186 tst \oldcpsr, #PSR_I_BIT 187 asm_trace_hardirqs_on cond=eq 188 restore_irqs_notrace \oldcpsr 189 .endm 190 191 /* 192 * Assembly version of "adr rd, BSYM(sym)". This should only be used to 193 * reference local symbols in the same assembly file which are to be 194 * resolved by the assembler. Other usage is undefined. 195 */ 196 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 197 .macro badr\c, rd, sym 198 #ifdef CONFIG_THUMB2_KERNEL 199 adr\c \rd, \sym + 1 200 #else 201 adr\c \rd, \sym 202 #endif 203 .endm 204 .endr 205 206 .macro get_current, rd 207 #ifdef CONFIG_CURRENT_POINTER_IN_TPIDRURO 208 mrc p15, 0, \rd, c13, c0, 3 @ get TPIDRURO register 209 #else 210 get_thread_info \rd 211 ldr \rd, [\rd, #TI_TASK] 212 #endif 213 .endm 214 215 .macro set_current, rn 216 #ifdef CONFIG_CURRENT_POINTER_IN_TPIDRURO 217 mcr p15, 0, \rn, c13, c0, 3 @ set TPIDRURO register 218 #endif 219 .endm 220 221 .macro reload_current, t1:req, t2:req 222 #ifdef CONFIG_CURRENT_POINTER_IN_TPIDRURO 223 ldr_this_cpu \t1, __entry_task, \t1, \t2 224 mcr p15, 0, \t1, c13, c0, 3 @ store in TPIDRURO 225 #endif 226 .endm 227 228 /* 229 * Get current thread_info. 230 */ 231 .macro get_thread_info, rd 232 #ifdef CONFIG_THREAD_INFO_IN_TASK 233 /* thread_info is the first member of struct task_struct */ 234 get_current \rd 235 #else 236 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT ) 237 THUMB( mov \rd, sp ) 238 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT ) 239 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT 240 #endif 241 .endm 242 243 /* 244 * Increment/decrement the preempt count. 245 */ 246 #ifdef CONFIG_PREEMPT_COUNT 247 .macro inc_preempt_count, ti, tmp 248 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 249 add \tmp, \tmp, #1 @ increment it 250 str \tmp, [\ti, #TI_PREEMPT] 251 .endm 252 253 .macro dec_preempt_count, ti, tmp 254 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 255 sub \tmp, \tmp, #1 @ decrement it 256 str \tmp, [\ti, #TI_PREEMPT] 257 .endm 258 259 .macro dec_preempt_count_ti, ti, tmp 260 get_thread_info \ti 261 dec_preempt_count \ti, \tmp 262 .endm 263 #else 264 .macro inc_preempt_count, ti, tmp 265 .endm 266 267 .macro dec_preempt_count, ti, tmp 268 .endm 269 270 .macro dec_preempt_count_ti, ti, tmp 271 .endm 272 #endif 273 274 #define USERL(l, x...) \ 275 9999: x; \ 276 .pushsection __ex_table,"a"; \ 277 .align 3; \ 278 .long 9999b,l; \ 279 .popsection 280 281 #define USER(x...) USERL(9001f, x) 282 283 #ifdef CONFIG_SMP 284 #define ALT_SMP(instr...) \ 285 9998: instr 286 /* 287 * Note: if you get assembler errors from ALT_UP() when building with 288 * CONFIG_THUMB2_KERNEL, you almost certainly need to use 289 * ALT_SMP( W(instr) ... ) 290 */ 291 #define ALT_UP(instr...) \ 292 .pushsection ".alt.smp.init", "a" ;\ 293 .long 9998b - . ;\ 294 9997: instr ;\ 295 .if . - 9997b == 2 ;\ 296 nop ;\ 297 .endif ;\ 298 .if . - 9997b != 4 ;\ 299 .error "ALT_UP() content must assemble to exactly 4 bytes";\ 300 .endif ;\ 301 .popsection 302 #define ALT_UP_B(label) \ 303 .pushsection ".alt.smp.init", "a" ;\ 304 .long 9998b - . ;\ 305 W(b) . + (label - 9998b) ;\ 306 .popsection 307 #else 308 #define ALT_SMP(instr...) 309 #define ALT_UP(instr...) instr 310 #define ALT_UP_B(label) b label 311 #endif 312 313 /* 314 * this_cpu_offset - load the per-CPU offset of this CPU into 315 * register 'rd' 316 */ 317 .macro this_cpu_offset, rd:req 318 #ifdef CONFIG_SMP 319 ALT_SMP(mrc p15, 0, \rd, c13, c0, 4) 320 #ifdef CONFIG_CPU_V6 321 ALT_UP_B(.L1_\@) 322 .L0_\@: 323 .subsection 1 324 .L1_\@: ldr_va \rd, __per_cpu_offset 325 b .L0_\@ 326 .previous 327 #endif 328 #else 329 mov \rd, #0 330 #endif 331 .endm 332 333 /* 334 * Instruction barrier 335 */ 336 .macro instr_sync 337 #if __LINUX_ARM_ARCH__ >= 7 338 isb 339 #elif __LINUX_ARM_ARCH__ == 6 340 mcr p15, 0, r0, c7, c5, 4 341 #endif 342 .endm 343 344 /* 345 * SMP data memory barrier 346 */ 347 .macro smp_dmb mode 348 #ifdef CONFIG_SMP 349 #if __LINUX_ARM_ARCH__ >= 7 350 .ifeqs "\mode","arm" 351 ALT_SMP(dmb ish) 352 .else 353 ALT_SMP(W(dmb) ish) 354 .endif 355 #elif __LINUX_ARM_ARCH__ == 6 356 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 357 #else 358 #error Incompatible SMP platform 359 #endif 360 .ifeqs "\mode","arm" 361 ALT_UP(nop) 362 .else 363 ALT_UP(W(nop)) 364 .endif 365 #endif 366 .endm 367 368 #if defined(CONFIG_CPU_V7M) 369 /* 370 * setmode is used to assert to be in svc mode during boot. For v7-M 371 * this is done in __v7m_setup, so setmode can be empty here. 372 */ 373 .macro setmode, mode, reg 374 .endm 375 #elif defined(CONFIG_THUMB2_KERNEL) 376 .macro setmode, mode, reg 377 mov \reg, #\mode 378 msr cpsr_c, \reg 379 .endm 380 #else 381 .macro setmode, mode, reg 382 msr cpsr_c, #\mode 383 .endm 384 #endif 385 386 /* 387 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is 388 * a scratch register for the macro to overwrite. 389 * 390 * This macro is intended for forcing the CPU into SVC mode at boot time. 391 * you cannot return to the original mode. 392 */ 393 .macro safe_svcmode_maskall reg:req 394 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M) 395 mrs \reg , cpsr 396 eor \reg, \reg, #HYP_MODE 397 tst \reg, #MODE_MASK 398 bic \reg , \reg , #MODE_MASK 399 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE 400 THUMB( orr \reg , \reg , #PSR_T_BIT ) 401 bne 1f 402 orr \reg, \reg, #PSR_A_BIT 403 badr lr, 2f 404 msr spsr_cxsf, \reg 405 __MSR_ELR_HYP(14) 406 __ERET 407 1: msr cpsr_c, \reg 408 2: 409 #else 410 /* 411 * workaround for possibly broken pre-v6 hardware 412 * (akita, Sharp Zaurus C-1000, PXA270-based) 413 */ 414 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg 415 #endif 416 .endm 417 418 /* 419 * STRT/LDRT access macros with ARM and Thumb-2 variants 420 */ 421 #ifdef CONFIG_THUMB2_KERNEL 422 423 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 424 9999: 425 .if \inc == 1 426 \instr\()b\t\cond\().w \reg, [\ptr, #\off] 427 .elseif \inc == 4 428 \instr\t\cond\().w \reg, [\ptr, #\off] 429 .else 430 .error "Unsupported inc macro argument" 431 .endif 432 433 .pushsection __ex_table,"a" 434 .align 3 435 .long 9999b, \abort 436 .popsection 437 .endm 438 439 .macro usracc, instr, reg, ptr, inc, cond, rept, abort 440 @ explicit IT instruction needed because of the label 441 @ introduced by the USER macro 442 .ifnc \cond,al 443 .if \rept == 1 444 itt \cond 445 .elseif \rept == 2 446 ittt \cond 447 .else 448 .error "Unsupported rept macro argument" 449 .endif 450 .endif 451 452 @ Slightly optimised to avoid incrementing the pointer twice 453 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 454 .if \rept == 2 455 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 456 .endif 457 458 add\cond \ptr, #\rept * \inc 459 .endm 460 461 #else /* !CONFIG_THUMB2_KERNEL */ 462 463 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 464 .rept \rept 465 9999: 466 .if \inc == 1 467 \instr\()b\t\cond \reg, [\ptr], #\inc 468 .elseif \inc == 4 469 \instr\t\cond \reg, [\ptr], #\inc 470 .else 471 .error "Unsupported inc macro argument" 472 .endif 473 474 .pushsection __ex_table,"a" 475 .align 3 476 .long 9999b, \abort 477 .popsection 478 .endr 479 .endm 480 481 #endif /* CONFIG_THUMB2_KERNEL */ 482 483 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 484 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 485 .endm 486 487 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 488 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 489 .endm 490 491 /* Utility macro for declaring string literals */ 492 .macro string name:req, string 493 .type \name , #object 494 \name: 495 .asciz "\string" 496 .size \name , . - \name 497 .endm 498 499 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 500 .macro ret\c, reg 501 #if __LINUX_ARM_ARCH__ < 6 502 mov\c pc, \reg 503 #else 504 .ifeqs "\reg", "lr" 505 bx\c \reg 506 .else 507 mov\c pc, \reg 508 .endif 509 #endif 510 .endm 511 .endr 512 513 .macro ret.w, reg 514 ret \reg 515 #ifdef CONFIG_THUMB2_KERNEL 516 nop 517 #endif 518 .endm 519 520 .macro bug, msg, line 521 #ifdef CONFIG_THUMB2_KERNEL 522 1: .inst 0xde02 523 #else 524 1: .inst 0xe7f001f2 525 #endif 526 #ifdef CONFIG_DEBUG_BUGVERBOSE 527 .pushsection .rodata.str, "aMS", %progbits, 1 528 2: .asciz "\msg" 529 .popsection 530 .pushsection __bug_table, "aw" 531 .align 2 532 .word 1b, 2b 533 .hword \line 534 .popsection 535 #endif 536 .endm 537 538 #ifdef CONFIG_KPROBES 539 #define _ASM_NOKPROBE(entry) \ 540 .pushsection "_kprobe_blacklist", "aw" ; \ 541 .balign 4 ; \ 542 .long entry; \ 543 .popsection 544 #else 545 #define _ASM_NOKPROBE(entry) 546 #endif 547 548 .macro __adldst_l, op, reg, sym, tmp, c 549 .if __LINUX_ARM_ARCH__ < 7 550 ldr\c \tmp, .La\@ 551 .subsection 1 552 .align 2 553 .La\@: .long \sym - .Lpc\@ 554 .previous 555 .else 556 .ifnb \c 557 THUMB( ittt \c ) 558 .endif 559 movw\c \tmp, #:lower16:\sym - .Lpc\@ 560 movt\c \tmp, #:upper16:\sym - .Lpc\@ 561 .endif 562 563 #ifndef CONFIG_THUMB2_KERNEL 564 .set .Lpc\@, . + 8 // PC bias 565 .ifc \op, add 566 add\c \reg, \tmp, pc 567 .else 568 \op\c \reg, [pc, \tmp] 569 .endif 570 #else 571 .Lb\@: add\c \tmp, \tmp, pc 572 /* 573 * In Thumb-2 builds, the PC bias depends on whether we are currently 574 * emitting into a .arm or a .thumb section. The size of the add opcode 575 * above will be 2 bytes when emitting in Thumb mode and 4 bytes when 576 * emitting in ARM mode, so let's use this to account for the bias. 577 */ 578 .set .Lpc\@, . + (. - .Lb\@) 579 580 .ifnc \op, add 581 \op\c \reg, [\tmp] 582 .endif 583 #endif 584 .endm 585 586 /* 587 * mov_l - move a constant value or [relocated] address into a register 588 */ 589 .macro mov_l, dst:req, imm:req, cond 590 .if __LINUX_ARM_ARCH__ < 7 591 ldr\cond \dst, =\imm 592 .else 593 movw\cond \dst, #:lower16:\imm 594 movt\cond \dst, #:upper16:\imm 595 .endif 596 .endm 597 598 /* 599 * adr_l - adr pseudo-op with unlimited range 600 * 601 * @dst: destination register 602 * @sym: name of the symbol 603 * @cond: conditional opcode suffix 604 */ 605 .macro adr_l, dst:req, sym:req, cond 606 __adldst_l add, \dst, \sym, \dst, \cond 607 .endm 608 609 /* 610 * ldr_l - ldr <literal> pseudo-op with unlimited range 611 * 612 * @dst: destination register 613 * @sym: name of the symbol 614 * @cond: conditional opcode suffix 615 */ 616 .macro ldr_l, dst:req, sym:req, cond 617 __adldst_l ldr, \dst, \sym, \dst, \cond 618 .endm 619 620 /* 621 * str_l - str <literal> pseudo-op with unlimited range 622 * 623 * @src: source register 624 * @sym: name of the symbol 625 * @tmp: mandatory scratch register 626 * @cond: conditional opcode suffix 627 */ 628 .macro str_l, src:req, sym:req, tmp:req, cond 629 __adldst_l str, \src, \sym, \tmp, \cond 630 .endm 631 632 .macro __ldst_va, op, reg, tmp, sym, cond 633 #if __LINUX_ARM_ARCH__ >= 7 || \ 634 (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS)) || \ 635 (defined(CONFIG_LD_IS_LLD) && CONFIG_LLD_VERSION < 140000) 636 mov_l \tmp, \sym, \cond 637 \op\cond \reg, [\tmp] 638 #else 639 /* 640 * Avoid a literal load, by emitting a sequence of ADD/LDR instructions 641 * with the appropriate relocations. The combined sequence has a range 642 * of -/+ 256 MiB, which should be sufficient for the core kernel and 643 * for modules loaded into the module region. 644 */ 645 .globl \sym 646 .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym 647 .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym 648 .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym 649 .L0_\@: sub\cond \tmp, pc, #8 650 .L1_\@: sub\cond \tmp, \tmp, #4 651 .L2_\@: \op\cond \reg, [\tmp, #0] 652 #endif 653 .endm 654 655 /* 656 * ldr_va - load a 32-bit word from the virtual address of \sym 657 */ 658 .macro ldr_va, rd:req, sym:req, cond 659 __ldst_va ldr, \rd, \rd, \sym, \cond 660 .endm 661 662 /* 663 * str_va - store a 32-bit word to the virtual address of \sym 664 */ 665 .macro str_va, rn:req, sym:req, tmp:req, cond 666 __ldst_va str, \rn, \tmp, \sym, \cond 667 .endm 668 669 /* 670 * ldr_this_cpu_armv6 - Load a 32-bit word from the per-CPU variable 'sym', 671 * without using a temp register. Supported in ARM mode 672 * only. 673 */ 674 .macro ldr_this_cpu_armv6, rd:req, sym:req 675 this_cpu_offset \rd 676 .globl \sym 677 .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym 678 .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym 679 .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym 680 add \rd, \rd, pc 681 .L0_\@: sub \rd, \rd, #4 682 .L1_\@: sub \rd, \rd, #0 683 .L2_\@: ldr \rd, [\rd, #4] 684 .endm 685 686 /* 687 * ldr_this_cpu - Load a 32-bit word from the per-CPU variable 'sym' 688 * into register 'rd', which may be the stack pointer, 689 * using 't1' and 't2' as general temp registers. These 690 * are permitted to overlap with 'rd' if != sp 691 */ 692 .macro ldr_this_cpu, rd:req, sym:req, t1:req, t2:req 693 #if __LINUX_ARM_ARCH__ >= 7 || \ 694 (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS)) || \ 695 (defined(CONFIG_LD_IS_LLD) && CONFIG_LLD_VERSION < 140000) 696 this_cpu_offset \t1 697 mov_l \t2, \sym 698 ldr \rd, [\t1, \t2] 699 #else 700 ldr_this_cpu_armv6 \rd, \sym 701 #endif 702 .endm 703 704 /* 705 * rev_l - byte-swap a 32-bit value 706 * 707 * @val: source/destination register 708 * @tmp: scratch register 709 */ 710 .macro rev_l, val:req, tmp:req 711 .if __LINUX_ARM_ARCH__ < 6 712 eor \tmp, \val, \val, ror #16 713 bic \tmp, \tmp, #0x00ff0000 714 mov \val, \val, ror #8 715 eor \val, \val, \tmp, lsr #8 716 .else 717 rev \val, \val 718 .endif 719 .endm 720 721 /* 722 * bl_r - branch and link to register 723 * 724 * @dst: target to branch to 725 * @c: conditional opcode suffix 726 */ 727 .macro bl_r, dst:req, c 728 .if __LINUX_ARM_ARCH__ < 6 729 mov\c lr, pc 730 mov\c pc, \dst 731 .else 732 blx\c \dst 733 .endif 734 .endm 735 736 #endif /* __ASM_ASSEMBLER_H__ */ 737