1 /* 2 * arch/arm/include/asm/assembler.h 3 * 4 * Copyright (C) 1996-2000 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This file contains arm architecture specific defines 11 * for the different processors. 12 * 13 * Do not include any C declarations in this file - it is included by 14 * assembler source. 15 */ 16 #ifndef __ASM_ASSEMBLER_H__ 17 #define __ASM_ASSEMBLER_H__ 18 19 #ifndef __ASSEMBLY__ 20 #error "Only include this from assembly code" 21 #endif 22 23 #include <asm/ptrace.h> 24 #include <asm/domain.h> 25 26 #define IOMEM(x) (x) 27 28 /* 29 * Endian independent macros for shifting bytes within registers. 30 */ 31 #ifndef __ARMEB__ 32 #define pull lsr 33 #define push lsl 34 #define get_byte_0 lsl #0 35 #define get_byte_1 lsr #8 36 #define get_byte_2 lsr #16 37 #define get_byte_3 lsr #24 38 #define put_byte_0 lsl #0 39 #define put_byte_1 lsl #8 40 #define put_byte_2 lsl #16 41 #define put_byte_3 lsl #24 42 #else 43 #define pull lsl 44 #define push lsr 45 #define get_byte_0 lsr #24 46 #define get_byte_1 lsr #16 47 #define get_byte_2 lsr #8 48 #define get_byte_3 lsl #0 49 #define put_byte_0 lsl #24 50 #define put_byte_1 lsl #16 51 #define put_byte_2 lsl #8 52 #define put_byte_3 lsl #0 53 #endif 54 55 /* 56 * Data preload for architectures that support it 57 */ 58 #if __LINUX_ARM_ARCH__ >= 5 59 #define PLD(code...) code 60 #else 61 #define PLD(code...) 62 #endif 63 64 /* 65 * This can be used to enable code to cacheline align the destination 66 * pointer when bulk writing to memory. Experiments on StrongARM and 67 * XScale didn't show this a worthwhile thing to do when the cache is not 68 * set to write-allocate (this would need further testing on XScale when WA 69 * is used). 70 * 71 * On Feroceon there is much to gain however, regardless of cache mode. 72 */ 73 #ifdef CONFIG_CPU_FEROCEON 74 #define CALGN(code...) code 75 #else 76 #define CALGN(code...) 77 #endif 78 79 /* 80 * Enable and disable interrupts 81 */ 82 #if __LINUX_ARM_ARCH__ >= 6 83 .macro disable_irq_notrace 84 cpsid i 85 .endm 86 87 .macro enable_irq_notrace 88 cpsie i 89 .endm 90 #else 91 .macro disable_irq_notrace 92 msr cpsr_c, #PSR_I_BIT | SVC_MODE 93 .endm 94 95 .macro enable_irq_notrace 96 msr cpsr_c, #SVC_MODE 97 .endm 98 #endif 99 100 .macro asm_trace_hardirqs_off 101 #if defined(CONFIG_TRACE_IRQFLAGS) 102 stmdb sp!, {r0-r3, ip, lr} 103 bl trace_hardirqs_off 104 ldmia sp!, {r0-r3, ip, lr} 105 #endif 106 .endm 107 108 .macro asm_trace_hardirqs_on_cond, cond 109 #if defined(CONFIG_TRACE_IRQFLAGS) 110 /* 111 * actually the registers should be pushed and pop'd conditionally, but 112 * after bl the flags are certainly clobbered 113 */ 114 stmdb sp!, {r0-r3, ip, lr} 115 bl\cond trace_hardirqs_on 116 ldmia sp!, {r0-r3, ip, lr} 117 #endif 118 .endm 119 120 .macro asm_trace_hardirqs_on 121 asm_trace_hardirqs_on_cond al 122 .endm 123 124 .macro disable_irq 125 disable_irq_notrace 126 asm_trace_hardirqs_off 127 .endm 128 129 .macro enable_irq 130 asm_trace_hardirqs_on 131 enable_irq_notrace 132 .endm 133 /* 134 * Save the current IRQ state and disable IRQs. Note that this macro 135 * assumes FIQs are enabled, and that the processor is in SVC mode. 136 */ 137 .macro save_and_disable_irqs, oldcpsr 138 mrs \oldcpsr, cpsr 139 disable_irq 140 .endm 141 142 /* 143 * Restore interrupt state previously stored in a register. We don't 144 * guarantee that this will preserve the flags. 145 */ 146 .macro restore_irqs_notrace, oldcpsr 147 msr cpsr_c, \oldcpsr 148 .endm 149 150 .macro restore_irqs, oldcpsr 151 tst \oldcpsr, #PSR_I_BIT 152 asm_trace_hardirqs_on_cond eq 153 restore_irqs_notrace \oldcpsr 154 .endm 155 156 #define USER(x...) \ 157 9999: x; \ 158 .pushsection __ex_table,"a"; \ 159 .align 3; \ 160 .long 9999b,9001f; \ 161 .popsection 162 163 #ifdef CONFIG_SMP 164 #define ALT_SMP(instr...) \ 165 9998: instr 166 /* 167 * Note: if you get assembler errors from ALT_UP() when building with 168 * CONFIG_THUMB2_KERNEL, you almost certainly need to use 169 * ALT_SMP( W(instr) ... ) 170 */ 171 #define ALT_UP(instr...) \ 172 .pushsection ".alt.smp.init", "a" ;\ 173 .long 9998b ;\ 174 9997: instr ;\ 175 .if . - 9997b != 4 ;\ 176 .error "ALT_UP() content must assemble to exactly 4 bytes";\ 177 .endif ;\ 178 .popsection 179 #define ALT_UP_B(label) \ 180 .equ up_b_offset, label - 9998b ;\ 181 .pushsection ".alt.smp.init", "a" ;\ 182 .long 9998b ;\ 183 W(b) . + up_b_offset ;\ 184 .popsection 185 #else 186 #define ALT_SMP(instr...) 187 #define ALT_UP(instr...) instr 188 #define ALT_UP_B(label) b label 189 #endif 190 191 /* 192 * Instruction barrier 193 */ 194 .macro instr_sync 195 #if __LINUX_ARM_ARCH__ >= 7 196 isb 197 #elif __LINUX_ARM_ARCH__ == 6 198 mcr p15, 0, r0, c7, c5, 4 199 #endif 200 .endm 201 202 /* 203 * SMP data memory barrier 204 */ 205 .macro smp_dmb mode 206 #ifdef CONFIG_SMP 207 #if __LINUX_ARM_ARCH__ >= 7 208 .ifeqs "\mode","arm" 209 ALT_SMP(dmb) 210 .else 211 ALT_SMP(W(dmb)) 212 .endif 213 #elif __LINUX_ARM_ARCH__ == 6 214 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 215 #else 216 #error Incompatible SMP platform 217 #endif 218 .ifeqs "\mode","arm" 219 ALT_UP(nop) 220 .else 221 ALT_UP(W(nop)) 222 .endif 223 #endif 224 .endm 225 226 #ifdef CONFIG_THUMB2_KERNEL 227 .macro setmode, mode, reg 228 mov \reg, #\mode 229 msr cpsr_c, \reg 230 .endm 231 #else 232 .macro setmode, mode, reg 233 msr cpsr_c, #\mode 234 .endm 235 #endif 236 237 /* 238 * STRT/LDRT access macros with ARM and Thumb-2 variants 239 */ 240 #ifdef CONFIG_THUMB2_KERNEL 241 242 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 243 9999: 244 .if \inc == 1 245 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] 246 .elseif \inc == 4 247 \instr\cond\()\t\().w \reg, [\ptr, #\off] 248 .else 249 .error "Unsupported inc macro argument" 250 .endif 251 252 .pushsection __ex_table,"a" 253 .align 3 254 .long 9999b, \abort 255 .popsection 256 .endm 257 258 .macro usracc, instr, reg, ptr, inc, cond, rept, abort 259 @ explicit IT instruction needed because of the label 260 @ introduced by the USER macro 261 .ifnc \cond,al 262 .if \rept == 1 263 itt \cond 264 .elseif \rept == 2 265 ittt \cond 266 .else 267 .error "Unsupported rept macro argument" 268 .endif 269 .endif 270 271 @ Slightly optimised to avoid incrementing the pointer twice 272 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 273 .if \rept == 2 274 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 275 .endif 276 277 add\cond \ptr, #\rept * \inc 278 .endm 279 280 #else /* !CONFIG_THUMB2_KERNEL */ 281 282 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 283 .rept \rept 284 9999: 285 .if \inc == 1 286 \instr\cond\()b\()\t \reg, [\ptr], #\inc 287 .elseif \inc == 4 288 \instr\cond\()\t \reg, [\ptr], #\inc 289 .else 290 .error "Unsupported inc macro argument" 291 .endif 292 293 .pushsection __ex_table,"a" 294 .align 3 295 .long 9999b, \abort 296 .popsection 297 .endr 298 .endm 299 300 #endif /* CONFIG_THUMB2_KERNEL */ 301 302 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 303 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 304 .endm 305 306 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 307 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 308 .endm 309 310 /* Utility macro for declaring string literals */ 311 .macro string name:req, string 312 .type \name , #object 313 \name: 314 .asciz "\string" 315 .size \name , . - \name 316 .endm 317 318 #endif /* __ASM_ASSEMBLER_H__ */ 319