1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * arch/arm/include/asm/assembler.h 4 * 5 * Copyright (C) 1996-2000 Russell King 6 * 7 * This file contains arm architecture specific defines 8 * for the different processors. 9 * 10 * Do not include any C declarations in this file - it is included by 11 * assembler source. 12 */ 13 #ifndef __ASM_ASSEMBLER_H__ 14 #define __ASM_ASSEMBLER_H__ 15 16 #ifndef __ASSEMBLY__ 17 #error "Only include this from assembly code" 18 #endif 19 20 #include <asm/ptrace.h> 21 #include <asm/opcodes-virt.h> 22 #include <asm/asm-offsets.h> 23 #include <asm/page.h> 24 #include <asm/thread_info.h> 25 #include <asm/uaccess-asm.h> 26 27 #define IOMEM(x) (x) 28 29 /* 30 * Endian independent macros for shifting bytes within registers. 31 */ 32 #ifndef __ARMEB__ 33 #define lspull lsr 34 #define lspush lsl 35 #define get_byte_0 lsl #0 36 #define get_byte_1 lsr #8 37 #define get_byte_2 lsr #16 38 #define get_byte_3 lsr #24 39 #define put_byte_0 lsl #0 40 #define put_byte_1 lsl #8 41 #define put_byte_2 lsl #16 42 #define put_byte_3 lsl #24 43 #else 44 #define lspull lsl 45 #define lspush lsr 46 #define get_byte_0 lsr #24 47 #define get_byte_1 lsr #16 48 #define get_byte_2 lsr #8 49 #define get_byte_3 lsl #0 50 #define put_byte_0 lsl #24 51 #define put_byte_1 lsl #16 52 #define put_byte_2 lsl #8 53 #define put_byte_3 lsl #0 54 #endif 55 56 /* Select code for any configuration running in BE8 mode */ 57 #ifdef CONFIG_CPU_ENDIAN_BE8 58 #define ARM_BE8(code...) code 59 #else 60 #define ARM_BE8(code...) 61 #endif 62 63 /* 64 * Data preload for architectures that support it 65 */ 66 #if __LINUX_ARM_ARCH__ >= 5 67 #define PLD(code...) code 68 #else 69 #define PLD(code...) 70 #endif 71 72 /* 73 * This can be used to enable code to cacheline align the destination 74 * pointer when bulk writing to memory. Experiments on StrongARM and 75 * XScale didn't show this a worthwhile thing to do when the cache is not 76 * set to write-allocate (this would need further testing on XScale when WA 77 * is used). 78 * 79 * On Feroceon there is much to gain however, regardless of cache mode. 80 */ 81 #ifdef CONFIG_CPU_FEROCEON 82 #define CALGN(code...) code 83 #else 84 #define CALGN(code...) 85 #endif 86 87 #define IMM12_MASK 0xfff 88 89 /* 90 * Enable and disable interrupts 91 */ 92 #if __LINUX_ARM_ARCH__ >= 6 93 .macro disable_irq_notrace 94 cpsid i 95 .endm 96 97 .macro enable_irq_notrace 98 cpsie i 99 .endm 100 #else 101 .macro disable_irq_notrace 102 msr cpsr_c, #PSR_I_BIT | SVC_MODE 103 .endm 104 105 .macro enable_irq_notrace 106 msr cpsr_c, #SVC_MODE 107 .endm 108 #endif 109 110 #if __LINUX_ARM_ARCH__ < 7 111 .macro dsb, args 112 mcr p15, 0, r0, c7, c10, 4 113 .endm 114 115 .macro isb, args 116 mcr p15, 0, r0, c7, r5, 4 117 .endm 118 #endif 119 120 .macro asm_trace_hardirqs_off, save=1 121 #if defined(CONFIG_TRACE_IRQFLAGS) 122 .if \save 123 stmdb sp!, {r0-r3, ip, lr} 124 .endif 125 bl trace_hardirqs_off 126 .if \save 127 ldmia sp!, {r0-r3, ip, lr} 128 .endif 129 #endif 130 .endm 131 132 .macro asm_trace_hardirqs_on, cond=al, save=1 133 #if defined(CONFIG_TRACE_IRQFLAGS) 134 /* 135 * actually the registers should be pushed and pop'd conditionally, but 136 * after bl the flags are certainly clobbered 137 */ 138 .if \save 139 stmdb sp!, {r0-r3, ip, lr} 140 .endif 141 bl\cond trace_hardirqs_on 142 .if \save 143 ldmia sp!, {r0-r3, ip, lr} 144 .endif 145 #endif 146 .endm 147 148 .macro disable_irq, save=1 149 disable_irq_notrace 150 asm_trace_hardirqs_off \save 151 .endm 152 153 .macro enable_irq 154 asm_trace_hardirqs_on 155 enable_irq_notrace 156 .endm 157 /* 158 * Save the current IRQ state and disable IRQs. Note that this macro 159 * assumes FIQs are enabled, and that the processor is in SVC mode. 160 */ 161 .macro save_and_disable_irqs, oldcpsr 162 #ifdef CONFIG_CPU_V7M 163 mrs \oldcpsr, primask 164 #else 165 mrs \oldcpsr, cpsr 166 #endif 167 disable_irq 168 .endm 169 170 .macro save_and_disable_irqs_notrace, oldcpsr 171 #ifdef CONFIG_CPU_V7M 172 mrs \oldcpsr, primask 173 #else 174 mrs \oldcpsr, cpsr 175 #endif 176 disable_irq_notrace 177 .endm 178 179 /* 180 * Restore interrupt state previously stored in a register. We don't 181 * guarantee that this will preserve the flags. 182 */ 183 .macro restore_irqs_notrace, oldcpsr 184 #ifdef CONFIG_CPU_V7M 185 msr primask, \oldcpsr 186 #else 187 msr cpsr_c, \oldcpsr 188 #endif 189 .endm 190 191 .macro restore_irqs, oldcpsr 192 tst \oldcpsr, #PSR_I_BIT 193 asm_trace_hardirqs_on cond=eq 194 restore_irqs_notrace \oldcpsr 195 .endm 196 197 /* 198 * Assembly version of "adr rd, BSYM(sym)". This should only be used to 199 * reference local symbols in the same assembly file which are to be 200 * resolved by the assembler. Other usage is undefined. 201 */ 202 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 203 .macro badr\c, rd, sym 204 #ifdef CONFIG_THUMB2_KERNEL 205 adr\c \rd, \sym + 1 206 #else 207 adr\c \rd, \sym 208 #endif 209 .endm 210 .endr 211 212 /* 213 * Get current thread_info. 214 */ 215 .macro get_thread_info, rd 216 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT ) 217 THUMB( mov \rd, sp ) 218 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT ) 219 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT 220 .endm 221 222 /* 223 * Increment/decrement the preempt count. 224 */ 225 #ifdef CONFIG_PREEMPT_COUNT 226 .macro inc_preempt_count, ti, tmp 227 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 228 add \tmp, \tmp, #1 @ increment it 229 str \tmp, [\ti, #TI_PREEMPT] 230 .endm 231 232 .macro dec_preempt_count, ti, tmp 233 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 234 sub \tmp, \tmp, #1 @ decrement it 235 str \tmp, [\ti, #TI_PREEMPT] 236 .endm 237 238 .macro dec_preempt_count_ti, ti, tmp 239 get_thread_info \ti 240 dec_preempt_count \ti, \tmp 241 .endm 242 #else 243 .macro inc_preempt_count, ti, tmp 244 .endm 245 246 .macro dec_preempt_count, ti, tmp 247 .endm 248 249 .macro dec_preempt_count_ti, ti, tmp 250 .endm 251 #endif 252 253 #define USERL(l, x...) \ 254 9999: x; \ 255 .pushsection __ex_table,"a"; \ 256 .align 3; \ 257 .long 9999b,l; \ 258 .popsection 259 260 #define USER(x...) USERL(9001f, x) 261 262 #ifdef CONFIG_SMP 263 #define ALT_SMP(instr...) \ 264 9998: instr 265 /* 266 * Note: if you get assembler errors from ALT_UP() when building with 267 * CONFIG_THUMB2_KERNEL, you almost certainly need to use 268 * ALT_SMP( W(instr) ... ) 269 */ 270 #define ALT_UP(instr...) \ 271 .pushsection ".alt.smp.init", "a" ;\ 272 .align 2 ;\ 273 .long 9998b - . ;\ 274 9997: instr ;\ 275 .if . - 9997b == 2 ;\ 276 nop ;\ 277 .endif ;\ 278 .if . - 9997b != 4 ;\ 279 .error "ALT_UP() content must assemble to exactly 4 bytes";\ 280 .endif ;\ 281 .popsection 282 #define ALT_UP_B(label) \ 283 .pushsection ".alt.smp.init", "a" ;\ 284 .align 2 ;\ 285 .long 9998b - . ;\ 286 W(b) . + (label - 9998b) ;\ 287 .popsection 288 #else 289 #define ALT_SMP(instr...) 290 #define ALT_UP(instr...) instr 291 #define ALT_UP_B(label) b label 292 #endif 293 294 /* 295 * Instruction barrier 296 */ 297 .macro instr_sync 298 #if __LINUX_ARM_ARCH__ >= 7 299 isb 300 #elif __LINUX_ARM_ARCH__ == 6 301 mcr p15, 0, r0, c7, c5, 4 302 #endif 303 .endm 304 305 /* 306 * SMP data memory barrier 307 */ 308 .macro smp_dmb mode 309 #ifdef CONFIG_SMP 310 #if __LINUX_ARM_ARCH__ >= 7 311 .ifeqs "\mode","arm" 312 ALT_SMP(dmb ish) 313 .else 314 ALT_SMP(W(dmb) ish) 315 .endif 316 #elif __LINUX_ARM_ARCH__ == 6 317 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 318 #else 319 #error Incompatible SMP platform 320 #endif 321 .ifeqs "\mode","arm" 322 ALT_UP(nop) 323 .else 324 ALT_UP(W(nop)) 325 .endif 326 #endif 327 .endm 328 329 #if defined(CONFIG_CPU_V7M) 330 /* 331 * setmode is used to assert to be in svc mode during boot. For v7-M 332 * this is done in __v7m_setup, so setmode can be empty here. 333 */ 334 .macro setmode, mode, reg 335 .endm 336 #elif defined(CONFIG_THUMB2_KERNEL) 337 .macro setmode, mode, reg 338 mov \reg, #\mode 339 msr cpsr_c, \reg 340 .endm 341 #else 342 .macro setmode, mode, reg 343 msr cpsr_c, #\mode 344 .endm 345 #endif 346 347 /* 348 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is 349 * a scratch register for the macro to overwrite. 350 * 351 * This macro is intended for forcing the CPU into SVC mode at boot time. 352 * you cannot return to the original mode. 353 */ 354 .macro safe_svcmode_maskall reg:req 355 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M) 356 mrs \reg , cpsr 357 eor \reg, \reg, #HYP_MODE 358 tst \reg, #MODE_MASK 359 bic \reg , \reg , #MODE_MASK 360 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE 361 THUMB( orr \reg , \reg , #PSR_T_BIT ) 362 bne 1f 363 orr \reg, \reg, #PSR_A_BIT 364 badr lr, 2f 365 msr spsr_cxsf, \reg 366 __MSR_ELR_HYP(14) 367 __ERET 368 1: msr cpsr_c, \reg 369 2: 370 #else 371 /* 372 * workaround for possibly broken pre-v6 hardware 373 * (akita, Sharp Zaurus C-1000, PXA270-based) 374 */ 375 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg 376 #endif 377 .endm 378 379 /* 380 * STRT/LDRT access macros with ARM and Thumb-2 variants 381 */ 382 #ifdef CONFIG_THUMB2_KERNEL 383 384 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 385 9999: 386 .if \inc == 1 387 \instr\()b\t\cond\().w \reg, [\ptr, #\off] 388 .elseif \inc == 4 389 \instr\t\cond\().w \reg, [\ptr, #\off] 390 .else 391 .error "Unsupported inc macro argument" 392 .endif 393 394 .pushsection __ex_table,"a" 395 .align 3 396 .long 9999b, \abort 397 .popsection 398 .endm 399 400 .macro usracc, instr, reg, ptr, inc, cond, rept, abort 401 @ explicit IT instruction needed because of the label 402 @ introduced by the USER macro 403 .ifnc \cond,al 404 .if \rept == 1 405 itt \cond 406 .elseif \rept == 2 407 ittt \cond 408 .else 409 .error "Unsupported rept macro argument" 410 .endif 411 .endif 412 413 @ Slightly optimised to avoid incrementing the pointer twice 414 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 415 .if \rept == 2 416 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 417 .endif 418 419 add\cond \ptr, #\rept * \inc 420 .endm 421 422 #else /* !CONFIG_THUMB2_KERNEL */ 423 424 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 425 .rept \rept 426 9999: 427 .if \inc == 1 428 \instr\()b\t\cond \reg, [\ptr], #\inc 429 .elseif \inc == 4 430 \instr\t\cond \reg, [\ptr], #\inc 431 .else 432 .error "Unsupported inc macro argument" 433 .endif 434 435 .pushsection __ex_table,"a" 436 .align 3 437 .long 9999b, \abort 438 .popsection 439 .endr 440 .endm 441 442 #endif /* CONFIG_THUMB2_KERNEL */ 443 444 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 445 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 446 .endm 447 448 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 449 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 450 .endm 451 452 /* Utility macro for declaring string literals */ 453 .macro string name:req, string 454 .type \name , #object 455 \name: 456 .asciz "\string" 457 .size \name , . - \name 458 .endm 459 460 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 461 .macro ret\c, reg 462 #if __LINUX_ARM_ARCH__ < 6 463 mov\c pc, \reg 464 #else 465 .ifeqs "\reg", "lr" 466 bx\c \reg 467 .else 468 mov\c pc, \reg 469 .endif 470 #endif 471 .endm 472 .endr 473 474 .macro ret.w, reg 475 ret \reg 476 #ifdef CONFIG_THUMB2_KERNEL 477 nop 478 #endif 479 .endm 480 481 .macro bug, msg, line 482 #ifdef CONFIG_THUMB2_KERNEL 483 1: .inst 0xde02 484 #else 485 1: .inst 0xe7f001f2 486 #endif 487 #ifdef CONFIG_DEBUG_BUGVERBOSE 488 .pushsection .rodata.str, "aMS", %progbits, 1 489 2: .asciz "\msg" 490 .popsection 491 .pushsection __bug_table, "aw" 492 .align 2 493 .word 1b, 2b 494 .hword \line 495 .popsection 496 #endif 497 .endm 498 499 #ifdef CONFIG_KPROBES 500 #define _ASM_NOKPROBE(entry) \ 501 .pushsection "_kprobe_blacklist", "aw" ; \ 502 .balign 4 ; \ 503 .long entry; \ 504 .popsection 505 #else 506 #define _ASM_NOKPROBE(entry) 507 #endif 508 509 .macro __adldst_l, op, reg, sym, tmp, c 510 .if __LINUX_ARM_ARCH__ < 7 511 ldr\c \tmp, .La\@ 512 .subsection 1 513 .align 2 514 .La\@: .long \sym - .Lpc\@ 515 .previous 516 .else 517 .ifnb \c 518 THUMB( ittt \c ) 519 .endif 520 movw\c \tmp, #:lower16:\sym - .Lpc\@ 521 movt\c \tmp, #:upper16:\sym - .Lpc\@ 522 .endif 523 524 #ifndef CONFIG_THUMB2_KERNEL 525 .set .Lpc\@, . + 8 // PC bias 526 .ifc \op, add 527 add\c \reg, \tmp, pc 528 .else 529 \op\c \reg, [pc, \tmp] 530 .endif 531 #else 532 .Lb\@: add\c \tmp, \tmp, pc 533 /* 534 * In Thumb-2 builds, the PC bias depends on whether we are currently 535 * emitting into a .arm or a .thumb section. The size of the add opcode 536 * above will be 2 bytes when emitting in Thumb mode and 4 bytes when 537 * emitting in ARM mode, so let's use this to account for the bias. 538 */ 539 .set .Lpc\@, . + (. - .Lb\@) 540 541 .ifnc \op, add 542 \op\c \reg, [\tmp] 543 .endif 544 #endif 545 .endm 546 547 /* 548 * mov_l - move a constant value or [relocated] address into a register 549 */ 550 .macro mov_l, dst:req, imm:req 551 .if __LINUX_ARM_ARCH__ < 7 552 ldr \dst, =\imm 553 .else 554 movw \dst, #:lower16:\imm 555 movt \dst, #:upper16:\imm 556 .endif 557 .endm 558 559 /* 560 * adr_l - adr pseudo-op with unlimited range 561 * 562 * @dst: destination register 563 * @sym: name of the symbol 564 * @cond: conditional opcode suffix 565 */ 566 .macro adr_l, dst:req, sym:req, cond 567 __adldst_l add, \dst, \sym, \dst, \cond 568 .endm 569 570 /* 571 * ldr_l - ldr <literal> pseudo-op with unlimited range 572 * 573 * @dst: destination register 574 * @sym: name of the symbol 575 * @cond: conditional opcode suffix 576 */ 577 .macro ldr_l, dst:req, sym:req, cond 578 __adldst_l ldr, \dst, \sym, \dst, \cond 579 .endm 580 581 /* 582 * str_l - str <literal> pseudo-op with unlimited range 583 * 584 * @src: source register 585 * @sym: name of the symbol 586 * @tmp: mandatory scratch register 587 * @cond: conditional opcode suffix 588 */ 589 .macro str_l, src:req, sym:req, tmp:req, cond 590 __adldst_l str, \src, \sym, \tmp, \cond 591 .endm 592 593 /* 594 * rev_l - byte-swap a 32-bit value 595 * 596 * @val: source/destination register 597 * @tmp: scratch register 598 */ 599 .macro rev_l, val:req, tmp:req 600 .if __LINUX_ARM_ARCH__ < 6 601 eor \tmp, \val, \val, ror #16 602 bic \tmp, \tmp, #0x00ff0000 603 mov \val, \val, ror #8 604 eor \val, \val, \tmp, lsr #8 605 .else 606 rev \val, \val 607 .endif 608 .endm 609 610 #endif /* __ASM_ASSEMBLER_H__ */ 611