1 /* 2 * arch/arm/include/asm/assembler.h 3 * 4 * Copyright (C) 1996-2000 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This file contains arm architecture specific defines 11 * for the different processors. 12 * 13 * Do not include any C declarations in this file - it is included by 14 * assembler source. 15 */ 16 #ifndef __ASM_ASSEMBLER_H__ 17 #define __ASM_ASSEMBLER_H__ 18 19 #ifndef __ASSEMBLY__ 20 #error "Only include this from assembly code" 21 #endif 22 23 #include <asm/ptrace.h> 24 #include <asm/domain.h> 25 #include <asm/opcodes-virt.h> 26 #include <asm/asm-offsets.h> 27 #include <asm/page.h> 28 #include <asm/thread_info.h> 29 30 #define IOMEM(x) (x) 31 32 /* 33 * Endian independent macros for shifting bytes within registers. 34 */ 35 #ifndef __ARMEB__ 36 #define lspull lsr 37 #define lspush lsl 38 #define get_byte_0 lsl #0 39 #define get_byte_1 lsr #8 40 #define get_byte_2 lsr #16 41 #define get_byte_3 lsr #24 42 #define put_byte_0 lsl #0 43 #define put_byte_1 lsl #8 44 #define put_byte_2 lsl #16 45 #define put_byte_3 lsl #24 46 #else 47 #define lspull lsl 48 #define lspush lsr 49 #define get_byte_0 lsr #24 50 #define get_byte_1 lsr #16 51 #define get_byte_2 lsr #8 52 #define get_byte_3 lsl #0 53 #define put_byte_0 lsl #24 54 #define put_byte_1 lsl #16 55 #define put_byte_2 lsl #8 56 #define put_byte_3 lsl #0 57 #endif 58 59 /* Select code for any configuration running in BE8 mode */ 60 #ifdef CONFIG_CPU_ENDIAN_BE8 61 #define ARM_BE8(code...) code 62 #else 63 #define ARM_BE8(code...) 64 #endif 65 66 /* 67 * Data preload for architectures that support it 68 */ 69 #if __LINUX_ARM_ARCH__ >= 5 70 #define PLD(code...) code 71 #else 72 #define PLD(code...) 73 #endif 74 75 /* 76 * This can be used to enable code to cacheline align the destination 77 * pointer when bulk writing to memory. Experiments on StrongARM and 78 * XScale didn't show this a worthwhile thing to do when the cache is not 79 * set to write-allocate (this would need further testing on XScale when WA 80 * is used). 81 * 82 * On Feroceon there is much to gain however, regardless of cache mode. 83 */ 84 #ifdef CONFIG_CPU_FEROCEON 85 #define CALGN(code...) code 86 #else 87 #define CALGN(code...) 88 #endif 89 90 /* 91 * Enable and disable interrupts 92 */ 93 #if __LINUX_ARM_ARCH__ >= 6 94 .macro disable_irq_notrace 95 cpsid i 96 .endm 97 98 .macro enable_irq_notrace 99 cpsie i 100 .endm 101 #else 102 .macro disable_irq_notrace 103 msr cpsr_c, #PSR_I_BIT | SVC_MODE 104 .endm 105 106 .macro enable_irq_notrace 107 msr cpsr_c, #SVC_MODE 108 .endm 109 #endif 110 111 .macro asm_trace_hardirqs_off 112 #if defined(CONFIG_TRACE_IRQFLAGS) 113 stmdb sp!, {r0-r3, ip, lr} 114 bl trace_hardirqs_off 115 ldmia sp!, {r0-r3, ip, lr} 116 #endif 117 .endm 118 119 .macro asm_trace_hardirqs_on_cond, cond 120 #if defined(CONFIG_TRACE_IRQFLAGS) 121 /* 122 * actually the registers should be pushed and pop'd conditionally, but 123 * after bl the flags are certainly clobbered 124 */ 125 stmdb sp!, {r0-r3, ip, lr} 126 bl\cond trace_hardirqs_on 127 ldmia sp!, {r0-r3, ip, lr} 128 #endif 129 .endm 130 131 .macro asm_trace_hardirqs_on 132 asm_trace_hardirqs_on_cond al 133 .endm 134 135 .macro disable_irq 136 disable_irq_notrace 137 asm_trace_hardirqs_off 138 .endm 139 140 .macro enable_irq 141 asm_trace_hardirqs_on 142 enable_irq_notrace 143 .endm 144 /* 145 * Save the current IRQ state and disable IRQs. Note that this macro 146 * assumes FIQs are enabled, and that the processor is in SVC mode. 147 */ 148 .macro save_and_disable_irqs, oldcpsr 149 #ifdef CONFIG_CPU_V7M 150 mrs \oldcpsr, primask 151 #else 152 mrs \oldcpsr, cpsr 153 #endif 154 disable_irq 155 .endm 156 157 .macro save_and_disable_irqs_notrace, oldcpsr 158 mrs \oldcpsr, cpsr 159 disable_irq_notrace 160 .endm 161 162 /* 163 * Restore interrupt state previously stored in a register. We don't 164 * guarantee that this will preserve the flags. 165 */ 166 .macro restore_irqs_notrace, oldcpsr 167 #ifdef CONFIG_CPU_V7M 168 msr primask, \oldcpsr 169 #else 170 msr cpsr_c, \oldcpsr 171 #endif 172 .endm 173 174 .macro restore_irqs, oldcpsr 175 tst \oldcpsr, #PSR_I_BIT 176 asm_trace_hardirqs_on_cond eq 177 restore_irqs_notrace \oldcpsr 178 .endm 179 180 /* 181 * Assembly version of "adr rd, BSYM(sym)". This should only be used to 182 * reference local symbols in the same assembly file which are to be 183 * resolved by the assembler. Other usage is undefined. 184 */ 185 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 186 .macro badr\c, rd, sym 187 #ifdef CONFIG_THUMB2_KERNEL 188 adr\c \rd, \sym + 1 189 #else 190 adr\c \rd, \sym 191 #endif 192 .endm 193 .endr 194 195 /* 196 * Get current thread_info. 197 */ 198 .macro get_thread_info, rd 199 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT ) 200 THUMB( mov \rd, sp ) 201 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT ) 202 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT 203 .endm 204 205 /* 206 * Increment/decrement the preempt count. 207 */ 208 #ifdef CONFIG_PREEMPT_COUNT 209 .macro inc_preempt_count, ti, tmp 210 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 211 add \tmp, \tmp, #1 @ increment it 212 str \tmp, [\ti, #TI_PREEMPT] 213 .endm 214 215 .macro dec_preempt_count, ti, tmp 216 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 217 sub \tmp, \tmp, #1 @ decrement it 218 str \tmp, [\ti, #TI_PREEMPT] 219 .endm 220 221 .macro dec_preempt_count_ti, ti, tmp 222 get_thread_info \ti 223 dec_preempt_count \ti, \tmp 224 .endm 225 #else 226 .macro inc_preempt_count, ti, tmp 227 .endm 228 229 .macro dec_preempt_count, ti, tmp 230 .endm 231 232 .macro dec_preempt_count_ti, ti, tmp 233 .endm 234 #endif 235 236 #define USER(x...) \ 237 9999: x; \ 238 .pushsection __ex_table,"a"; \ 239 .align 3; \ 240 .long 9999b,9001f; \ 241 .popsection 242 243 #ifdef CONFIG_SMP 244 #define ALT_SMP(instr...) \ 245 9998: instr 246 /* 247 * Note: if you get assembler errors from ALT_UP() when building with 248 * CONFIG_THUMB2_KERNEL, you almost certainly need to use 249 * ALT_SMP( W(instr) ... ) 250 */ 251 #define ALT_UP(instr...) \ 252 .pushsection ".alt.smp.init", "a" ;\ 253 .long 9998b ;\ 254 9997: instr ;\ 255 .if . - 9997b == 2 ;\ 256 nop ;\ 257 .endif ;\ 258 .if . - 9997b != 4 ;\ 259 .error "ALT_UP() content must assemble to exactly 4 bytes";\ 260 .endif ;\ 261 .popsection 262 #define ALT_UP_B(label) \ 263 .equ up_b_offset, label - 9998b ;\ 264 .pushsection ".alt.smp.init", "a" ;\ 265 .long 9998b ;\ 266 W(b) . + up_b_offset ;\ 267 .popsection 268 #else 269 #define ALT_SMP(instr...) 270 #define ALT_UP(instr...) instr 271 #define ALT_UP_B(label) b label 272 #endif 273 274 /* 275 * Instruction barrier 276 */ 277 .macro instr_sync 278 #if __LINUX_ARM_ARCH__ >= 7 279 isb 280 #elif __LINUX_ARM_ARCH__ == 6 281 mcr p15, 0, r0, c7, c5, 4 282 #endif 283 .endm 284 285 /* 286 * SMP data memory barrier 287 */ 288 .macro smp_dmb mode 289 #ifdef CONFIG_SMP 290 #if __LINUX_ARM_ARCH__ >= 7 291 .ifeqs "\mode","arm" 292 ALT_SMP(dmb ish) 293 .else 294 ALT_SMP(W(dmb) ish) 295 .endif 296 #elif __LINUX_ARM_ARCH__ == 6 297 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 298 #else 299 #error Incompatible SMP platform 300 #endif 301 .ifeqs "\mode","arm" 302 ALT_UP(nop) 303 .else 304 ALT_UP(W(nop)) 305 .endif 306 #endif 307 .endm 308 309 #if defined(CONFIG_CPU_V7M) 310 /* 311 * setmode is used to assert to be in svc mode during boot. For v7-M 312 * this is done in __v7m_setup, so setmode can be empty here. 313 */ 314 .macro setmode, mode, reg 315 .endm 316 #elif defined(CONFIG_THUMB2_KERNEL) 317 .macro setmode, mode, reg 318 mov \reg, #\mode 319 msr cpsr_c, \reg 320 .endm 321 #else 322 .macro setmode, mode, reg 323 msr cpsr_c, #\mode 324 .endm 325 #endif 326 327 /* 328 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is 329 * a scratch register for the macro to overwrite. 330 * 331 * This macro is intended for forcing the CPU into SVC mode at boot time. 332 * you cannot return to the original mode. 333 */ 334 .macro safe_svcmode_maskall reg:req 335 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M) 336 mrs \reg , cpsr 337 eor \reg, \reg, #HYP_MODE 338 tst \reg, #MODE_MASK 339 bic \reg , \reg , #MODE_MASK 340 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE 341 THUMB( orr \reg , \reg , #PSR_T_BIT ) 342 bne 1f 343 orr \reg, \reg, #PSR_A_BIT 344 badr lr, 2f 345 msr spsr_cxsf, \reg 346 __MSR_ELR_HYP(14) 347 __ERET 348 1: msr cpsr_c, \reg 349 2: 350 #else 351 /* 352 * workaround for possibly broken pre-v6 hardware 353 * (akita, Sharp Zaurus C-1000, PXA270-based) 354 */ 355 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg 356 #endif 357 .endm 358 359 /* 360 * STRT/LDRT access macros with ARM and Thumb-2 variants 361 */ 362 #ifdef CONFIG_THUMB2_KERNEL 363 364 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 365 9999: 366 .if \inc == 1 367 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] 368 .elseif \inc == 4 369 \instr\cond\()\t\().w \reg, [\ptr, #\off] 370 .else 371 .error "Unsupported inc macro argument" 372 .endif 373 374 .pushsection __ex_table,"a" 375 .align 3 376 .long 9999b, \abort 377 .popsection 378 .endm 379 380 .macro usracc, instr, reg, ptr, inc, cond, rept, abort 381 @ explicit IT instruction needed because of the label 382 @ introduced by the USER macro 383 .ifnc \cond,al 384 .if \rept == 1 385 itt \cond 386 .elseif \rept == 2 387 ittt \cond 388 .else 389 .error "Unsupported rept macro argument" 390 .endif 391 .endif 392 393 @ Slightly optimised to avoid incrementing the pointer twice 394 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 395 .if \rept == 2 396 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 397 .endif 398 399 add\cond \ptr, #\rept * \inc 400 .endm 401 402 #else /* !CONFIG_THUMB2_KERNEL */ 403 404 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 405 .rept \rept 406 9999: 407 .if \inc == 1 408 \instr\cond\()b\()\t \reg, [\ptr], #\inc 409 .elseif \inc == 4 410 \instr\cond\()\t \reg, [\ptr], #\inc 411 .else 412 .error "Unsupported inc macro argument" 413 .endif 414 415 .pushsection __ex_table,"a" 416 .align 3 417 .long 9999b, \abort 418 .popsection 419 .endr 420 .endm 421 422 #endif /* CONFIG_THUMB2_KERNEL */ 423 424 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 425 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 426 .endm 427 428 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 429 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 430 .endm 431 432 /* Utility macro for declaring string literals */ 433 .macro string name:req, string 434 .type \name , #object 435 \name: 436 .asciz "\string" 437 .size \name , . - \name 438 .endm 439 440 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req 441 #ifndef CONFIG_CPU_USE_DOMAINS 442 adds \tmp, \addr, #\size - 1 443 sbcccs \tmp, \tmp, \limit 444 bcs \bad 445 #endif 446 .endm 447 448 .macro uaccess_disable, tmp, isb=1 449 .endm 450 451 .macro uaccess_enable, tmp, isb=1 452 .endm 453 454 .macro uaccess_save, tmp 455 .endm 456 457 .macro uaccess_restore 458 .endm 459 460 .macro uaccess_save_and_disable, tmp 461 uaccess_save \tmp 462 uaccess_disable \tmp 463 .endm 464 465 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 466 .macro ret\c, reg 467 #if __LINUX_ARM_ARCH__ < 6 468 mov\c pc, \reg 469 #else 470 .ifeqs "\reg", "lr" 471 bx\c \reg 472 .else 473 mov\c pc, \reg 474 .endif 475 #endif 476 .endm 477 .endr 478 479 .macro ret.w, reg 480 ret \reg 481 #ifdef CONFIG_THUMB2_KERNEL 482 nop 483 #endif 484 .endm 485 486 #endif /* __ASM_ASSEMBLER_H__ */ 487