1 /* 2 * arch/arm/include/asm/assembler.h 3 * 4 * Copyright (C) 1996-2000 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This file contains arm architecture specific defines 11 * for the different processors. 12 * 13 * Do not include any C declarations in this file - it is included by 14 * assembler source. 15 */ 16 #ifndef __ASM_ASSEMBLER_H__ 17 #define __ASM_ASSEMBLER_H__ 18 19 #ifndef __ASSEMBLY__ 20 #error "Only include this from assembly code" 21 #endif 22 23 #include <asm/ptrace.h> 24 #include <asm/domain.h> 25 #include <asm/opcodes-virt.h> 26 #include <asm/asm-offsets.h> 27 #include <asm/page.h> 28 #include <asm/thread_info.h> 29 30 #define IOMEM(x) (x) 31 32 /* 33 * Endian independent macros for shifting bytes within registers. 34 */ 35 #ifndef __ARMEB__ 36 #define lspull lsr 37 #define lspush lsl 38 #define get_byte_0 lsl #0 39 #define get_byte_1 lsr #8 40 #define get_byte_2 lsr #16 41 #define get_byte_3 lsr #24 42 #define put_byte_0 lsl #0 43 #define put_byte_1 lsl #8 44 #define put_byte_2 lsl #16 45 #define put_byte_3 lsl #24 46 #else 47 #define lspull lsl 48 #define lspush lsr 49 #define get_byte_0 lsr #24 50 #define get_byte_1 lsr #16 51 #define get_byte_2 lsr #8 52 #define get_byte_3 lsl #0 53 #define put_byte_0 lsl #24 54 #define put_byte_1 lsl #16 55 #define put_byte_2 lsl #8 56 #define put_byte_3 lsl #0 57 #endif 58 59 /* Select code for any configuration running in BE8 mode */ 60 #ifdef CONFIG_CPU_ENDIAN_BE8 61 #define ARM_BE8(code...) code 62 #else 63 #define ARM_BE8(code...) 64 #endif 65 66 /* 67 * Data preload for architectures that support it 68 */ 69 #if __LINUX_ARM_ARCH__ >= 5 70 #define PLD(code...) code 71 #else 72 #define PLD(code...) 73 #endif 74 75 /* 76 * This can be used to enable code to cacheline align the destination 77 * pointer when bulk writing to memory. Experiments on StrongARM and 78 * XScale didn't show this a worthwhile thing to do when the cache is not 79 * set to write-allocate (this would need further testing on XScale when WA 80 * is used). 81 * 82 * On Feroceon there is much to gain however, regardless of cache mode. 83 */ 84 #ifdef CONFIG_CPU_FEROCEON 85 #define CALGN(code...) code 86 #else 87 #define CALGN(code...) 88 #endif 89 90 /* 91 * Enable and disable interrupts 92 */ 93 #if __LINUX_ARM_ARCH__ >= 6 94 .macro disable_irq_notrace 95 cpsid i 96 .endm 97 98 .macro enable_irq_notrace 99 cpsie i 100 .endm 101 #else 102 .macro disable_irq_notrace 103 msr cpsr_c, #PSR_I_BIT | SVC_MODE 104 .endm 105 106 .macro enable_irq_notrace 107 msr cpsr_c, #SVC_MODE 108 .endm 109 #endif 110 111 .macro asm_trace_hardirqs_off 112 #if defined(CONFIG_TRACE_IRQFLAGS) 113 stmdb sp!, {r0-r3, ip, lr} 114 bl trace_hardirqs_off 115 ldmia sp!, {r0-r3, ip, lr} 116 #endif 117 .endm 118 119 .macro asm_trace_hardirqs_on, cond=al 120 #if defined(CONFIG_TRACE_IRQFLAGS) 121 /* 122 * actually the registers should be pushed and pop'd conditionally, but 123 * after bl the flags are certainly clobbered 124 */ 125 stmdb sp!, {r0-r3, ip, lr} 126 bl\cond trace_hardirqs_on 127 ldmia sp!, {r0-r3, ip, lr} 128 #endif 129 .endm 130 131 .macro disable_irq 132 disable_irq_notrace 133 asm_trace_hardirqs_off 134 .endm 135 136 .macro enable_irq 137 asm_trace_hardirqs_on 138 enable_irq_notrace 139 .endm 140 /* 141 * Save the current IRQ state and disable IRQs. Note that this macro 142 * assumes FIQs are enabled, and that the processor is in SVC mode. 143 */ 144 .macro save_and_disable_irqs, oldcpsr 145 #ifdef CONFIG_CPU_V7M 146 mrs \oldcpsr, primask 147 #else 148 mrs \oldcpsr, cpsr 149 #endif 150 disable_irq 151 .endm 152 153 .macro save_and_disable_irqs_notrace, oldcpsr 154 mrs \oldcpsr, cpsr 155 disable_irq_notrace 156 .endm 157 158 /* 159 * Restore interrupt state previously stored in a register. We don't 160 * guarantee that this will preserve the flags. 161 */ 162 .macro restore_irqs_notrace, oldcpsr 163 #ifdef CONFIG_CPU_V7M 164 msr primask, \oldcpsr 165 #else 166 msr cpsr_c, \oldcpsr 167 #endif 168 .endm 169 170 .macro restore_irqs, oldcpsr 171 tst \oldcpsr, #PSR_I_BIT 172 asm_trace_hardirqs_on cond=eq 173 restore_irqs_notrace \oldcpsr 174 .endm 175 176 /* 177 * Assembly version of "adr rd, BSYM(sym)". This should only be used to 178 * reference local symbols in the same assembly file which are to be 179 * resolved by the assembler. Other usage is undefined. 180 */ 181 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 182 .macro badr\c, rd, sym 183 #ifdef CONFIG_THUMB2_KERNEL 184 adr\c \rd, \sym + 1 185 #else 186 adr\c \rd, \sym 187 #endif 188 .endm 189 .endr 190 191 /* 192 * Get current thread_info. 193 */ 194 .macro get_thread_info, rd 195 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT ) 196 THUMB( mov \rd, sp ) 197 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT ) 198 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT 199 .endm 200 201 /* 202 * Increment/decrement the preempt count. 203 */ 204 #ifdef CONFIG_PREEMPT_COUNT 205 .macro inc_preempt_count, ti, tmp 206 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 207 add \tmp, \tmp, #1 @ increment it 208 str \tmp, [\ti, #TI_PREEMPT] 209 .endm 210 211 .macro dec_preempt_count, ti, tmp 212 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 213 sub \tmp, \tmp, #1 @ decrement it 214 str \tmp, [\ti, #TI_PREEMPT] 215 .endm 216 217 .macro dec_preempt_count_ti, ti, tmp 218 get_thread_info \ti 219 dec_preempt_count \ti, \tmp 220 .endm 221 #else 222 .macro inc_preempt_count, ti, tmp 223 .endm 224 225 .macro dec_preempt_count, ti, tmp 226 .endm 227 228 .macro dec_preempt_count_ti, ti, tmp 229 .endm 230 #endif 231 232 #define USER(x...) \ 233 9999: x; \ 234 .pushsection __ex_table,"a"; \ 235 .align 3; \ 236 .long 9999b,9001f; \ 237 .popsection 238 239 #ifdef CONFIG_SMP 240 #define ALT_SMP(instr...) \ 241 9998: instr 242 /* 243 * Note: if you get assembler errors from ALT_UP() when building with 244 * CONFIG_THUMB2_KERNEL, you almost certainly need to use 245 * ALT_SMP( W(instr) ... ) 246 */ 247 #define ALT_UP(instr...) \ 248 .pushsection ".alt.smp.init", "a" ;\ 249 .long 9998b ;\ 250 9997: instr ;\ 251 .if . - 9997b == 2 ;\ 252 nop ;\ 253 .endif ;\ 254 .if . - 9997b != 4 ;\ 255 .error "ALT_UP() content must assemble to exactly 4 bytes";\ 256 .endif ;\ 257 .popsection 258 #define ALT_UP_B(label) \ 259 .equ up_b_offset, label - 9998b ;\ 260 .pushsection ".alt.smp.init", "a" ;\ 261 .long 9998b ;\ 262 W(b) . + up_b_offset ;\ 263 .popsection 264 #else 265 #define ALT_SMP(instr...) 266 #define ALT_UP(instr...) instr 267 #define ALT_UP_B(label) b label 268 #endif 269 270 /* 271 * Instruction barrier 272 */ 273 .macro instr_sync 274 #if __LINUX_ARM_ARCH__ >= 7 275 isb 276 #elif __LINUX_ARM_ARCH__ == 6 277 mcr p15, 0, r0, c7, c5, 4 278 #endif 279 .endm 280 281 /* 282 * SMP data memory barrier 283 */ 284 .macro smp_dmb mode 285 #ifdef CONFIG_SMP 286 #if __LINUX_ARM_ARCH__ >= 7 287 .ifeqs "\mode","arm" 288 ALT_SMP(dmb ish) 289 .else 290 ALT_SMP(W(dmb) ish) 291 .endif 292 #elif __LINUX_ARM_ARCH__ == 6 293 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 294 #else 295 #error Incompatible SMP platform 296 #endif 297 .ifeqs "\mode","arm" 298 ALT_UP(nop) 299 .else 300 ALT_UP(W(nop)) 301 .endif 302 #endif 303 .endm 304 305 #if defined(CONFIG_CPU_V7M) 306 /* 307 * setmode is used to assert to be in svc mode during boot. For v7-M 308 * this is done in __v7m_setup, so setmode can be empty here. 309 */ 310 .macro setmode, mode, reg 311 .endm 312 #elif defined(CONFIG_THUMB2_KERNEL) 313 .macro setmode, mode, reg 314 mov \reg, #\mode 315 msr cpsr_c, \reg 316 .endm 317 #else 318 .macro setmode, mode, reg 319 msr cpsr_c, #\mode 320 .endm 321 #endif 322 323 /* 324 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is 325 * a scratch register for the macro to overwrite. 326 * 327 * This macro is intended for forcing the CPU into SVC mode at boot time. 328 * you cannot return to the original mode. 329 */ 330 .macro safe_svcmode_maskall reg:req 331 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M) 332 mrs \reg , cpsr 333 eor \reg, \reg, #HYP_MODE 334 tst \reg, #MODE_MASK 335 bic \reg , \reg , #MODE_MASK 336 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE 337 THUMB( orr \reg , \reg , #PSR_T_BIT ) 338 bne 1f 339 orr \reg, \reg, #PSR_A_BIT 340 badr lr, 2f 341 msr spsr_cxsf, \reg 342 __MSR_ELR_HYP(14) 343 __ERET 344 1: msr cpsr_c, \reg 345 2: 346 #else 347 /* 348 * workaround for possibly broken pre-v6 hardware 349 * (akita, Sharp Zaurus C-1000, PXA270-based) 350 */ 351 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg 352 #endif 353 .endm 354 355 /* 356 * STRT/LDRT access macros with ARM and Thumb-2 variants 357 */ 358 #ifdef CONFIG_THUMB2_KERNEL 359 360 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 361 9999: 362 .if \inc == 1 363 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] 364 .elseif \inc == 4 365 \instr\cond\()\t\().w \reg, [\ptr, #\off] 366 .else 367 .error "Unsupported inc macro argument" 368 .endif 369 370 .pushsection __ex_table,"a" 371 .align 3 372 .long 9999b, \abort 373 .popsection 374 .endm 375 376 .macro usracc, instr, reg, ptr, inc, cond, rept, abort 377 @ explicit IT instruction needed because of the label 378 @ introduced by the USER macro 379 .ifnc \cond,al 380 .if \rept == 1 381 itt \cond 382 .elseif \rept == 2 383 ittt \cond 384 .else 385 .error "Unsupported rept macro argument" 386 .endif 387 .endif 388 389 @ Slightly optimised to avoid incrementing the pointer twice 390 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 391 .if \rept == 2 392 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 393 .endif 394 395 add\cond \ptr, #\rept * \inc 396 .endm 397 398 #else /* !CONFIG_THUMB2_KERNEL */ 399 400 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 401 .rept \rept 402 9999: 403 .if \inc == 1 404 \instr\cond\()b\()\t \reg, [\ptr], #\inc 405 .elseif \inc == 4 406 \instr\cond\()\t \reg, [\ptr], #\inc 407 .else 408 .error "Unsupported inc macro argument" 409 .endif 410 411 .pushsection __ex_table,"a" 412 .align 3 413 .long 9999b, \abort 414 .popsection 415 .endr 416 .endm 417 418 #endif /* CONFIG_THUMB2_KERNEL */ 419 420 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 421 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 422 .endm 423 424 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 425 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 426 .endm 427 428 /* Utility macro for declaring string literals */ 429 .macro string name:req, string 430 .type \name , #object 431 \name: 432 .asciz "\string" 433 .size \name , . - \name 434 .endm 435 436 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req 437 #ifndef CONFIG_CPU_USE_DOMAINS 438 adds \tmp, \addr, #\size - 1 439 sbcccs \tmp, \tmp, \limit 440 bcs \bad 441 #endif 442 .endm 443 444 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 445 .macro ret\c, reg 446 #if __LINUX_ARM_ARCH__ < 6 447 mov\c pc, \reg 448 #else 449 .ifeqs "\reg", "lr" 450 bx\c \reg 451 .else 452 mov\c pc, \reg 453 .endif 454 #endif 455 .endm 456 .endr 457 458 .macro ret.w, reg 459 ret \reg 460 #ifdef CONFIG_THUMB2_KERNEL 461 nop 462 #endif 463 .endm 464 465 #endif /* __ASM_ASSEMBLER_H__ */ 466