14baa9922SRussell King /* 24baa9922SRussell King * arch/arm/include/asm/assembler.h 34baa9922SRussell King * 44baa9922SRussell King * Copyright (C) 1996-2000 Russell King 54baa9922SRussell King * 64baa9922SRussell King * This program is free software; you can redistribute it and/or modify 74baa9922SRussell King * it under the terms of the GNU General Public License version 2 as 84baa9922SRussell King * published by the Free Software Foundation. 94baa9922SRussell King * 104baa9922SRussell King * This file contains arm architecture specific defines 114baa9922SRussell King * for the different processors. 124baa9922SRussell King * 134baa9922SRussell King * Do not include any C declarations in this file - it is included by 144baa9922SRussell King * assembler source. 154baa9922SRussell King */ 164baa9922SRussell King #ifndef __ASSEMBLY__ 174baa9922SRussell King #error "Only include this from assembly code" 184baa9922SRussell King #endif 194baa9922SRussell King 204baa9922SRussell King #include <asm/ptrace.h> 214baa9922SRussell King 224baa9922SRussell King /* 234baa9922SRussell King * Endian independent macros for shifting bytes within registers. 244baa9922SRussell King */ 254baa9922SRussell King #ifndef __ARMEB__ 264baa9922SRussell King #define pull lsr 274baa9922SRussell King #define push lsl 284baa9922SRussell King #define get_byte_0 lsl #0 294baa9922SRussell King #define get_byte_1 lsr #8 304baa9922SRussell King #define get_byte_2 lsr #16 314baa9922SRussell King #define get_byte_3 lsr #24 324baa9922SRussell King #define put_byte_0 lsl #0 334baa9922SRussell King #define put_byte_1 lsl #8 344baa9922SRussell King #define put_byte_2 lsl #16 354baa9922SRussell King #define put_byte_3 lsl #24 364baa9922SRussell King #else 374baa9922SRussell King #define pull lsl 384baa9922SRussell King #define push lsr 394baa9922SRussell King #define get_byte_0 lsr #24 404baa9922SRussell King #define get_byte_1 lsr #16 414baa9922SRussell King #define get_byte_2 lsr #8 424baa9922SRussell King #define get_byte_3 lsl #0 434baa9922SRussell King #define put_byte_0 lsl #24 444baa9922SRussell King #define put_byte_1 lsl #16 454baa9922SRussell King #define put_byte_2 lsl #8 464baa9922SRussell King #define put_byte_3 lsl #0 474baa9922SRussell King #endif 484baa9922SRussell King 494baa9922SRussell King /* 504baa9922SRussell King * Data preload for architectures that support it 514baa9922SRussell King */ 524baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 5 534baa9922SRussell King #define PLD(code...) code 544baa9922SRussell King #else 554baa9922SRussell King #define PLD(code...) 564baa9922SRussell King #endif 574baa9922SRussell King 584baa9922SRussell King /* 594baa9922SRussell King * This can be used to enable code to cacheline align the destination 604baa9922SRussell King * pointer when bulk writing to memory. Experiments on StrongARM and 614baa9922SRussell King * XScale didn't show this a worthwhile thing to do when the cache is not 624baa9922SRussell King * set to write-allocate (this would need further testing on XScale when WA 634baa9922SRussell King * is used). 644baa9922SRussell King * 654baa9922SRussell King * On Feroceon there is much to gain however, regardless of cache mode. 664baa9922SRussell King */ 674baa9922SRussell King #ifdef CONFIG_CPU_FEROCEON 684baa9922SRussell King #define CALGN(code...) code 694baa9922SRussell King #else 704baa9922SRussell King #define CALGN(code...) 714baa9922SRussell King #endif 724baa9922SRussell King 734baa9922SRussell King /* 744baa9922SRussell King * Enable and disable interrupts 754baa9922SRussell King */ 764baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 6 770d928b0bSUwe Kleine-König .macro disable_irq_notrace 784baa9922SRussell King cpsid i 794baa9922SRussell King .endm 804baa9922SRussell King 810d928b0bSUwe Kleine-König .macro enable_irq_notrace 824baa9922SRussell King cpsie i 834baa9922SRussell King .endm 844baa9922SRussell King #else 850d928b0bSUwe Kleine-König .macro disable_irq_notrace 864baa9922SRussell King msr cpsr_c, #PSR_I_BIT | SVC_MODE 874baa9922SRussell King .endm 884baa9922SRussell King 890d928b0bSUwe Kleine-König .macro enable_irq_notrace 904baa9922SRussell King msr cpsr_c, #SVC_MODE 914baa9922SRussell King .endm 924baa9922SRussell King #endif 934baa9922SRussell King 940d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_off 950d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 960d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 970d928b0bSUwe Kleine-König bl trace_hardirqs_off 980d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 990d928b0bSUwe Kleine-König #endif 1000d928b0bSUwe Kleine-König .endm 1010d928b0bSUwe Kleine-König 1020d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_on_cond, cond 1030d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1040d928b0bSUwe Kleine-König /* 1050d928b0bSUwe Kleine-König * actually the registers should be pushed and pop'd conditionally, but 1060d928b0bSUwe Kleine-König * after bl the flags are certainly clobbered 1070d928b0bSUwe Kleine-König */ 1080d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1090d928b0bSUwe Kleine-König bl\cond trace_hardirqs_on 1100d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1110d928b0bSUwe Kleine-König #endif 1120d928b0bSUwe Kleine-König .endm 1130d928b0bSUwe Kleine-König 1140d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_on 1150d928b0bSUwe Kleine-König asm_trace_hardirqs_on_cond al 1160d928b0bSUwe Kleine-König .endm 1170d928b0bSUwe Kleine-König 1180d928b0bSUwe Kleine-König .macro disable_irq 1190d928b0bSUwe Kleine-König disable_irq_notrace 1200d928b0bSUwe Kleine-König asm_trace_hardirqs_off 1210d928b0bSUwe Kleine-König .endm 1220d928b0bSUwe Kleine-König 1230d928b0bSUwe Kleine-König .macro enable_irq 1240d928b0bSUwe Kleine-König asm_trace_hardirqs_on 1250d928b0bSUwe Kleine-König enable_irq_notrace 1260d928b0bSUwe Kleine-König .endm 1274baa9922SRussell King /* 1284baa9922SRussell King * Save the current IRQ state and disable IRQs. Note that this macro 1294baa9922SRussell King * assumes FIQs are enabled, and that the processor is in SVC mode. 1304baa9922SRussell King */ 1314baa9922SRussell King .macro save_and_disable_irqs, oldcpsr 1324baa9922SRussell King mrs \oldcpsr, cpsr 1334baa9922SRussell King disable_irq 1344baa9922SRussell King .endm 1354baa9922SRussell King 1364baa9922SRussell King /* 1374baa9922SRussell King * Restore interrupt state previously stored in a register. We don't 1384baa9922SRussell King * guarantee that this will preserve the flags. 1394baa9922SRussell King */ 1400d928b0bSUwe Kleine-König .macro restore_irqs_notrace, oldcpsr 1414baa9922SRussell King msr cpsr_c, \oldcpsr 1424baa9922SRussell King .endm 1434baa9922SRussell King 1440d928b0bSUwe Kleine-König .macro restore_irqs, oldcpsr 1450d928b0bSUwe Kleine-König tst \oldcpsr, #PSR_I_BIT 1460d928b0bSUwe Kleine-König asm_trace_hardirqs_on_cond eq 1470d928b0bSUwe Kleine-König restore_irqs_notrace \oldcpsr 1480d928b0bSUwe Kleine-König .endm 1490d928b0bSUwe Kleine-König 1504baa9922SRussell King #define USER(x...) \ 1514baa9922SRussell King 9999: x; \ 1524260415fSRussell King .pushsection __ex_table,"a"; \ 1534baa9922SRussell King .align 3; \ 1544baa9922SRussell King .long 9999b,9001f; \ 1554260415fSRussell King .popsection 156bac4e960SRussell King 157f00ec48fSRussell King #ifdef CONFIG_SMP 158f00ec48fSRussell King #define ALT_SMP(instr...) \ 159f00ec48fSRussell King 9998: instr 160ed3768a8SDave Martin /* 161ed3768a8SDave Martin * Note: if you get assembler errors from ALT_UP() when building with 162ed3768a8SDave Martin * CONFIG_THUMB2_KERNEL, you almost certainly need to use 163ed3768a8SDave Martin * ALT_SMP( W(instr) ... ) 164ed3768a8SDave Martin */ 165f00ec48fSRussell King #define ALT_UP(instr...) \ 166f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 167f00ec48fSRussell King .long 9998b ;\ 168ed3768a8SDave Martin 9997: instr ;\ 169ed3768a8SDave Martin .if . - 9997b != 4 ;\ 170ed3768a8SDave Martin .error "ALT_UP() content must assemble to exactly 4 bytes";\ 171ed3768a8SDave Martin .endif ;\ 172f00ec48fSRussell King .popsection 173f00ec48fSRussell King #define ALT_UP_B(label) \ 174f00ec48fSRussell King .equ up_b_offset, label - 9998b ;\ 175f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 176f00ec48fSRussell King .long 9998b ;\ 177ed3768a8SDave Martin W(b) . + up_b_offset ;\ 178f00ec48fSRussell King .popsection 179f00ec48fSRussell King #else 180f00ec48fSRussell King #define ALT_SMP(instr...) 181f00ec48fSRussell King #define ALT_UP(instr...) instr 182f00ec48fSRussell King #define ALT_UP_B(label) b label 183f00ec48fSRussell King #endif 184f00ec48fSRussell King 185bac4e960SRussell King /* 186bac4e960SRussell King * SMP data memory barrier 187bac4e960SRussell King */ 188ed3768a8SDave Martin .macro smp_dmb mode 189bac4e960SRussell King #ifdef CONFIG_SMP 190bac4e960SRussell King #if __LINUX_ARM_ARCH__ >= 7 191ed3768a8SDave Martin .ifeqs "\mode","arm" 192f00ec48fSRussell King ALT_SMP(dmb) 193ed3768a8SDave Martin .else 194ed3768a8SDave Martin ALT_SMP(W(dmb)) 195ed3768a8SDave Martin .endif 196bac4e960SRussell King #elif __LINUX_ARM_ARCH__ == 6 197f00ec48fSRussell King ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 198f00ec48fSRussell King #else 199f00ec48fSRussell King #error Incompatible SMP platform 200bac4e960SRussell King #endif 201ed3768a8SDave Martin .ifeqs "\mode","arm" 202f00ec48fSRussell King ALT_UP(nop) 203ed3768a8SDave Martin .else 204ed3768a8SDave Martin ALT_UP(W(nop)) 205ed3768a8SDave Martin .endif 206bac4e960SRussell King #endif 207bac4e960SRussell King .endm 208b86040a5SCatalin Marinas 209b86040a5SCatalin Marinas #ifdef CONFIG_THUMB2_KERNEL 210b86040a5SCatalin Marinas .macro setmode, mode, reg 211b86040a5SCatalin Marinas mov \reg, #\mode 212b86040a5SCatalin Marinas msr cpsr_c, \reg 213b86040a5SCatalin Marinas .endm 214b86040a5SCatalin Marinas #else 215b86040a5SCatalin Marinas .macro setmode, mode, reg 216b86040a5SCatalin Marinas msr cpsr_c, #\mode 217b86040a5SCatalin Marinas .endm 218b86040a5SCatalin Marinas #endif 2198b592783SCatalin Marinas 2208b592783SCatalin Marinas /* 2218b592783SCatalin Marinas * STRT/LDRT access macros with ARM and Thumb-2 variants 2228b592783SCatalin Marinas */ 2238b592783SCatalin Marinas #ifdef CONFIG_THUMB2_KERNEL 2248b592783SCatalin Marinas 2258b592783SCatalin Marinas .macro usraccoff, instr, reg, ptr, inc, off, cond, abort 2268b592783SCatalin Marinas 9999: 2278b592783SCatalin Marinas .if \inc == 1 2288b592783SCatalin Marinas \instr\cond\()bt \reg, [\ptr, #\off] 2298b592783SCatalin Marinas .elseif \inc == 4 2308b592783SCatalin Marinas \instr\cond\()t \reg, [\ptr, #\off] 2318b592783SCatalin Marinas .else 2328b592783SCatalin Marinas .error "Unsupported inc macro argument" 2338b592783SCatalin Marinas .endif 2348b592783SCatalin Marinas 2354260415fSRussell King .pushsection __ex_table,"a" 2368b592783SCatalin Marinas .align 3 2378b592783SCatalin Marinas .long 9999b, \abort 2384260415fSRussell King .popsection 2398b592783SCatalin Marinas .endm 2408b592783SCatalin Marinas 2418b592783SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort 2428b592783SCatalin Marinas @ explicit IT instruction needed because of the label 2438b592783SCatalin Marinas @ introduced by the USER macro 2448b592783SCatalin Marinas .ifnc \cond,al 2458b592783SCatalin Marinas .if \rept == 1 2468b592783SCatalin Marinas itt \cond 2478b592783SCatalin Marinas .elseif \rept == 2 2488b592783SCatalin Marinas ittt \cond 2498b592783SCatalin Marinas .else 2508b592783SCatalin Marinas .error "Unsupported rept macro argument" 2518b592783SCatalin Marinas .endif 2528b592783SCatalin Marinas .endif 2538b592783SCatalin Marinas 2548b592783SCatalin Marinas @ Slightly optimised to avoid incrementing the pointer twice 2558b592783SCatalin Marinas usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 2568b592783SCatalin Marinas .if \rept == 2 2571142b71dSWill Deacon usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 2588b592783SCatalin Marinas .endif 2598b592783SCatalin Marinas 2608b592783SCatalin Marinas add\cond \ptr, #\rept * \inc 2618b592783SCatalin Marinas .endm 2628b592783SCatalin Marinas 2638b592783SCatalin Marinas #else /* !CONFIG_THUMB2_KERNEL */ 2648b592783SCatalin Marinas 2658b592783SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort 2668b592783SCatalin Marinas .rept \rept 2678b592783SCatalin Marinas 9999: 2688b592783SCatalin Marinas .if \inc == 1 2698b592783SCatalin Marinas \instr\cond\()bt \reg, [\ptr], #\inc 2708b592783SCatalin Marinas .elseif \inc == 4 2718b592783SCatalin Marinas \instr\cond\()t \reg, [\ptr], #\inc 2728b592783SCatalin Marinas .else 2738b592783SCatalin Marinas .error "Unsupported inc macro argument" 2748b592783SCatalin Marinas .endif 2758b592783SCatalin Marinas 2764260415fSRussell King .pushsection __ex_table,"a" 2778b592783SCatalin Marinas .align 3 2788b592783SCatalin Marinas .long 9999b, \abort 2794260415fSRussell King .popsection 2808b592783SCatalin Marinas .endr 2818b592783SCatalin Marinas .endm 2828b592783SCatalin Marinas 2838b592783SCatalin Marinas #endif /* CONFIG_THUMB2_KERNEL */ 2848b592783SCatalin Marinas 2858b592783SCatalin Marinas .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 2868b592783SCatalin Marinas usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 2878b592783SCatalin Marinas .endm 2888b592783SCatalin Marinas 2898b592783SCatalin Marinas .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 2908b592783SCatalin Marinas usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 2918b592783SCatalin Marinas .endm 292