1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24baa9922SRussell King /* 34baa9922SRussell King * arch/arm/include/asm/assembler.h 44baa9922SRussell King * 54baa9922SRussell King * Copyright (C) 1996-2000 Russell King 64baa9922SRussell King * 74baa9922SRussell King * This file contains arm architecture specific defines 84baa9922SRussell King * for the different processors. 94baa9922SRussell King * 104baa9922SRussell King * Do not include any C declarations in this file - it is included by 114baa9922SRussell King * assembler source. 124baa9922SRussell King */ 132bc58a6fSMagnus Damm #ifndef __ASM_ASSEMBLER_H__ 142bc58a6fSMagnus Damm #define __ASM_ASSEMBLER_H__ 152bc58a6fSMagnus Damm 164baa9922SRussell King #ifndef __ASSEMBLY__ 174baa9922SRussell King #error "Only include this from assembly code" 184baa9922SRussell King #endif 194baa9922SRussell King 204baa9922SRussell King #include <asm/ptrace.h> 21247055aaSCatalin Marinas #include <asm/domain.h> 2280c59dafSDave Martin #include <asm/opcodes-virt.h> 230b1f68e8SCatalin Marinas #include <asm/asm-offsets.h> 249a2b51b6SAndrey Ryabinin #include <asm/page.h> 259a2b51b6SAndrey Ryabinin #include <asm/thread_info.h> 264baa9922SRussell King 276f6f6a70SRob Herring #define IOMEM(x) (x) 286f6f6a70SRob Herring 294baa9922SRussell King /* 304baa9922SRussell King * Endian independent macros for shifting bytes within registers. 314baa9922SRussell King */ 324baa9922SRussell King #ifndef __ARMEB__ 33d98b90eaSVictor Kamensky #define lspull lsr 34d98b90eaSVictor Kamensky #define lspush lsl 354baa9922SRussell King #define get_byte_0 lsl #0 364baa9922SRussell King #define get_byte_1 lsr #8 374baa9922SRussell King #define get_byte_2 lsr #16 384baa9922SRussell King #define get_byte_3 lsr #24 394baa9922SRussell King #define put_byte_0 lsl #0 404baa9922SRussell King #define put_byte_1 lsl #8 414baa9922SRussell King #define put_byte_2 lsl #16 424baa9922SRussell King #define put_byte_3 lsl #24 434baa9922SRussell King #else 44d98b90eaSVictor Kamensky #define lspull lsl 45d98b90eaSVictor Kamensky #define lspush lsr 464baa9922SRussell King #define get_byte_0 lsr #24 474baa9922SRussell King #define get_byte_1 lsr #16 484baa9922SRussell King #define get_byte_2 lsr #8 494baa9922SRussell King #define get_byte_3 lsl #0 504baa9922SRussell King #define put_byte_0 lsl #24 514baa9922SRussell King #define put_byte_1 lsl #16 524baa9922SRussell King #define put_byte_2 lsl #8 534baa9922SRussell King #define put_byte_3 lsl #0 544baa9922SRussell King #endif 554baa9922SRussell King 56457c2403SBen Dooks /* Select code for any configuration running in BE8 mode */ 57457c2403SBen Dooks #ifdef CONFIG_CPU_ENDIAN_BE8 58457c2403SBen Dooks #define ARM_BE8(code...) code 59457c2403SBen Dooks #else 60457c2403SBen Dooks #define ARM_BE8(code...) 61457c2403SBen Dooks #endif 62457c2403SBen Dooks 634baa9922SRussell King /* 644baa9922SRussell King * Data preload for architectures that support it 654baa9922SRussell King */ 664baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 5 674baa9922SRussell King #define PLD(code...) code 684baa9922SRussell King #else 694baa9922SRussell King #define PLD(code...) 704baa9922SRussell King #endif 714baa9922SRussell King 724baa9922SRussell King /* 734baa9922SRussell King * This can be used to enable code to cacheline align the destination 744baa9922SRussell King * pointer when bulk writing to memory. Experiments on StrongARM and 754baa9922SRussell King * XScale didn't show this a worthwhile thing to do when the cache is not 764baa9922SRussell King * set to write-allocate (this would need further testing on XScale when WA 774baa9922SRussell King * is used). 784baa9922SRussell King * 794baa9922SRussell King * On Feroceon there is much to gain however, regardless of cache mode. 804baa9922SRussell King */ 814baa9922SRussell King #ifdef CONFIG_CPU_FEROCEON 824baa9922SRussell King #define CALGN(code...) code 834baa9922SRussell King #else 844baa9922SRussell King #define CALGN(code...) 854baa9922SRussell King #endif 864baa9922SRussell King 87ffa47aa6SArnd Bergmann #define IMM12_MASK 0xfff 88ffa47aa6SArnd Bergmann 894baa9922SRussell King /* 904baa9922SRussell King * Enable and disable interrupts 914baa9922SRussell King */ 924baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 6 930d928b0bSUwe Kleine-König .macro disable_irq_notrace 944baa9922SRussell King cpsid i 954baa9922SRussell King .endm 964baa9922SRussell King 970d928b0bSUwe Kleine-König .macro enable_irq_notrace 984baa9922SRussell King cpsie i 994baa9922SRussell King .endm 1004baa9922SRussell King #else 1010d928b0bSUwe Kleine-König .macro disable_irq_notrace 1024baa9922SRussell King msr cpsr_c, #PSR_I_BIT | SVC_MODE 1034baa9922SRussell King .endm 1044baa9922SRussell King 1050d928b0bSUwe Kleine-König .macro enable_irq_notrace 1064baa9922SRussell King msr cpsr_c, #SVC_MODE 1074baa9922SRussell King .endm 1084baa9922SRussell King #endif 1094baa9922SRussell King 1103302caddSRussell King .macro asm_trace_hardirqs_off, save=1 1110d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1123302caddSRussell King .if \save 1130d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1143302caddSRussell King .endif 1150d928b0bSUwe Kleine-König bl trace_hardirqs_off 1163302caddSRussell King .if \save 1170d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1183302caddSRussell King .endif 1190d928b0bSUwe Kleine-König #endif 1200d928b0bSUwe Kleine-König .endm 1210d928b0bSUwe Kleine-König 1223302caddSRussell King .macro asm_trace_hardirqs_on, cond=al, save=1 1230d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1240d928b0bSUwe Kleine-König /* 1250d928b0bSUwe Kleine-König * actually the registers should be pushed and pop'd conditionally, but 1260d928b0bSUwe Kleine-König * after bl the flags are certainly clobbered 1270d928b0bSUwe Kleine-König */ 1283302caddSRussell King .if \save 1290d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1303302caddSRussell King .endif 1310d928b0bSUwe Kleine-König bl\cond trace_hardirqs_on 1323302caddSRussell King .if \save 1330d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1343302caddSRussell King .endif 1350d928b0bSUwe Kleine-König #endif 1360d928b0bSUwe Kleine-König .endm 1370d928b0bSUwe Kleine-König 1383302caddSRussell King .macro disable_irq, save=1 1390d928b0bSUwe Kleine-König disable_irq_notrace 1403302caddSRussell King asm_trace_hardirqs_off \save 1410d928b0bSUwe Kleine-König .endm 1420d928b0bSUwe Kleine-König 1430d928b0bSUwe Kleine-König .macro enable_irq 1440d928b0bSUwe Kleine-König asm_trace_hardirqs_on 1450d928b0bSUwe Kleine-König enable_irq_notrace 1460d928b0bSUwe Kleine-König .endm 1474baa9922SRussell King /* 1484baa9922SRussell King * Save the current IRQ state and disable IRQs. Note that this macro 1494baa9922SRussell King * assumes FIQs are enabled, and that the processor is in SVC mode. 1504baa9922SRussell King */ 1514baa9922SRussell King .macro save_and_disable_irqs, oldcpsr 15255bdd694SCatalin Marinas #ifdef CONFIG_CPU_V7M 15355bdd694SCatalin Marinas mrs \oldcpsr, primask 15455bdd694SCatalin Marinas #else 1554baa9922SRussell King mrs \oldcpsr, cpsr 15655bdd694SCatalin Marinas #endif 1574baa9922SRussell King disable_irq 1584baa9922SRussell King .endm 1594baa9922SRussell King 1608e43a905SRabin Vincent .macro save_and_disable_irqs_notrace, oldcpsr 161b2bf482aSVladimir Murzin #ifdef CONFIG_CPU_V7M 162b2bf482aSVladimir Murzin mrs \oldcpsr, primask 163b2bf482aSVladimir Murzin #else 1648e43a905SRabin Vincent mrs \oldcpsr, cpsr 165b2bf482aSVladimir Murzin #endif 1668e43a905SRabin Vincent disable_irq_notrace 1678e43a905SRabin Vincent .endm 1688e43a905SRabin Vincent 1694baa9922SRussell King /* 1704baa9922SRussell King * Restore interrupt state previously stored in a register. We don't 1714baa9922SRussell King * guarantee that this will preserve the flags. 1724baa9922SRussell King */ 1730d928b0bSUwe Kleine-König .macro restore_irqs_notrace, oldcpsr 17455bdd694SCatalin Marinas #ifdef CONFIG_CPU_V7M 17555bdd694SCatalin Marinas msr primask, \oldcpsr 17655bdd694SCatalin Marinas #else 1774baa9922SRussell King msr cpsr_c, \oldcpsr 17855bdd694SCatalin Marinas #endif 1794baa9922SRussell King .endm 1804baa9922SRussell King 1810d928b0bSUwe Kleine-König .macro restore_irqs, oldcpsr 1820d928b0bSUwe Kleine-König tst \oldcpsr, #PSR_I_BIT 18301e09a28SRussell King asm_trace_hardirqs_on cond=eq 1840d928b0bSUwe Kleine-König restore_irqs_notrace \oldcpsr 1850d928b0bSUwe Kleine-König .endm 1860d928b0bSUwe Kleine-König 18739ad04ccSCatalin Marinas /* 18814327c66SRussell King * Assembly version of "adr rd, BSYM(sym)". This should only be used to 18914327c66SRussell King * reference local symbols in the same assembly file which are to be 19014327c66SRussell King * resolved by the assembler. Other usage is undefined. 19114327c66SRussell King */ 19214327c66SRussell King .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 19314327c66SRussell King .macro badr\c, rd, sym 19414327c66SRussell King #ifdef CONFIG_THUMB2_KERNEL 19514327c66SRussell King adr\c \rd, \sym + 1 19614327c66SRussell King #else 19714327c66SRussell King adr\c \rd, \sym 19814327c66SRussell King #endif 19914327c66SRussell King .endm 20014327c66SRussell King .endr 20114327c66SRussell King 20214327c66SRussell King /* 20339ad04ccSCatalin Marinas * Get current thread_info. 20439ad04ccSCatalin Marinas */ 20539ad04ccSCatalin Marinas .macro get_thread_info, rd 2069a2b51b6SAndrey Ryabinin ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT ) 20739ad04ccSCatalin Marinas THUMB( mov \rd, sp ) 2089a2b51b6SAndrey Ryabinin THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT ) 2099a2b51b6SAndrey Ryabinin mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT 21039ad04ccSCatalin Marinas .endm 21139ad04ccSCatalin Marinas 2120b1f68e8SCatalin Marinas /* 2130b1f68e8SCatalin Marinas * Increment/decrement the preempt count. 2140b1f68e8SCatalin Marinas */ 2150b1f68e8SCatalin Marinas #ifdef CONFIG_PREEMPT_COUNT 2160b1f68e8SCatalin Marinas .macro inc_preempt_count, ti, tmp 2170b1f68e8SCatalin Marinas ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 2180b1f68e8SCatalin Marinas add \tmp, \tmp, #1 @ increment it 2190b1f68e8SCatalin Marinas str \tmp, [\ti, #TI_PREEMPT] 2200b1f68e8SCatalin Marinas .endm 2210b1f68e8SCatalin Marinas 2220b1f68e8SCatalin Marinas .macro dec_preempt_count, ti, tmp 2230b1f68e8SCatalin Marinas ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 2240b1f68e8SCatalin Marinas sub \tmp, \tmp, #1 @ decrement it 2250b1f68e8SCatalin Marinas str \tmp, [\ti, #TI_PREEMPT] 2260b1f68e8SCatalin Marinas .endm 2270b1f68e8SCatalin Marinas 2280b1f68e8SCatalin Marinas .macro dec_preempt_count_ti, ti, tmp 2290b1f68e8SCatalin Marinas get_thread_info \ti 2300b1f68e8SCatalin Marinas dec_preempt_count \ti, \tmp 2310b1f68e8SCatalin Marinas .endm 2320b1f68e8SCatalin Marinas #else 2330b1f68e8SCatalin Marinas .macro inc_preempt_count, ti, tmp 2340b1f68e8SCatalin Marinas .endm 2350b1f68e8SCatalin Marinas 2360b1f68e8SCatalin Marinas .macro dec_preempt_count, ti, tmp 2370b1f68e8SCatalin Marinas .endm 2380b1f68e8SCatalin Marinas 2390b1f68e8SCatalin Marinas .macro dec_preempt_count_ti, ti, tmp 2400b1f68e8SCatalin Marinas .endm 2410b1f68e8SCatalin Marinas #endif 2420b1f68e8SCatalin Marinas 243f441882aSVincent Whitchurch #define USERL(l, x...) \ 2444baa9922SRussell King 9999: x; \ 2454260415fSRussell King .pushsection __ex_table,"a"; \ 2464baa9922SRussell King .align 3; \ 247f441882aSVincent Whitchurch .long 9999b,l; \ 2484260415fSRussell King .popsection 249bac4e960SRussell King 250f441882aSVincent Whitchurch #define USER(x...) USERL(9001f, x) 251f441882aSVincent Whitchurch 252f00ec48fSRussell King #ifdef CONFIG_SMP 253f00ec48fSRussell King #define ALT_SMP(instr...) \ 254f00ec48fSRussell King 9998: instr 255ed3768a8SDave Martin /* 256ed3768a8SDave Martin * Note: if you get assembler errors from ALT_UP() when building with 257ed3768a8SDave Martin * CONFIG_THUMB2_KERNEL, you almost certainly need to use 258ed3768a8SDave Martin * ALT_SMP( W(instr) ... ) 259ed3768a8SDave Martin */ 260f00ec48fSRussell King #define ALT_UP(instr...) \ 261f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 262f00ec48fSRussell King .long 9998b ;\ 263ed3768a8SDave Martin 9997: instr ;\ 26489c6bc58SRussell King .if . - 9997b == 2 ;\ 26589c6bc58SRussell King nop ;\ 26689c6bc58SRussell King .endif ;\ 267ed3768a8SDave Martin .if . - 9997b != 4 ;\ 268ed3768a8SDave Martin .error "ALT_UP() content must assemble to exactly 4 bytes";\ 269ed3768a8SDave Martin .endif ;\ 270f00ec48fSRussell King .popsection 271f00ec48fSRussell King #define ALT_UP_B(label) \ 272f00ec48fSRussell King .equ up_b_offset, label - 9998b ;\ 273f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 274f00ec48fSRussell King .long 9998b ;\ 275ed3768a8SDave Martin W(b) . + up_b_offset ;\ 276f00ec48fSRussell King .popsection 277f00ec48fSRussell King #else 278f00ec48fSRussell King #define ALT_SMP(instr...) 279f00ec48fSRussell King #define ALT_UP(instr...) instr 280f00ec48fSRussell King #define ALT_UP_B(label) b label 281f00ec48fSRussell King #endif 282f00ec48fSRussell King 283bac4e960SRussell King /* 284d675d0bcSWill Deacon * Instruction barrier 285d675d0bcSWill Deacon */ 286d675d0bcSWill Deacon .macro instr_sync 287d675d0bcSWill Deacon #if __LINUX_ARM_ARCH__ >= 7 288d675d0bcSWill Deacon isb 289d675d0bcSWill Deacon #elif __LINUX_ARM_ARCH__ == 6 290d675d0bcSWill Deacon mcr p15, 0, r0, c7, c5, 4 291d675d0bcSWill Deacon #endif 292d675d0bcSWill Deacon .endm 293d675d0bcSWill Deacon 294d675d0bcSWill Deacon /* 295bac4e960SRussell King * SMP data memory barrier 296bac4e960SRussell King */ 297ed3768a8SDave Martin .macro smp_dmb mode 298bac4e960SRussell King #ifdef CONFIG_SMP 299bac4e960SRussell King #if __LINUX_ARM_ARCH__ >= 7 300ed3768a8SDave Martin .ifeqs "\mode","arm" 3013ea12806SWill Deacon ALT_SMP(dmb ish) 302ed3768a8SDave Martin .else 3033ea12806SWill Deacon ALT_SMP(W(dmb) ish) 304ed3768a8SDave Martin .endif 305bac4e960SRussell King #elif __LINUX_ARM_ARCH__ == 6 306f00ec48fSRussell King ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 307f00ec48fSRussell King #else 308f00ec48fSRussell King #error Incompatible SMP platform 309bac4e960SRussell King #endif 310ed3768a8SDave Martin .ifeqs "\mode","arm" 311f00ec48fSRussell King ALT_UP(nop) 312ed3768a8SDave Martin .else 313ed3768a8SDave Martin ALT_UP(W(nop)) 314ed3768a8SDave Martin .endif 315bac4e960SRussell King #endif 316bac4e960SRussell King .endm 317b86040a5SCatalin Marinas 31855bdd694SCatalin Marinas #if defined(CONFIG_CPU_V7M) 31955bdd694SCatalin Marinas /* 32055bdd694SCatalin Marinas * setmode is used to assert to be in svc mode during boot. For v7-M 32155bdd694SCatalin Marinas * this is done in __v7m_setup, so setmode can be empty here. 32255bdd694SCatalin Marinas */ 32355bdd694SCatalin Marinas .macro setmode, mode, reg 32455bdd694SCatalin Marinas .endm 32555bdd694SCatalin Marinas #elif defined(CONFIG_THUMB2_KERNEL) 326b86040a5SCatalin Marinas .macro setmode, mode, reg 327b86040a5SCatalin Marinas mov \reg, #\mode 328b86040a5SCatalin Marinas msr cpsr_c, \reg 329b86040a5SCatalin Marinas .endm 330b86040a5SCatalin Marinas #else 331b86040a5SCatalin Marinas .macro setmode, mode, reg 332b86040a5SCatalin Marinas msr cpsr_c, #\mode 333b86040a5SCatalin Marinas .endm 334b86040a5SCatalin Marinas #endif 3358b592783SCatalin Marinas 3368b592783SCatalin Marinas /* 33780c59dafSDave Martin * Helper macro to enter SVC mode cleanly and mask interrupts. reg is 33880c59dafSDave Martin * a scratch register for the macro to overwrite. 33980c59dafSDave Martin * 34080c59dafSDave Martin * This macro is intended for forcing the CPU into SVC mode at boot time. 34180c59dafSDave Martin * you cannot return to the original mode. 34280c59dafSDave Martin */ 34380c59dafSDave Martin .macro safe_svcmode_maskall reg:req 3440e0779daSLorenzo Pieralisi #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M) 34580c59dafSDave Martin mrs \reg , cpsr 3468e9c24a2SRussell King eor \reg, \reg, #HYP_MODE 3478e9c24a2SRussell King tst \reg, #MODE_MASK 34880c59dafSDave Martin bic \reg , \reg , #MODE_MASK 3498e9c24a2SRussell King orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE 35080c59dafSDave Martin THUMB( orr \reg , \reg , #PSR_T_BIT ) 35180c59dafSDave Martin bne 1f 3522a552d5eSMarc Zyngier orr \reg, \reg, #PSR_A_BIT 35314327c66SRussell King badr lr, 2f 3542a552d5eSMarc Zyngier msr spsr_cxsf, \reg 35580c59dafSDave Martin __MSR_ELR_HYP(14) 35680c59dafSDave Martin __ERET 3572a552d5eSMarc Zyngier 1: msr cpsr_c, \reg 35880c59dafSDave Martin 2: 3591ecec696SDave Martin #else 3601ecec696SDave Martin /* 3611ecec696SDave Martin * workaround for possibly broken pre-v6 hardware 3621ecec696SDave Martin * (akita, Sharp Zaurus C-1000, PXA270-based) 3631ecec696SDave Martin */ 3641ecec696SDave Martin setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg 3651ecec696SDave Martin #endif 36680c59dafSDave Martin .endm 36780c59dafSDave Martin 36880c59dafSDave Martin /* 3698b592783SCatalin Marinas * STRT/LDRT access macros with ARM and Thumb-2 variants 3708b592783SCatalin Marinas */ 3718b592783SCatalin Marinas #ifdef CONFIG_THUMB2_KERNEL 3728b592783SCatalin Marinas 3734e7682d0SCatalin Marinas .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 3748b592783SCatalin Marinas 9999: 3758b592783SCatalin Marinas .if \inc == 1 376c001899aSStefan Agner \instr\()b\t\cond\().w \reg, [\ptr, #\off] 3778b592783SCatalin Marinas .elseif \inc == 4 378c001899aSStefan Agner \instr\t\cond\().w \reg, [\ptr, #\off] 3798b592783SCatalin Marinas .else 3808b592783SCatalin Marinas .error "Unsupported inc macro argument" 3818b592783SCatalin Marinas .endif 3828b592783SCatalin Marinas 3834260415fSRussell King .pushsection __ex_table,"a" 3848b592783SCatalin Marinas .align 3 3858b592783SCatalin Marinas .long 9999b, \abort 3864260415fSRussell King .popsection 3878b592783SCatalin Marinas .endm 3888b592783SCatalin Marinas 3898b592783SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort 3908b592783SCatalin Marinas @ explicit IT instruction needed because of the label 3918b592783SCatalin Marinas @ introduced by the USER macro 3928b592783SCatalin Marinas .ifnc \cond,al 3938b592783SCatalin Marinas .if \rept == 1 3948b592783SCatalin Marinas itt \cond 3958b592783SCatalin Marinas .elseif \rept == 2 3968b592783SCatalin Marinas ittt \cond 3978b592783SCatalin Marinas .else 3988b592783SCatalin Marinas .error "Unsupported rept macro argument" 3998b592783SCatalin Marinas .endif 4008b592783SCatalin Marinas .endif 4018b592783SCatalin Marinas 4028b592783SCatalin Marinas @ Slightly optimised to avoid incrementing the pointer twice 4038b592783SCatalin Marinas usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 4048b592783SCatalin Marinas .if \rept == 2 4051142b71dSWill Deacon usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 4068b592783SCatalin Marinas .endif 4078b592783SCatalin Marinas 4088b592783SCatalin Marinas add\cond \ptr, #\rept * \inc 4098b592783SCatalin Marinas .endm 4108b592783SCatalin Marinas 4118b592783SCatalin Marinas #else /* !CONFIG_THUMB2_KERNEL */ 4128b592783SCatalin Marinas 4134e7682d0SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 4148b592783SCatalin Marinas .rept \rept 4158b592783SCatalin Marinas 9999: 4168b592783SCatalin Marinas .if \inc == 1 417c001899aSStefan Agner \instr\()b\t\cond \reg, [\ptr], #\inc 4188b592783SCatalin Marinas .elseif \inc == 4 419c001899aSStefan Agner \instr\t\cond \reg, [\ptr], #\inc 4208b592783SCatalin Marinas .else 4218b592783SCatalin Marinas .error "Unsupported inc macro argument" 4228b592783SCatalin Marinas .endif 4238b592783SCatalin Marinas 4244260415fSRussell King .pushsection __ex_table,"a" 4258b592783SCatalin Marinas .align 3 4268b592783SCatalin Marinas .long 9999b, \abort 4274260415fSRussell King .popsection 4288b592783SCatalin Marinas .endr 4298b592783SCatalin Marinas .endm 4308b592783SCatalin Marinas 4318b592783SCatalin Marinas #endif /* CONFIG_THUMB2_KERNEL */ 4328b592783SCatalin Marinas 4338b592783SCatalin Marinas .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 4348b592783SCatalin Marinas usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 4358b592783SCatalin Marinas .endm 4368b592783SCatalin Marinas 4378b592783SCatalin Marinas .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 4388b592783SCatalin Marinas usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 4398b592783SCatalin Marinas .endm 4408f51965eSDave Martin 4418f51965eSDave Martin /* Utility macro for declaring string literals */ 4428f51965eSDave Martin .macro string name:req, string 4438f51965eSDave Martin .type \name , #object 4448f51965eSDave Martin \name: 4458f51965eSDave Martin .asciz "\string" 4468f51965eSDave Martin .size \name , . - \name 4478f51965eSDave Martin .endm 4488f51965eSDave Martin 449a78d1565SRussell King .macro csdb 450a78d1565SRussell King #ifdef CONFIG_THUMB2_KERNEL 451a78d1565SRussell King .inst.w 0xf3af8014 452a78d1565SRussell King #else 453a78d1565SRussell King .inst 0xe320f014 454a78d1565SRussell King #endif 455a78d1565SRussell King .endm 456a78d1565SRussell King 4578404663fSRussell King .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req 4588404663fSRussell King #ifndef CONFIG_CPU_USE_DOMAINS 4598404663fSRussell King adds \tmp, \addr, #\size - 1 460c001899aSStefan Agner sbcscc \tmp, \tmp, \limit 4618404663fSRussell King bcs \bad 462a3c0f847SRussell King #ifdef CONFIG_CPU_SPECTRE 463a3c0f847SRussell King movcs \addr, #0 464a3c0f847SRussell King csdb 465a3c0f847SRussell King #endif 4668404663fSRussell King #endif 4678404663fSRussell King .endm 4688404663fSRussell King 469afaf6838SJulien Thierry .macro uaccess_mask_range_ptr, addr:req, size:req, limit:req, tmp:req 470afaf6838SJulien Thierry #ifdef CONFIG_CPU_SPECTRE 471afaf6838SJulien Thierry sub \tmp, \limit, #1 472afaf6838SJulien Thierry subs \tmp, \tmp, \addr @ tmp = limit - 1 - addr 473afaf6838SJulien Thierry addhs \tmp, \tmp, #1 @ if (tmp >= 0) { 474c001899aSStefan Agner subshs \tmp, \tmp, \size @ tmp = limit - (addr + size) } 475afaf6838SJulien Thierry movlo \addr, #0 @ if (tmp < 0) addr = NULL 476afaf6838SJulien Thierry csdb 477afaf6838SJulien Thierry #endif 478afaf6838SJulien Thierry .endm 479afaf6838SJulien Thierry 4802190fed6SRussell King .macro uaccess_disable, tmp, isb=1 481a5e090acSRussell King #ifdef CONFIG_CPU_SW_DOMAIN_PAN 482a5e090acSRussell King /* 483a5e090acSRussell King * Whenever we re-enter userspace, the domains should always be 484a5e090acSRussell King * set appropriately. 485a5e090acSRussell King */ 486a5e090acSRussell King mov \tmp, #DACR_UACCESS_DISABLE 487a5e090acSRussell King mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register 488a5e090acSRussell King .if \isb 489a5e090acSRussell King instr_sync 490a5e090acSRussell King .endif 491a5e090acSRussell King #endif 4922190fed6SRussell King .endm 4932190fed6SRussell King 4942190fed6SRussell King .macro uaccess_enable, tmp, isb=1 495a5e090acSRussell King #ifdef CONFIG_CPU_SW_DOMAIN_PAN 496a5e090acSRussell King /* 497a5e090acSRussell King * Whenever we re-enter userspace, the domains should always be 498a5e090acSRussell King * set appropriately. 499a5e090acSRussell King */ 500a5e090acSRussell King mov \tmp, #DACR_UACCESS_ENABLE 501a5e090acSRussell King mcr p15, 0, \tmp, c3, c0, 0 502a5e090acSRussell King .if \isb 503a5e090acSRussell King instr_sync 504a5e090acSRussell King .endif 505a5e090acSRussell King #endif 5062190fed6SRussell King .endm 5072190fed6SRussell King 5082190fed6SRussell King .macro uaccess_save, tmp 509a5e090acSRussell King #ifdef CONFIG_CPU_SW_DOMAIN_PAN 510a5e090acSRussell King mrc p15, 0, \tmp, c3, c0, 0 511e6a9dc61SRussell King str \tmp, [sp, #SVC_DACR] 512a5e090acSRussell King #endif 5132190fed6SRussell King .endm 5142190fed6SRussell King 5152190fed6SRussell King .macro uaccess_restore 516a5e090acSRussell King #ifdef CONFIG_CPU_SW_DOMAIN_PAN 517e6a9dc61SRussell King ldr r0, [sp, #SVC_DACR] 518a5e090acSRussell King mcr p15, 0, r0, c3, c0, 0 519a5e090acSRussell King #endif 5202190fed6SRussell King .endm 5212190fed6SRussell King 5226ebbf2ceSRussell King .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 5236ebbf2ceSRussell King .macro ret\c, reg 5246ebbf2ceSRussell King #if __LINUX_ARM_ARCH__ < 6 5256ebbf2ceSRussell King mov\c pc, \reg 5266ebbf2ceSRussell King #else 5276ebbf2ceSRussell King .ifeqs "\reg", "lr" 5286ebbf2ceSRussell King bx\c \reg 5296ebbf2ceSRussell King .else 5306ebbf2ceSRussell King mov\c pc, \reg 5316ebbf2ceSRussell King .endif 5326ebbf2ceSRussell King #endif 5336ebbf2ceSRussell King .endm 5346ebbf2ceSRussell King .endr 5356ebbf2ceSRussell King 5366ebbf2ceSRussell King .macro ret.w, reg 5376ebbf2ceSRussell King ret \reg 5386ebbf2ceSRussell King #ifdef CONFIG_THUMB2_KERNEL 5396ebbf2ceSRussell King nop 5406ebbf2ceSRussell King #endif 5416ebbf2ceSRussell King .endm 5426ebbf2ceSRussell King 5438bafae20SRussell King .macro bug, msg, line 5448bafae20SRussell King #ifdef CONFIG_THUMB2_KERNEL 5458bafae20SRussell King 1: .inst 0xde02 5468bafae20SRussell King #else 5478bafae20SRussell King 1: .inst 0xe7f001f2 5488bafae20SRussell King #endif 5498bafae20SRussell King #ifdef CONFIG_DEBUG_BUGVERBOSE 5508bafae20SRussell King .pushsection .rodata.str, "aMS", %progbits, 1 5518bafae20SRussell King 2: .asciz "\msg" 5528bafae20SRussell King .popsection 5538bafae20SRussell King .pushsection __bug_table, "aw" 5548bafae20SRussell King .align 2 5558bafae20SRussell King .word 1b, 2b 5568bafae20SRussell King .hword \line 5578bafae20SRussell King .popsection 5588bafae20SRussell King #endif 5598bafae20SRussell King .endm 5608bafae20SRussell King 5610d73c3f8SMasami Hiramatsu #ifdef CONFIG_KPROBES 5620d73c3f8SMasami Hiramatsu #define _ASM_NOKPROBE(entry) \ 5630d73c3f8SMasami Hiramatsu .pushsection "_kprobe_blacklist", "aw" ; \ 5640d73c3f8SMasami Hiramatsu .balign 4 ; \ 5650d73c3f8SMasami Hiramatsu .long entry; \ 5660d73c3f8SMasami Hiramatsu .popsection 5670d73c3f8SMasami Hiramatsu #else 5680d73c3f8SMasami Hiramatsu #define _ASM_NOKPROBE(entry) 5690d73c3f8SMasami Hiramatsu #endif 5700d73c3f8SMasami Hiramatsu 5712bc58a6fSMagnus Damm #endif /* __ASM_ASSEMBLER_H__ */ 572