14baa9922SRussell King /* 24baa9922SRussell King * arch/arm/include/asm/assembler.h 34baa9922SRussell King * 44baa9922SRussell King * Copyright (C) 1996-2000 Russell King 54baa9922SRussell King * 64baa9922SRussell King * This program is free software; you can redistribute it and/or modify 74baa9922SRussell King * it under the terms of the GNU General Public License version 2 as 84baa9922SRussell King * published by the Free Software Foundation. 94baa9922SRussell King * 104baa9922SRussell King * This file contains arm architecture specific defines 114baa9922SRussell King * for the different processors. 124baa9922SRussell King * 134baa9922SRussell King * Do not include any C declarations in this file - it is included by 144baa9922SRussell King * assembler source. 154baa9922SRussell King */ 162bc58a6fSMagnus Damm #ifndef __ASM_ASSEMBLER_H__ 172bc58a6fSMagnus Damm #define __ASM_ASSEMBLER_H__ 182bc58a6fSMagnus Damm 194baa9922SRussell King #ifndef __ASSEMBLY__ 204baa9922SRussell King #error "Only include this from assembly code" 214baa9922SRussell King #endif 224baa9922SRussell King 234baa9922SRussell King #include <asm/ptrace.h> 24247055aaSCatalin Marinas #include <asm/domain.h> 2580c59dafSDave Martin #include <asm/opcodes-virt.h> 260b1f68e8SCatalin Marinas #include <asm/asm-offsets.h> 279a2b51b6SAndrey Ryabinin #include <asm/page.h> 289a2b51b6SAndrey Ryabinin #include <asm/thread_info.h> 294baa9922SRussell King 306f6f6a70SRob Herring #define IOMEM(x) (x) 316f6f6a70SRob Herring 324baa9922SRussell King /* 334baa9922SRussell King * Endian independent macros for shifting bytes within registers. 344baa9922SRussell King */ 354baa9922SRussell King #ifndef __ARMEB__ 36d98b90eaSVictor Kamensky #define lspull lsr 37d98b90eaSVictor Kamensky #define lspush lsl 384baa9922SRussell King #define get_byte_0 lsl #0 394baa9922SRussell King #define get_byte_1 lsr #8 404baa9922SRussell King #define get_byte_2 lsr #16 414baa9922SRussell King #define get_byte_3 lsr #24 424baa9922SRussell King #define put_byte_0 lsl #0 434baa9922SRussell King #define put_byte_1 lsl #8 444baa9922SRussell King #define put_byte_2 lsl #16 454baa9922SRussell King #define put_byte_3 lsl #24 464baa9922SRussell King #else 47d98b90eaSVictor Kamensky #define lspull lsl 48d98b90eaSVictor Kamensky #define lspush lsr 494baa9922SRussell King #define get_byte_0 lsr #24 504baa9922SRussell King #define get_byte_1 lsr #16 514baa9922SRussell King #define get_byte_2 lsr #8 524baa9922SRussell King #define get_byte_3 lsl #0 534baa9922SRussell King #define put_byte_0 lsl #24 544baa9922SRussell King #define put_byte_1 lsl #16 554baa9922SRussell King #define put_byte_2 lsl #8 564baa9922SRussell King #define put_byte_3 lsl #0 574baa9922SRussell King #endif 584baa9922SRussell King 59457c2403SBen Dooks /* Select code for any configuration running in BE8 mode */ 60457c2403SBen Dooks #ifdef CONFIG_CPU_ENDIAN_BE8 61457c2403SBen Dooks #define ARM_BE8(code...) code 62457c2403SBen Dooks #else 63457c2403SBen Dooks #define ARM_BE8(code...) 64457c2403SBen Dooks #endif 65457c2403SBen Dooks 664baa9922SRussell King /* 674baa9922SRussell King * Data preload for architectures that support it 684baa9922SRussell King */ 694baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 5 704baa9922SRussell King #define PLD(code...) code 714baa9922SRussell King #else 724baa9922SRussell King #define PLD(code...) 734baa9922SRussell King #endif 744baa9922SRussell King 754baa9922SRussell King /* 764baa9922SRussell King * This can be used to enable code to cacheline align the destination 774baa9922SRussell King * pointer when bulk writing to memory. Experiments on StrongARM and 784baa9922SRussell King * XScale didn't show this a worthwhile thing to do when the cache is not 794baa9922SRussell King * set to write-allocate (this would need further testing on XScale when WA 804baa9922SRussell King * is used). 814baa9922SRussell King * 824baa9922SRussell King * On Feroceon there is much to gain however, regardless of cache mode. 834baa9922SRussell King */ 844baa9922SRussell King #ifdef CONFIG_CPU_FEROCEON 854baa9922SRussell King #define CALGN(code...) code 864baa9922SRussell King #else 874baa9922SRussell King #define CALGN(code...) 884baa9922SRussell King #endif 894baa9922SRussell King 904baa9922SRussell King /* 914baa9922SRussell King * Enable and disable interrupts 924baa9922SRussell King */ 934baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 6 940d928b0bSUwe Kleine-König .macro disable_irq_notrace 954baa9922SRussell King cpsid i 964baa9922SRussell King .endm 974baa9922SRussell King 980d928b0bSUwe Kleine-König .macro enable_irq_notrace 994baa9922SRussell King cpsie i 1004baa9922SRussell King .endm 1014baa9922SRussell King #else 1020d928b0bSUwe Kleine-König .macro disable_irq_notrace 1034baa9922SRussell King msr cpsr_c, #PSR_I_BIT | SVC_MODE 1044baa9922SRussell King .endm 1054baa9922SRussell King 1060d928b0bSUwe Kleine-König .macro enable_irq_notrace 1074baa9922SRussell King msr cpsr_c, #SVC_MODE 1084baa9922SRussell King .endm 1094baa9922SRussell King #endif 1104baa9922SRussell King 1113302caddSRussell King .macro asm_trace_hardirqs_off, save=1 1120d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1133302caddSRussell King .if \save 1140d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1153302caddSRussell King .endif 1160d928b0bSUwe Kleine-König bl trace_hardirqs_off 1173302caddSRussell King .if \save 1180d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1193302caddSRussell King .endif 1200d928b0bSUwe Kleine-König #endif 1210d928b0bSUwe Kleine-König .endm 1220d928b0bSUwe Kleine-König 1233302caddSRussell King .macro asm_trace_hardirqs_on, cond=al, save=1 1240d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1250d928b0bSUwe Kleine-König /* 1260d928b0bSUwe Kleine-König * actually the registers should be pushed and pop'd conditionally, but 1270d928b0bSUwe Kleine-König * after bl the flags are certainly clobbered 1280d928b0bSUwe Kleine-König */ 1293302caddSRussell King .if \save 1300d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1313302caddSRussell King .endif 1320d928b0bSUwe Kleine-König bl\cond trace_hardirqs_on 1333302caddSRussell King .if \save 1340d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1353302caddSRussell King .endif 1360d928b0bSUwe Kleine-König #endif 1370d928b0bSUwe Kleine-König .endm 1380d928b0bSUwe Kleine-König 1393302caddSRussell King .macro disable_irq, save=1 1400d928b0bSUwe Kleine-König disable_irq_notrace 1413302caddSRussell King asm_trace_hardirqs_off \save 1420d928b0bSUwe Kleine-König .endm 1430d928b0bSUwe Kleine-König 1440d928b0bSUwe Kleine-König .macro enable_irq 1450d928b0bSUwe Kleine-König asm_trace_hardirqs_on 1460d928b0bSUwe Kleine-König enable_irq_notrace 1470d928b0bSUwe Kleine-König .endm 1484baa9922SRussell King /* 1494baa9922SRussell King * Save the current IRQ state and disable IRQs. Note that this macro 1504baa9922SRussell King * assumes FIQs are enabled, and that the processor is in SVC mode. 1514baa9922SRussell King */ 1524baa9922SRussell King .macro save_and_disable_irqs, oldcpsr 15355bdd694SCatalin Marinas #ifdef CONFIG_CPU_V7M 15455bdd694SCatalin Marinas mrs \oldcpsr, primask 15555bdd694SCatalin Marinas #else 1564baa9922SRussell King mrs \oldcpsr, cpsr 15755bdd694SCatalin Marinas #endif 1584baa9922SRussell King disable_irq 1594baa9922SRussell King .endm 1604baa9922SRussell King 1618e43a905SRabin Vincent .macro save_and_disable_irqs_notrace, oldcpsr 162b2bf482aSVladimir Murzin #ifdef CONFIG_CPU_V7M 163b2bf482aSVladimir Murzin mrs \oldcpsr, primask 164b2bf482aSVladimir Murzin #else 1658e43a905SRabin Vincent mrs \oldcpsr, cpsr 166b2bf482aSVladimir Murzin #endif 1678e43a905SRabin Vincent disable_irq_notrace 1688e43a905SRabin Vincent .endm 1698e43a905SRabin Vincent 1704baa9922SRussell King /* 1714baa9922SRussell King * Restore interrupt state previously stored in a register. We don't 1724baa9922SRussell King * guarantee that this will preserve the flags. 1734baa9922SRussell King */ 1740d928b0bSUwe Kleine-König .macro restore_irqs_notrace, oldcpsr 17555bdd694SCatalin Marinas #ifdef CONFIG_CPU_V7M 17655bdd694SCatalin Marinas msr primask, \oldcpsr 17755bdd694SCatalin Marinas #else 1784baa9922SRussell King msr cpsr_c, \oldcpsr 17955bdd694SCatalin Marinas #endif 1804baa9922SRussell King .endm 1814baa9922SRussell King 1820d928b0bSUwe Kleine-König .macro restore_irqs, oldcpsr 1830d928b0bSUwe Kleine-König tst \oldcpsr, #PSR_I_BIT 18401e09a28SRussell King asm_trace_hardirqs_on cond=eq 1850d928b0bSUwe Kleine-König restore_irqs_notrace \oldcpsr 1860d928b0bSUwe Kleine-König .endm 1870d928b0bSUwe Kleine-König 18839ad04ccSCatalin Marinas /* 18914327c66SRussell King * Assembly version of "adr rd, BSYM(sym)". This should only be used to 19014327c66SRussell King * reference local symbols in the same assembly file which are to be 19114327c66SRussell King * resolved by the assembler. Other usage is undefined. 19214327c66SRussell King */ 19314327c66SRussell King .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 19414327c66SRussell King .macro badr\c, rd, sym 19514327c66SRussell King #ifdef CONFIG_THUMB2_KERNEL 19614327c66SRussell King adr\c \rd, \sym + 1 19714327c66SRussell King #else 19814327c66SRussell King adr\c \rd, \sym 19914327c66SRussell King #endif 20014327c66SRussell King .endm 20114327c66SRussell King .endr 20214327c66SRussell King 20314327c66SRussell King /* 20439ad04ccSCatalin Marinas * Get current thread_info. 20539ad04ccSCatalin Marinas */ 20639ad04ccSCatalin Marinas .macro get_thread_info, rd 2079a2b51b6SAndrey Ryabinin ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT ) 20839ad04ccSCatalin Marinas THUMB( mov \rd, sp ) 2099a2b51b6SAndrey Ryabinin THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT ) 2109a2b51b6SAndrey Ryabinin mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT 21139ad04ccSCatalin Marinas .endm 21239ad04ccSCatalin Marinas 2130b1f68e8SCatalin Marinas /* 2140b1f68e8SCatalin Marinas * Increment/decrement the preempt count. 2150b1f68e8SCatalin Marinas */ 2160b1f68e8SCatalin Marinas #ifdef CONFIG_PREEMPT_COUNT 2170b1f68e8SCatalin Marinas .macro inc_preempt_count, ti, tmp 2180b1f68e8SCatalin Marinas ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 2190b1f68e8SCatalin Marinas add \tmp, \tmp, #1 @ increment it 2200b1f68e8SCatalin Marinas str \tmp, [\ti, #TI_PREEMPT] 2210b1f68e8SCatalin Marinas .endm 2220b1f68e8SCatalin Marinas 2230b1f68e8SCatalin Marinas .macro dec_preempt_count, ti, tmp 2240b1f68e8SCatalin Marinas ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 2250b1f68e8SCatalin Marinas sub \tmp, \tmp, #1 @ decrement it 2260b1f68e8SCatalin Marinas str \tmp, [\ti, #TI_PREEMPT] 2270b1f68e8SCatalin Marinas .endm 2280b1f68e8SCatalin Marinas 2290b1f68e8SCatalin Marinas .macro dec_preempt_count_ti, ti, tmp 2300b1f68e8SCatalin Marinas get_thread_info \ti 2310b1f68e8SCatalin Marinas dec_preempt_count \ti, \tmp 2320b1f68e8SCatalin Marinas .endm 2330b1f68e8SCatalin Marinas #else 2340b1f68e8SCatalin Marinas .macro inc_preempt_count, ti, tmp 2350b1f68e8SCatalin Marinas .endm 2360b1f68e8SCatalin Marinas 2370b1f68e8SCatalin Marinas .macro dec_preempt_count, ti, tmp 2380b1f68e8SCatalin Marinas .endm 2390b1f68e8SCatalin Marinas 2400b1f68e8SCatalin Marinas .macro dec_preempt_count_ti, ti, tmp 2410b1f68e8SCatalin Marinas .endm 2420b1f68e8SCatalin Marinas #endif 2430b1f68e8SCatalin Marinas 2444baa9922SRussell King #define USER(x...) \ 2454baa9922SRussell King 9999: x; \ 2464260415fSRussell King .pushsection __ex_table,"a"; \ 2474baa9922SRussell King .align 3; \ 2484baa9922SRussell King .long 9999b,9001f; \ 2494260415fSRussell King .popsection 250bac4e960SRussell King 251f00ec48fSRussell King #ifdef CONFIG_SMP 252f00ec48fSRussell King #define ALT_SMP(instr...) \ 253f00ec48fSRussell King 9998: instr 254ed3768a8SDave Martin /* 255ed3768a8SDave Martin * Note: if you get assembler errors from ALT_UP() when building with 256ed3768a8SDave Martin * CONFIG_THUMB2_KERNEL, you almost certainly need to use 257ed3768a8SDave Martin * ALT_SMP( W(instr) ... ) 258ed3768a8SDave Martin */ 259f00ec48fSRussell King #define ALT_UP(instr...) \ 260f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 261f00ec48fSRussell King .long 9998b ;\ 262ed3768a8SDave Martin 9997: instr ;\ 26389c6bc58SRussell King .if . - 9997b == 2 ;\ 26489c6bc58SRussell King nop ;\ 26589c6bc58SRussell King .endif ;\ 266ed3768a8SDave Martin .if . - 9997b != 4 ;\ 267ed3768a8SDave Martin .error "ALT_UP() content must assemble to exactly 4 bytes";\ 268ed3768a8SDave Martin .endif ;\ 269f00ec48fSRussell King .popsection 270f00ec48fSRussell King #define ALT_UP_B(label) \ 271f00ec48fSRussell King .equ up_b_offset, label - 9998b ;\ 272f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 273f00ec48fSRussell King .long 9998b ;\ 274ed3768a8SDave Martin W(b) . + up_b_offset ;\ 275f00ec48fSRussell King .popsection 276f00ec48fSRussell King #else 277f00ec48fSRussell King #define ALT_SMP(instr...) 278f00ec48fSRussell King #define ALT_UP(instr...) instr 279f00ec48fSRussell King #define ALT_UP_B(label) b label 280f00ec48fSRussell King #endif 281f00ec48fSRussell King 282bac4e960SRussell King /* 283d675d0bcSWill Deacon * Instruction barrier 284d675d0bcSWill Deacon */ 285d675d0bcSWill Deacon .macro instr_sync 286d675d0bcSWill Deacon #if __LINUX_ARM_ARCH__ >= 7 287d675d0bcSWill Deacon isb 288d675d0bcSWill Deacon #elif __LINUX_ARM_ARCH__ == 6 289d675d0bcSWill Deacon mcr p15, 0, r0, c7, c5, 4 290d675d0bcSWill Deacon #endif 291d675d0bcSWill Deacon .endm 292d675d0bcSWill Deacon 293d675d0bcSWill Deacon /* 294bac4e960SRussell King * SMP data memory barrier 295bac4e960SRussell King */ 296ed3768a8SDave Martin .macro smp_dmb mode 297bac4e960SRussell King #ifdef CONFIG_SMP 298bac4e960SRussell King #if __LINUX_ARM_ARCH__ >= 7 299ed3768a8SDave Martin .ifeqs "\mode","arm" 3003ea12806SWill Deacon ALT_SMP(dmb ish) 301ed3768a8SDave Martin .else 3023ea12806SWill Deacon ALT_SMP(W(dmb) ish) 303ed3768a8SDave Martin .endif 304bac4e960SRussell King #elif __LINUX_ARM_ARCH__ == 6 305f00ec48fSRussell King ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 306f00ec48fSRussell King #else 307f00ec48fSRussell King #error Incompatible SMP platform 308bac4e960SRussell King #endif 309ed3768a8SDave Martin .ifeqs "\mode","arm" 310f00ec48fSRussell King ALT_UP(nop) 311ed3768a8SDave Martin .else 312ed3768a8SDave Martin ALT_UP(W(nop)) 313ed3768a8SDave Martin .endif 314bac4e960SRussell King #endif 315bac4e960SRussell King .endm 316b86040a5SCatalin Marinas 31755bdd694SCatalin Marinas #if defined(CONFIG_CPU_V7M) 31855bdd694SCatalin Marinas /* 31955bdd694SCatalin Marinas * setmode is used to assert to be in svc mode during boot. For v7-M 32055bdd694SCatalin Marinas * this is done in __v7m_setup, so setmode can be empty here. 32155bdd694SCatalin Marinas */ 32255bdd694SCatalin Marinas .macro setmode, mode, reg 32355bdd694SCatalin Marinas .endm 32455bdd694SCatalin Marinas #elif defined(CONFIG_THUMB2_KERNEL) 325b86040a5SCatalin Marinas .macro setmode, mode, reg 326b86040a5SCatalin Marinas mov \reg, #\mode 327b86040a5SCatalin Marinas msr cpsr_c, \reg 328b86040a5SCatalin Marinas .endm 329b86040a5SCatalin Marinas #else 330b86040a5SCatalin Marinas .macro setmode, mode, reg 331b86040a5SCatalin Marinas msr cpsr_c, #\mode 332b86040a5SCatalin Marinas .endm 333b86040a5SCatalin Marinas #endif 3348b592783SCatalin Marinas 3358b592783SCatalin Marinas /* 33680c59dafSDave Martin * Helper macro to enter SVC mode cleanly and mask interrupts. reg is 33780c59dafSDave Martin * a scratch register for the macro to overwrite. 33880c59dafSDave Martin * 33980c59dafSDave Martin * This macro is intended for forcing the CPU into SVC mode at boot time. 34080c59dafSDave Martin * you cannot return to the original mode. 34180c59dafSDave Martin */ 34280c59dafSDave Martin .macro safe_svcmode_maskall reg:req 3430e0779daSLorenzo Pieralisi #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M) 34480c59dafSDave Martin mrs \reg , cpsr 3458e9c24a2SRussell King eor \reg, \reg, #HYP_MODE 3468e9c24a2SRussell King tst \reg, #MODE_MASK 34780c59dafSDave Martin bic \reg , \reg , #MODE_MASK 3488e9c24a2SRussell King orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE 34980c59dafSDave Martin THUMB( orr \reg , \reg , #PSR_T_BIT ) 35080c59dafSDave Martin bne 1f 3512a552d5eSMarc Zyngier orr \reg, \reg, #PSR_A_BIT 35214327c66SRussell King badr lr, 2f 3532a552d5eSMarc Zyngier msr spsr_cxsf, \reg 35480c59dafSDave Martin __MSR_ELR_HYP(14) 35580c59dafSDave Martin __ERET 3562a552d5eSMarc Zyngier 1: msr cpsr_c, \reg 35780c59dafSDave Martin 2: 3581ecec696SDave Martin #else 3591ecec696SDave Martin /* 3601ecec696SDave Martin * workaround for possibly broken pre-v6 hardware 3611ecec696SDave Martin * (akita, Sharp Zaurus C-1000, PXA270-based) 3621ecec696SDave Martin */ 3631ecec696SDave Martin setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg 3641ecec696SDave Martin #endif 36580c59dafSDave Martin .endm 36680c59dafSDave Martin 36780c59dafSDave Martin /* 3688b592783SCatalin Marinas * STRT/LDRT access macros with ARM and Thumb-2 variants 3698b592783SCatalin Marinas */ 3708b592783SCatalin Marinas #ifdef CONFIG_THUMB2_KERNEL 3718b592783SCatalin Marinas 3724e7682d0SCatalin Marinas .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 3738b592783SCatalin Marinas 9999: 3748b592783SCatalin Marinas .if \inc == 1 375247055aaSCatalin Marinas \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] 3768b592783SCatalin Marinas .elseif \inc == 4 377247055aaSCatalin Marinas \instr\cond\()\t\().w \reg, [\ptr, #\off] 3788b592783SCatalin Marinas .else 3798b592783SCatalin Marinas .error "Unsupported inc macro argument" 3808b592783SCatalin Marinas .endif 3818b592783SCatalin Marinas 3824260415fSRussell King .pushsection __ex_table,"a" 3838b592783SCatalin Marinas .align 3 3848b592783SCatalin Marinas .long 9999b, \abort 3854260415fSRussell King .popsection 3868b592783SCatalin Marinas .endm 3878b592783SCatalin Marinas 3888b592783SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort 3898b592783SCatalin Marinas @ explicit IT instruction needed because of the label 3908b592783SCatalin Marinas @ introduced by the USER macro 3918b592783SCatalin Marinas .ifnc \cond,al 3928b592783SCatalin Marinas .if \rept == 1 3938b592783SCatalin Marinas itt \cond 3948b592783SCatalin Marinas .elseif \rept == 2 3958b592783SCatalin Marinas ittt \cond 3968b592783SCatalin Marinas .else 3978b592783SCatalin Marinas .error "Unsupported rept macro argument" 3988b592783SCatalin Marinas .endif 3998b592783SCatalin Marinas .endif 4008b592783SCatalin Marinas 4018b592783SCatalin Marinas @ Slightly optimised to avoid incrementing the pointer twice 4028b592783SCatalin Marinas usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 4038b592783SCatalin Marinas .if \rept == 2 4041142b71dSWill Deacon usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 4058b592783SCatalin Marinas .endif 4068b592783SCatalin Marinas 4078b592783SCatalin Marinas add\cond \ptr, #\rept * \inc 4088b592783SCatalin Marinas .endm 4098b592783SCatalin Marinas 4108b592783SCatalin Marinas #else /* !CONFIG_THUMB2_KERNEL */ 4118b592783SCatalin Marinas 4124e7682d0SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 4138b592783SCatalin Marinas .rept \rept 4148b592783SCatalin Marinas 9999: 4158b592783SCatalin Marinas .if \inc == 1 416247055aaSCatalin Marinas \instr\cond\()b\()\t \reg, [\ptr], #\inc 4178b592783SCatalin Marinas .elseif \inc == 4 418247055aaSCatalin Marinas \instr\cond\()\t \reg, [\ptr], #\inc 4198b592783SCatalin Marinas .else 4208b592783SCatalin Marinas .error "Unsupported inc macro argument" 4218b592783SCatalin Marinas .endif 4228b592783SCatalin Marinas 4234260415fSRussell King .pushsection __ex_table,"a" 4248b592783SCatalin Marinas .align 3 4258b592783SCatalin Marinas .long 9999b, \abort 4264260415fSRussell King .popsection 4278b592783SCatalin Marinas .endr 4288b592783SCatalin Marinas .endm 4298b592783SCatalin Marinas 4308b592783SCatalin Marinas #endif /* CONFIG_THUMB2_KERNEL */ 4318b592783SCatalin Marinas 4328b592783SCatalin Marinas .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 4338b592783SCatalin Marinas usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 4348b592783SCatalin Marinas .endm 4358b592783SCatalin Marinas 4368b592783SCatalin Marinas .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 4378b592783SCatalin Marinas usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 4388b592783SCatalin Marinas .endm 4398f51965eSDave Martin 4408f51965eSDave Martin /* Utility macro for declaring string literals */ 4418f51965eSDave Martin .macro string name:req, string 4428f51965eSDave Martin .type \name , #object 4438f51965eSDave Martin \name: 4448f51965eSDave Martin .asciz "\string" 4458f51965eSDave Martin .size \name , . - \name 4468f51965eSDave Martin .endm 4478f51965eSDave Martin 4488404663fSRussell King .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req 4498404663fSRussell King #ifndef CONFIG_CPU_USE_DOMAINS 4508404663fSRussell King adds \tmp, \addr, #\size - 1 4518404663fSRussell King sbcccs \tmp, \tmp, \limit 4528404663fSRussell King bcs \bad 4538404663fSRussell King #endif 4548404663fSRussell King .endm 4558404663fSRussell King 4562190fed6SRussell King .macro uaccess_disable, tmp, isb=1 457a5e090acSRussell King #ifdef CONFIG_CPU_SW_DOMAIN_PAN 458a5e090acSRussell King /* 459a5e090acSRussell King * Whenever we re-enter userspace, the domains should always be 460a5e090acSRussell King * set appropriately. 461a5e090acSRussell King */ 462a5e090acSRussell King mov \tmp, #DACR_UACCESS_DISABLE 463a5e090acSRussell King mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register 464a5e090acSRussell King .if \isb 465a5e090acSRussell King instr_sync 466a5e090acSRussell King .endif 467a5e090acSRussell King #endif 4682190fed6SRussell King .endm 4692190fed6SRussell King 4702190fed6SRussell King .macro uaccess_enable, tmp, isb=1 471a5e090acSRussell King #ifdef CONFIG_CPU_SW_DOMAIN_PAN 472a5e090acSRussell King /* 473a5e090acSRussell King * Whenever we re-enter userspace, the domains should always be 474a5e090acSRussell King * set appropriately. 475a5e090acSRussell King */ 476a5e090acSRussell King mov \tmp, #DACR_UACCESS_ENABLE 477a5e090acSRussell King mcr p15, 0, \tmp, c3, c0, 0 478a5e090acSRussell King .if \isb 479a5e090acSRussell King instr_sync 480a5e090acSRussell King .endif 481a5e090acSRussell King #endif 4822190fed6SRussell King .endm 4832190fed6SRussell King 4842190fed6SRussell King .macro uaccess_save, tmp 485a5e090acSRussell King #ifdef CONFIG_CPU_SW_DOMAIN_PAN 486a5e090acSRussell King mrc p15, 0, \tmp, c3, c0, 0 487e6a9dc61SRussell King str \tmp, [sp, #SVC_DACR] 488a5e090acSRussell King #endif 4892190fed6SRussell King .endm 4902190fed6SRussell King 4912190fed6SRussell King .macro uaccess_restore 492a5e090acSRussell King #ifdef CONFIG_CPU_SW_DOMAIN_PAN 493e6a9dc61SRussell King ldr r0, [sp, #SVC_DACR] 494a5e090acSRussell King mcr p15, 0, r0, c3, c0, 0 495a5e090acSRussell King #endif 4962190fed6SRussell King .endm 4972190fed6SRussell King 4986ebbf2ceSRussell King .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 4996ebbf2ceSRussell King .macro ret\c, reg 5006ebbf2ceSRussell King #if __LINUX_ARM_ARCH__ < 6 5016ebbf2ceSRussell King mov\c pc, \reg 5026ebbf2ceSRussell King #else 5036ebbf2ceSRussell King .ifeqs "\reg", "lr" 5046ebbf2ceSRussell King bx\c \reg 5056ebbf2ceSRussell King .else 5066ebbf2ceSRussell King mov\c pc, \reg 5076ebbf2ceSRussell King .endif 5086ebbf2ceSRussell King #endif 5096ebbf2ceSRussell King .endm 5106ebbf2ceSRussell King .endr 5116ebbf2ceSRussell King 5126ebbf2ceSRussell King .macro ret.w, reg 5136ebbf2ceSRussell King ret \reg 5146ebbf2ceSRussell King #ifdef CONFIG_THUMB2_KERNEL 5156ebbf2ceSRussell King nop 5166ebbf2ceSRussell King #endif 5176ebbf2ceSRussell King .endm 5186ebbf2ceSRussell King 5192bc58a6fSMagnus Damm #endif /* __ASM_ASSEMBLER_H__ */ 520