1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24baa9922SRussell King /* 34baa9922SRussell King * arch/arm/include/asm/assembler.h 44baa9922SRussell King * 54baa9922SRussell King * Copyright (C) 1996-2000 Russell King 64baa9922SRussell King * 74baa9922SRussell King * This file contains arm architecture specific defines 84baa9922SRussell King * for the different processors. 94baa9922SRussell King * 104baa9922SRussell King * Do not include any C declarations in this file - it is included by 114baa9922SRussell King * assembler source. 124baa9922SRussell King */ 132bc58a6fSMagnus Damm #ifndef __ASM_ASSEMBLER_H__ 142bc58a6fSMagnus Damm #define __ASM_ASSEMBLER_H__ 152bc58a6fSMagnus Damm 164baa9922SRussell King #ifndef __ASSEMBLY__ 174baa9922SRussell King #error "Only include this from assembly code" 184baa9922SRussell King #endif 194baa9922SRussell King 204baa9922SRussell King #include <asm/ptrace.h> 2180c59dafSDave Martin #include <asm/opcodes-virt.h> 220b1f68e8SCatalin Marinas #include <asm/asm-offsets.h> 239a2b51b6SAndrey Ryabinin #include <asm/page.h> 249a2b51b6SAndrey Ryabinin #include <asm/thread_info.h> 25747ffc2fSRussell King #include <asm/uaccess-asm.h> 264baa9922SRussell King 276f6f6a70SRob Herring #define IOMEM(x) (x) 286f6f6a70SRob Herring 294baa9922SRussell King /* 304baa9922SRussell King * Endian independent macros for shifting bytes within registers. 314baa9922SRussell King */ 324baa9922SRussell King #ifndef __ARMEB__ 33d98b90eaSVictor Kamensky #define lspull lsr 34d98b90eaSVictor Kamensky #define lspush lsl 354baa9922SRussell King #define get_byte_0 lsl #0 364baa9922SRussell King #define get_byte_1 lsr #8 374baa9922SRussell King #define get_byte_2 lsr #16 384baa9922SRussell King #define get_byte_3 lsr #24 394baa9922SRussell King #define put_byte_0 lsl #0 404baa9922SRussell King #define put_byte_1 lsl #8 414baa9922SRussell King #define put_byte_2 lsl #16 424baa9922SRussell King #define put_byte_3 lsl #24 434baa9922SRussell King #else 44d98b90eaSVictor Kamensky #define lspull lsl 45d98b90eaSVictor Kamensky #define lspush lsr 464baa9922SRussell King #define get_byte_0 lsr #24 474baa9922SRussell King #define get_byte_1 lsr #16 484baa9922SRussell King #define get_byte_2 lsr #8 494baa9922SRussell King #define get_byte_3 lsl #0 504baa9922SRussell King #define put_byte_0 lsl #24 514baa9922SRussell King #define put_byte_1 lsl #16 524baa9922SRussell King #define put_byte_2 lsl #8 534baa9922SRussell King #define put_byte_3 lsl #0 544baa9922SRussell King #endif 554baa9922SRussell King 56457c2403SBen Dooks /* Select code for any configuration running in BE8 mode */ 57457c2403SBen Dooks #ifdef CONFIG_CPU_ENDIAN_BE8 58457c2403SBen Dooks #define ARM_BE8(code...) code 59457c2403SBen Dooks #else 60457c2403SBen Dooks #define ARM_BE8(code...) 61457c2403SBen Dooks #endif 62457c2403SBen Dooks 634baa9922SRussell King /* 644baa9922SRussell King * Data preload for architectures that support it 654baa9922SRussell King */ 664baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 5 674baa9922SRussell King #define PLD(code...) code 684baa9922SRussell King #else 694baa9922SRussell King #define PLD(code...) 704baa9922SRussell King #endif 714baa9922SRussell King 724baa9922SRussell King /* 734baa9922SRussell King * This can be used to enable code to cacheline align the destination 744baa9922SRussell King * pointer when bulk writing to memory. Experiments on StrongARM and 754baa9922SRussell King * XScale didn't show this a worthwhile thing to do when the cache is not 764baa9922SRussell King * set to write-allocate (this would need further testing on XScale when WA 774baa9922SRussell King * is used). 784baa9922SRussell King * 794baa9922SRussell King * On Feroceon there is much to gain however, regardless of cache mode. 804baa9922SRussell King */ 814baa9922SRussell King #ifdef CONFIG_CPU_FEROCEON 824baa9922SRussell King #define CALGN(code...) code 834baa9922SRussell King #else 844baa9922SRussell King #define CALGN(code...) 854baa9922SRussell King #endif 864baa9922SRussell King 87ffa47aa6SArnd Bergmann #define IMM12_MASK 0xfff 88ffa47aa6SArnd Bergmann 89d4664b6cSArd Biesheuvel /* the frame pointer used for stack unwinding */ 90d4664b6cSArd Biesheuvel ARM( fpreg .req r11 ) 91d4664b6cSArd Biesheuvel THUMB( fpreg .req r7 ) 92d4664b6cSArd Biesheuvel 934baa9922SRussell King /* 944baa9922SRussell King * Enable and disable interrupts 954baa9922SRussell King */ 964baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 6 970d928b0bSUwe Kleine-König .macro disable_irq_notrace 984baa9922SRussell King cpsid i 994baa9922SRussell King .endm 1004baa9922SRussell King 1010d928b0bSUwe Kleine-König .macro enable_irq_notrace 1024baa9922SRussell King cpsie i 1034baa9922SRussell King .endm 1044baa9922SRussell King #else 1050d928b0bSUwe Kleine-König .macro disable_irq_notrace 1064baa9922SRussell King msr cpsr_c, #PSR_I_BIT | SVC_MODE 1074baa9922SRussell King .endm 1084baa9922SRussell King 1090d928b0bSUwe Kleine-König .macro enable_irq_notrace 1104baa9922SRussell King msr cpsr_c, #SVC_MODE 1114baa9922SRussell King .endm 1124baa9922SRussell King #endif 1134baa9922SRussell King 1143302caddSRussell King .macro asm_trace_hardirqs_off, save=1 1150d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1163302caddSRussell King .if \save 1170d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1183302caddSRussell King .endif 1190d928b0bSUwe Kleine-König bl trace_hardirqs_off 1203302caddSRussell King .if \save 1210d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1223302caddSRussell King .endif 1230d928b0bSUwe Kleine-König #endif 1240d928b0bSUwe Kleine-König .endm 1250d928b0bSUwe Kleine-König 1263302caddSRussell King .macro asm_trace_hardirqs_on, cond=al, save=1 1270d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1280d928b0bSUwe Kleine-König /* 1290d928b0bSUwe Kleine-König * actually the registers should be pushed and pop'd conditionally, but 1300d928b0bSUwe Kleine-König * after bl the flags are certainly clobbered 1310d928b0bSUwe Kleine-König */ 1323302caddSRussell King .if \save 1330d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1343302caddSRussell King .endif 1350d928b0bSUwe Kleine-König bl\cond trace_hardirqs_on 1363302caddSRussell King .if \save 1370d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1383302caddSRussell King .endif 1390d928b0bSUwe Kleine-König #endif 1400d928b0bSUwe Kleine-König .endm 1410d928b0bSUwe Kleine-König 1423302caddSRussell King .macro disable_irq, save=1 1430d928b0bSUwe Kleine-König disable_irq_notrace 1443302caddSRussell King asm_trace_hardirqs_off \save 1450d928b0bSUwe Kleine-König .endm 1460d928b0bSUwe Kleine-König 1470d928b0bSUwe Kleine-König .macro enable_irq 1480d928b0bSUwe Kleine-König asm_trace_hardirqs_on 1490d928b0bSUwe Kleine-König enable_irq_notrace 1500d928b0bSUwe Kleine-König .endm 1514baa9922SRussell King /* 1524baa9922SRussell King * Save the current IRQ state and disable IRQs. Note that this macro 1534baa9922SRussell King * assumes FIQs are enabled, and that the processor is in SVC mode. 1544baa9922SRussell King */ 1554baa9922SRussell King .macro save_and_disable_irqs, oldcpsr 15655bdd694SCatalin Marinas #ifdef CONFIG_CPU_V7M 15755bdd694SCatalin Marinas mrs \oldcpsr, primask 15855bdd694SCatalin Marinas #else 1594baa9922SRussell King mrs \oldcpsr, cpsr 16055bdd694SCatalin Marinas #endif 1614baa9922SRussell King disable_irq 1624baa9922SRussell King .endm 1634baa9922SRussell King 1648e43a905SRabin Vincent .macro save_and_disable_irqs_notrace, oldcpsr 165b2bf482aSVladimir Murzin #ifdef CONFIG_CPU_V7M 166b2bf482aSVladimir Murzin mrs \oldcpsr, primask 167b2bf482aSVladimir Murzin #else 1688e43a905SRabin Vincent mrs \oldcpsr, cpsr 169b2bf482aSVladimir Murzin #endif 1708e43a905SRabin Vincent disable_irq_notrace 1718e43a905SRabin Vincent .endm 1728e43a905SRabin Vincent 1734baa9922SRussell King /* 1744baa9922SRussell King * Restore interrupt state previously stored in a register. We don't 1754baa9922SRussell King * guarantee that this will preserve the flags. 1764baa9922SRussell King */ 1770d928b0bSUwe Kleine-König .macro restore_irqs_notrace, oldcpsr 17855bdd694SCatalin Marinas #ifdef CONFIG_CPU_V7M 17955bdd694SCatalin Marinas msr primask, \oldcpsr 18055bdd694SCatalin Marinas #else 1814baa9922SRussell King msr cpsr_c, \oldcpsr 18255bdd694SCatalin Marinas #endif 1834baa9922SRussell King .endm 1844baa9922SRussell King 1850d928b0bSUwe Kleine-König .macro restore_irqs, oldcpsr 1860d928b0bSUwe Kleine-König tst \oldcpsr, #PSR_I_BIT 18701e09a28SRussell King asm_trace_hardirqs_on cond=eq 1880d928b0bSUwe Kleine-König restore_irqs_notrace \oldcpsr 1890d928b0bSUwe Kleine-König .endm 1900d928b0bSUwe Kleine-König 19139ad04ccSCatalin Marinas /* 19214327c66SRussell King * Assembly version of "adr rd, BSYM(sym)". This should only be used to 19314327c66SRussell King * reference local symbols in the same assembly file which are to be 19414327c66SRussell King * resolved by the assembler. Other usage is undefined. 19514327c66SRussell King */ 19614327c66SRussell King .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 19714327c66SRussell King .macro badr\c, rd, sym 19814327c66SRussell King #ifdef CONFIG_THUMB2_KERNEL 19914327c66SRussell King adr\c \rd, \sym + 1 20014327c66SRussell King #else 20114327c66SRussell King adr\c \rd, \sym 20214327c66SRussell King #endif 20314327c66SRussell King .endm 20414327c66SRussell King .endr 20514327c66SRussell King 20614327c66SRussell King /* 20739ad04ccSCatalin Marinas * Get current thread_info. 20839ad04ccSCatalin Marinas */ 20939ad04ccSCatalin Marinas .macro get_thread_info, rd 21018ed1c01SArd Biesheuvel /* thread_info is the first member of struct task_struct */ 21118ed1c01SArd Biesheuvel get_current \rd 21239ad04ccSCatalin Marinas .endm 21339ad04ccSCatalin Marinas 2140b1f68e8SCatalin Marinas /* 2150b1f68e8SCatalin Marinas * Increment/decrement the preempt count. 2160b1f68e8SCatalin Marinas */ 2170b1f68e8SCatalin Marinas #ifdef CONFIG_PREEMPT_COUNT 2180b1f68e8SCatalin Marinas .macro inc_preempt_count, ti, tmp 2190b1f68e8SCatalin Marinas ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 2200b1f68e8SCatalin Marinas add \tmp, \tmp, #1 @ increment it 2210b1f68e8SCatalin Marinas str \tmp, [\ti, #TI_PREEMPT] 2220b1f68e8SCatalin Marinas .endm 2230b1f68e8SCatalin Marinas 2240b1f68e8SCatalin Marinas .macro dec_preempt_count, ti, tmp 2250b1f68e8SCatalin Marinas ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 2260b1f68e8SCatalin Marinas sub \tmp, \tmp, #1 @ decrement it 2270b1f68e8SCatalin Marinas str \tmp, [\ti, #TI_PREEMPT] 2280b1f68e8SCatalin Marinas .endm 2290b1f68e8SCatalin Marinas 2300b1f68e8SCatalin Marinas .macro dec_preempt_count_ti, ti, tmp 2310b1f68e8SCatalin Marinas get_thread_info \ti 2320b1f68e8SCatalin Marinas dec_preempt_count \ti, \tmp 2330b1f68e8SCatalin Marinas .endm 2340b1f68e8SCatalin Marinas #else 2350b1f68e8SCatalin Marinas .macro inc_preempt_count, ti, tmp 2360b1f68e8SCatalin Marinas .endm 2370b1f68e8SCatalin Marinas 2380b1f68e8SCatalin Marinas .macro dec_preempt_count, ti, tmp 2390b1f68e8SCatalin Marinas .endm 2400b1f68e8SCatalin Marinas 2410b1f68e8SCatalin Marinas .macro dec_preempt_count_ti, ti, tmp 2420b1f68e8SCatalin Marinas .endm 2430b1f68e8SCatalin Marinas #endif 2440b1f68e8SCatalin Marinas 245f441882aSVincent Whitchurch #define USERL(l, x...) \ 2464baa9922SRussell King 9999: x; \ 2474260415fSRussell King .pushsection __ex_table,"a"; \ 2484baa9922SRussell King .align 3; \ 249f441882aSVincent Whitchurch .long 9999b,l; \ 2504260415fSRussell King .popsection 251bac4e960SRussell King 252f441882aSVincent Whitchurch #define USER(x...) USERL(9001f, x) 253f441882aSVincent Whitchurch 254f00ec48fSRussell King #ifdef CONFIG_SMP 255f00ec48fSRussell King #define ALT_SMP(instr...) \ 256f00ec48fSRussell King 9998: instr 257ed3768a8SDave Martin /* 258ed3768a8SDave Martin * Note: if you get assembler errors from ALT_UP() when building with 259ed3768a8SDave Martin * CONFIG_THUMB2_KERNEL, you almost certainly need to use 260ed3768a8SDave Martin * ALT_SMP( W(instr) ... ) 261ed3768a8SDave Martin */ 262f00ec48fSRussell King #define ALT_UP(instr...) \ 263f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 264450abd38SArd Biesheuvel .long 9998b - . ;\ 265ed3768a8SDave Martin 9997: instr ;\ 26689c6bc58SRussell King .if . - 9997b == 2 ;\ 26789c6bc58SRussell King nop ;\ 26889c6bc58SRussell King .endif ;\ 269ed3768a8SDave Martin .if . - 9997b != 4 ;\ 270ed3768a8SDave Martin .error "ALT_UP() content must assemble to exactly 4 bytes";\ 271ed3768a8SDave Martin .endif ;\ 272f00ec48fSRussell King .popsection 273f00ec48fSRussell King #define ALT_UP_B(label) \ 274f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 275450abd38SArd Biesheuvel .long 9998b - . ;\ 276a780e485SJian Cai W(b) . + (label - 9998b) ;\ 277f00ec48fSRussell King .popsection 278f00ec48fSRussell King #else 279f00ec48fSRussell King #define ALT_SMP(instr...) 280f00ec48fSRussell King #define ALT_UP(instr...) instr 281f00ec48fSRussell King #define ALT_UP_B(label) b label 282f00ec48fSRussell King #endif 283f00ec48fSRussell King 284bac4e960SRussell King /* 2857b9896c3SArd Biesheuvel * this_cpu_offset - load the per-CPU offset of this CPU into 2867b9896c3SArd Biesheuvel * register 'rd' 2877b9896c3SArd Biesheuvel */ 2887b9896c3SArd Biesheuvel .macro this_cpu_offset, rd:req 2897b9896c3SArd Biesheuvel #ifdef CONFIG_SMP 2907b9896c3SArd Biesheuvel ALT_SMP(mrc p15, 0, \rd, c13, c0, 4) 2917b9896c3SArd Biesheuvel #ifdef CONFIG_CPU_V6 2927b9896c3SArd Biesheuvel ALT_UP_B(.L1_\@) 2937b9896c3SArd Biesheuvel .L0_\@: 2947b9896c3SArd Biesheuvel .subsection 1 2957b9896c3SArd Biesheuvel .L1_\@: ldr_va \rd, __per_cpu_offset 2967b9896c3SArd Biesheuvel b .L0_\@ 2977b9896c3SArd Biesheuvel .previous 2987b9896c3SArd Biesheuvel #endif 2997b9896c3SArd Biesheuvel #else 3007b9896c3SArd Biesheuvel mov \rd, #0 3017b9896c3SArd Biesheuvel #endif 3027b9896c3SArd Biesheuvel .endm 3037b9896c3SArd Biesheuvel 3047b9896c3SArd Biesheuvel /* 305*9c46929eSArd Biesheuvel * set_current - store the task pointer of this CPU's current task 306*9c46929eSArd Biesheuvel */ 307*9c46929eSArd Biesheuvel .macro set_current, rn:req, tmp:req 308*9c46929eSArd Biesheuvel #if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP) 309*9c46929eSArd Biesheuvel 9998: mcr p15, 0, \rn, c13, c0, 3 @ set TPIDRURO register 310*9c46929eSArd Biesheuvel #ifdef CONFIG_CPU_V6 311*9c46929eSArd Biesheuvel ALT_UP_B(.L0_\@) 312*9c46929eSArd Biesheuvel .subsection 1 313*9c46929eSArd Biesheuvel .L0_\@: str_va \rn, __current, \tmp 314*9c46929eSArd Biesheuvel b .L1_\@ 315*9c46929eSArd Biesheuvel .previous 316*9c46929eSArd Biesheuvel .L1_\@: 317*9c46929eSArd Biesheuvel #endif 318*9c46929eSArd Biesheuvel #else 319*9c46929eSArd Biesheuvel str_va \rn, __current, \tmp 320*9c46929eSArd Biesheuvel #endif 321*9c46929eSArd Biesheuvel .endm 322*9c46929eSArd Biesheuvel 323*9c46929eSArd Biesheuvel /* 324*9c46929eSArd Biesheuvel * get_current - load the task pointer of this CPU's current task 325*9c46929eSArd Biesheuvel */ 326*9c46929eSArd Biesheuvel .macro get_current, rd:req 327*9c46929eSArd Biesheuvel #if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP) 328*9c46929eSArd Biesheuvel 9998: mrc p15, 0, \rd, c13, c0, 3 @ get TPIDRURO register 329*9c46929eSArd Biesheuvel #ifdef CONFIG_CPU_V6 330*9c46929eSArd Biesheuvel ALT_UP_B(.L0_\@) 331*9c46929eSArd Biesheuvel .subsection 1 332*9c46929eSArd Biesheuvel .L0_\@: ldr_va \rd, __current 333*9c46929eSArd Biesheuvel b .L1_\@ 334*9c46929eSArd Biesheuvel .previous 335*9c46929eSArd Biesheuvel .L1_\@: 336*9c46929eSArd Biesheuvel #endif 337*9c46929eSArd Biesheuvel #else 338*9c46929eSArd Biesheuvel ldr_va \rd, __current 339*9c46929eSArd Biesheuvel #endif 340*9c46929eSArd Biesheuvel .endm 341*9c46929eSArd Biesheuvel 342*9c46929eSArd Biesheuvel /* 343*9c46929eSArd Biesheuvel * reload_current - reload the task pointer of this CPU's current task 344*9c46929eSArd Biesheuvel * into the TLS register 345*9c46929eSArd Biesheuvel */ 346*9c46929eSArd Biesheuvel .macro reload_current, t1:req, t2:req 347*9c46929eSArd Biesheuvel #if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP) 348*9c46929eSArd Biesheuvel #ifdef CONFIG_CPU_V6 349*9c46929eSArd Biesheuvel ALT_SMP(nop) 350*9c46929eSArd Biesheuvel ALT_UP_B(.L0_\@) 351*9c46929eSArd Biesheuvel #endif 352*9c46929eSArd Biesheuvel ldr_this_cpu \t1, __entry_task, \t1, \t2 353*9c46929eSArd Biesheuvel mcr p15, 0, \t1, c13, c0, 3 @ store in TPIDRURO 354*9c46929eSArd Biesheuvel .L0_\@: 355*9c46929eSArd Biesheuvel #endif 356*9c46929eSArd Biesheuvel .endm 357*9c46929eSArd Biesheuvel 358*9c46929eSArd Biesheuvel /* 359d675d0bcSWill Deacon * Instruction barrier 360d675d0bcSWill Deacon */ 361d675d0bcSWill Deacon .macro instr_sync 362d675d0bcSWill Deacon #if __LINUX_ARM_ARCH__ >= 7 363d675d0bcSWill Deacon isb 364d675d0bcSWill Deacon #elif __LINUX_ARM_ARCH__ == 6 365d675d0bcSWill Deacon mcr p15, 0, r0, c7, c5, 4 366d675d0bcSWill Deacon #endif 367d675d0bcSWill Deacon .endm 368d675d0bcSWill Deacon 369d675d0bcSWill Deacon /* 370bac4e960SRussell King * SMP data memory barrier 371bac4e960SRussell King */ 372ed3768a8SDave Martin .macro smp_dmb mode 373bac4e960SRussell King #ifdef CONFIG_SMP 374bac4e960SRussell King #if __LINUX_ARM_ARCH__ >= 7 375ed3768a8SDave Martin .ifeqs "\mode","arm" 3763ea12806SWill Deacon ALT_SMP(dmb ish) 377ed3768a8SDave Martin .else 3783ea12806SWill Deacon ALT_SMP(W(dmb) ish) 379ed3768a8SDave Martin .endif 380bac4e960SRussell King #elif __LINUX_ARM_ARCH__ == 6 381f00ec48fSRussell King ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 382f00ec48fSRussell King #else 383f00ec48fSRussell King #error Incompatible SMP platform 384bac4e960SRussell King #endif 385ed3768a8SDave Martin .ifeqs "\mode","arm" 386f00ec48fSRussell King ALT_UP(nop) 387ed3768a8SDave Martin .else 388ed3768a8SDave Martin ALT_UP(W(nop)) 389ed3768a8SDave Martin .endif 390bac4e960SRussell King #endif 391bac4e960SRussell King .endm 392b86040a5SCatalin Marinas 39355bdd694SCatalin Marinas #if defined(CONFIG_CPU_V7M) 39455bdd694SCatalin Marinas /* 39555bdd694SCatalin Marinas * setmode is used to assert to be in svc mode during boot. For v7-M 39655bdd694SCatalin Marinas * this is done in __v7m_setup, so setmode can be empty here. 39755bdd694SCatalin Marinas */ 39855bdd694SCatalin Marinas .macro setmode, mode, reg 39955bdd694SCatalin Marinas .endm 40055bdd694SCatalin Marinas #elif defined(CONFIG_THUMB2_KERNEL) 401b86040a5SCatalin Marinas .macro setmode, mode, reg 402b86040a5SCatalin Marinas mov \reg, #\mode 403b86040a5SCatalin Marinas msr cpsr_c, \reg 404b86040a5SCatalin Marinas .endm 405b86040a5SCatalin Marinas #else 406b86040a5SCatalin Marinas .macro setmode, mode, reg 407b86040a5SCatalin Marinas msr cpsr_c, #\mode 408b86040a5SCatalin Marinas .endm 409b86040a5SCatalin Marinas #endif 4108b592783SCatalin Marinas 4118b592783SCatalin Marinas /* 41280c59dafSDave Martin * Helper macro to enter SVC mode cleanly and mask interrupts. reg is 41380c59dafSDave Martin * a scratch register for the macro to overwrite. 41480c59dafSDave Martin * 41580c59dafSDave Martin * This macro is intended for forcing the CPU into SVC mode at boot time. 41680c59dafSDave Martin * you cannot return to the original mode. 41780c59dafSDave Martin */ 41880c59dafSDave Martin .macro safe_svcmode_maskall reg:req 4190e0779daSLorenzo Pieralisi #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M) 42080c59dafSDave Martin mrs \reg , cpsr 4218e9c24a2SRussell King eor \reg, \reg, #HYP_MODE 4228e9c24a2SRussell King tst \reg, #MODE_MASK 42380c59dafSDave Martin bic \reg , \reg , #MODE_MASK 4248e9c24a2SRussell King orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE 42580c59dafSDave Martin THUMB( orr \reg , \reg , #PSR_T_BIT ) 42680c59dafSDave Martin bne 1f 4272a552d5eSMarc Zyngier orr \reg, \reg, #PSR_A_BIT 42814327c66SRussell King badr lr, 2f 4292a552d5eSMarc Zyngier msr spsr_cxsf, \reg 43080c59dafSDave Martin __MSR_ELR_HYP(14) 43180c59dafSDave Martin __ERET 4322a552d5eSMarc Zyngier 1: msr cpsr_c, \reg 43380c59dafSDave Martin 2: 4341ecec696SDave Martin #else 4351ecec696SDave Martin /* 4361ecec696SDave Martin * workaround for possibly broken pre-v6 hardware 4371ecec696SDave Martin * (akita, Sharp Zaurus C-1000, PXA270-based) 4381ecec696SDave Martin */ 4391ecec696SDave Martin setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg 4401ecec696SDave Martin #endif 44180c59dafSDave Martin .endm 44280c59dafSDave Martin 44380c59dafSDave Martin /* 4448b592783SCatalin Marinas * STRT/LDRT access macros with ARM and Thumb-2 variants 4458b592783SCatalin Marinas */ 4468b592783SCatalin Marinas #ifdef CONFIG_THUMB2_KERNEL 4478b592783SCatalin Marinas 4484e7682d0SCatalin Marinas .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 4498b592783SCatalin Marinas 9999: 4508b592783SCatalin Marinas .if \inc == 1 451c001899aSStefan Agner \instr\()b\t\cond\().w \reg, [\ptr, #\off] 4528b592783SCatalin Marinas .elseif \inc == 4 453c001899aSStefan Agner \instr\t\cond\().w \reg, [\ptr, #\off] 4548b592783SCatalin Marinas .else 4558b592783SCatalin Marinas .error "Unsupported inc macro argument" 4568b592783SCatalin Marinas .endif 4578b592783SCatalin Marinas 4584260415fSRussell King .pushsection __ex_table,"a" 4598b592783SCatalin Marinas .align 3 4608b592783SCatalin Marinas .long 9999b, \abort 4614260415fSRussell King .popsection 4628b592783SCatalin Marinas .endm 4638b592783SCatalin Marinas 4648b592783SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort 4658b592783SCatalin Marinas @ explicit IT instruction needed because of the label 4668b592783SCatalin Marinas @ introduced by the USER macro 4678b592783SCatalin Marinas .ifnc \cond,al 4688b592783SCatalin Marinas .if \rept == 1 4698b592783SCatalin Marinas itt \cond 4708b592783SCatalin Marinas .elseif \rept == 2 4718b592783SCatalin Marinas ittt \cond 4728b592783SCatalin Marinas .else 4738b592783SCatalin Marinas .error "Unsupported rept macro argument" 4748b592783SCatalin Marinas .endif 4758b592783SCatalin Marinas .endif 4768b592783SCatalin Marinas 4778b592783SCatalin Marinas @ Slightly optimised to avoid incrementing the pointer twice 4788b592783SCatalin Marinas usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 4798b592783SCatalin Marinas .if \rept == 2 4801142b71dSWill Deacon usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 4818b592783SCatalin Marinas .endif 4828b592783SCatalin Marinas 4838b592783SCatalin Marinas add\cond \ptr, #\rept * \inc 4848b592783SCatalin Marinas .endm 4858b592783SCatalin Marinas 4868b592783SCatalin Marinas #else /* !CONFIG_THUMB2_KERNEL */ 4878b592783SCatalin Marinas 4884e7682d0SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 4898b592783SCatalin Marinas .rept \rept 4908b592783SCatalin Marinas 9999: 4918b592783SCatalin Marinas .if \inc == 1 492c001899aSStefan Agner \instr\()b\t\cond \reg, [\ptr], #\inc 4938b592783SCatalin Marinas .elseif \inc == 4 494c001899aSStefan Agner \instr\t\cond \reg, [\ptr], #\inc 4958b592783SCatalin Marinas .else 4968b592783SCatalin Marinas .error "Unsupported inc macro argument" 4978b592783SCatalin Marinas .endif 4988b592783SCatalin Marinas 4994260415fSRussell King .pushsection __ex_table,"a" 5008b592783SCatalin Marinas .align 3 5018b592783SCatalin Marinas .long 9999b, \abort 5024260415fSRussell King .popsection 5038b592783SCatalin Marinas .endr 5048b592783SCatalin Marinas .endm 5058b592783SCatalin Marinas 5068b592783SCatalin Marinas #endif /* CONFIG_THUMB2_KERNEL */ 5078b592783SCatalin Marinas 5088b592783SCatalin Marinas .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 5098b592783SCatalin Marinas usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 5108b592783SCatalin Marinas .endm 5118b592783SCatalin Marinas 5128b592783SCatalin Marinas .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 5138b592783SCatalin Marinas usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 5148b592783SCatalin Marinas .endm 5158f51965eSDave Martin 5168f51965eSDave Martin /* Utility macro for declaring string literals */ 5178f51965eSDave Martin .macro string name:req, string 5188f51965eSDave Martin .type \name , #object 5198f51965eSDave Martin \name: 5208f51965eSDave Martin .asciz "\string" 5218f51965eSDave Martin .size \name , . - \name 5228f51965eSDave Martin .endm 5238f51965eSDave Martin 5246ebbf2ceSRussell King .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 5256ebbf2ceSRussell King .macro ret\c, reg 5266ebbf2ceSRussell King #if __LINUX_ARM_ARCH__ < 6 5276ebbf2ceSRussell King mov\c pc, \reg 5286ebbf2ceSRussell King #else 5296ebbf2ceSRussell King .ifeqs "\reg", "lr" 5306ebbf2ceSRussell King bx\c \reg 5316ebbf2ceSRussell King .else 5326ebbf2ceSRussell King mov\c pc, \reg 5336ebbf2ceSRussell King .endif 5346ebbf2ceSRussell King #endif 5356ebbf2ceSRussell King .endm 5366ebbf2ceSRussell King .endr 5376ebbf2ceSRussell King 5386ebbf2ceSRussell King .macro ret.w, reg 5396ebbf2ceSRussell King ret \reg 5406ebbf2ceSRussell King #ifdef CONFIG_THUMB2_KERNEL 5416ebbf2ceSRussell King nop 5426ebbf2ceSRussell King #endif 5436ebbf2ceSRussell King .endm 5446ebbf2ceSRussell King 5458bafae20SRussell King .macro bug, msg, line 5468bafae20SRussell King #ifdef CONFIG_THUMB2_KERNEL 5478bafae20SRussell King 1: .inst 0xde02 5488bafae20SRussell King #else 5498bafae20SRussell King 1: .inst 0xe7f001f2 5508bafae20SRussell King #endif 5518bafae20SRussell King #ifdef CONFIG_DEBUG_BUGVERBOSE 5528bafae20SRussell King .pushsection .rodata.str, "aMS", %progbits, 1 5538bafae20SRussell King 2: .asciz "\msg" 5548bafae20SRussell King .popsection 5558bafae20SRussell King .pushsection __bug_table, "aw" 5568bafae20SRussell King .align 2 5578bafae20SRussell King .word 1b, 2b 5588bafae20SRussell King .hword \line 5598bafae20SRussell King .popsection 5608bafae20SRussell King #endif 5618bafae20SRussell King .endm 5628bafae20SRussell King 5630d73c3f8SMasami Hiramatsu #ifdef CONFIG_KPROBES 5640d73c3f8SMasami Hiramatsu #define _ASM_NOKPROBE(entry) \ 5650d73c3f8SMasami Hiramatsu .pushsection "_kprobe_blacklist", "aw" ; \ 5660d73c3f8SMasami Hiramatsu .balign 4 ; \ 5670d73c3f8SMasami Hiramatsu .long entry; \ 5680d73c3f8SMasami Hiramatsu .popsection 5690d73c3f8SMasami Hiramatsu #else 5700d73c3f8SMasami Hiramatsu #define _ASM_NOKPROBE(entry) 5710d73c3f8SMasami Hiramatsu #endif 5720d73c3f8SMasami Hiramatsu 5730b167463SArd Biesheuvel .macro __adldst_l, op, reg, sym, tmp, c 5740b167463SArd Biesheuvel .if __LINUX_ARM_ARCH__ < 7 5750b167463SArd Biesheuvel ldr\c \tmp, .La\@ 5760b167463SArd Biesheuvel .subsection 1 5770b167463SArd Biesheuvel .align 2 5780b167463SArd Biesheuvel .La\@: .long \sym - .Lpc\@ 5790b167463SArd Biesheuvel .previous 5800b167463SArd Biesheuvel .else 5810b167463SArd Biesheuvel .ifnb \c 5820b167463SArd Biesheuvel THUMB( ittt \c ) 5830b167463SArd Biesheuvel .endif 5840b167463SArd Biesheuvel movw\c \tmp, #:lower16:\sym - .Lpc\@ 5850b167463SArd Biesheuvel movt\c \tmp, #:upper16:\sym - .Lpc\@ 5860b167463SArd Biesheuvel .endif 5870b167463SArd Biesheuvel 5880b167463SArd Biesheuvel #ifndef CONFIG_THUMB2_KERNEL 5890b167463SArd Biesheuvel .set .Lpc\@, . + 8 // PC bias 5900b167463SArd Biesheuvel .ifc \op, add 5910b167463SArd Biesheuvel add\c \reg, \tmp, pc 5920b167463SArd Biesheuvel .else 5930b167463SArd Biesheuvel \op\c \reg, [pc, \tmp] 5940b167463SArd Biesheuvel .endif 5950b167463SArd Biesheuvel #else 5960b167463SArd Biesheuvel .Lb\@: add\c \tmp, \tmp, pc 5970b167463SArd Biesheuvel /* 5980b167463SArd Biesheuvel * In Thumb-2 builds, the PC bias depends on whether we are currently 5990b167463SArd Biesheuvel * emitting into a .arm or a .thumb section. The size of the add opcode 6000b167463SArd Biesheuvel * above will be 2 bytes when emitting in Thumb mode and 4 bytes when 6010b167463SArd Biesheuvel * emitting in ARM mode, so let's use this to account for the bias. 6020b167463SArd Biesheuvel */ 6030b167463SArd Biesheuvel .set .Lpc\@, . + (. - .Lb\@) 6040b167463SArd Biesheuvel 6050b167463SArd Biesheuvel .ifnc \op, add 6060b167463SArd Biesheuvel \op\c \reg, [\tmp] 6070b167463SArd Biesheuvel .endif 6080b167463SArd Biesheuvel #endif 6090b167463SArd Biesheuvel .endm 6100b167463SArd Biesheuvel 6110b167463SArd Biesheuvel /* 6120b167463SArd Biesheuvel * mov_l - move a constant value or [relocated] address into a register 6130b167463SArd Biesheuvel */ 6144e918ab1SArd Biesheuvel .macro mov_l, dst:req, imm:req, cond 6150b167463SArd Biesheuvel .if __LINUX_ARM_ARCH__ < 7 6164e918ab1SArd Biesheuvel ldr\cond \dst, =\imm 6170b167463SArd Biesheuvel .else 6184e918ab1SArd Biesheuvel movw\cond \dst, #:lower16:\imm 6194e918ab1SArd Biesheuvel movt\cond \dst, #:upper16:\imm 6200b167463SArd Biesheuvel .endif 6210b167463SArd Biesheuvel .endm 6220b167463SArd Biesheuvel 6230b167463SArd Biesheuvel /* 6240b167463SArd Biesheuvel * adr_l - adr pseudo-op with unlimited range 6250b167463SArd Biesheuvel * 6260b167463SArd Biesheuvel * @dst: destination register 6270b167463SArd Biesheuvel * @sym: name of the symbol 6280b167463SArd Biesheuvel * @cond: conditional opcode suffix 6290b167463SArd Biesheuvel */ 6300b167463SArd Biesheuvel .macro adr_l, dst:req, sym:req, cond 6310b167463SArd Biesheuvel __adldst_l add, \dst, \sym, \dst, \cond 6320b167463SArd Biesheuvel .endm 6330b167463SArd Biesheuvel 6340b167463SArd Biesheuvel /* 6350b167463SArd Biesheuvel * ldr_l - ldr <literal> pseudo-op with unlimited range 6360b167463SArd Biesheuvel * 6370b167463SArd Biesheuvel * @dst: destination register 6380b167463SArd Biesheuvel * @sym: name of the symbol 6390b167463SArd Biesheuvel * @cond: conditional opcode suffix 6400b167463SArd Biesheuvel */ 6410b167463SArd Biesheuvel .macro ldr_l, dst:req, sym:req, cond 6420b167463SArd Biesheuvel __adldst_l ldr, \dst, \sym, \dst, \cond 6430b167463SArd Biesheuvel .endm 6440b167463SArd Biesheuvel 6450b167463SArd Biesheuvel /* 6460b167463SArd Biesheuvel * str_l - str <literal> pseudo-op with unlimited range 6470b167463SArd Biesheuvel * 6480b167463SArd Biesheuvel * @src: source register 6490b167463SArd Biesheuvel * @sym: name of the symbol 6500b167463SArd Biesheuvel * @tmp: mandatory scratch register 6510b167463SArd Biesheuvel * @cond: conditional opcode suffix 6520b167463SArd Biesheuvel */ 6530b167463SArd Biesheuvel .macro str_l, src:req, sym:req, tmp:req, cond 6540b167463SArd Biesheuvel __adldst_l str, \src, \sym, \tmp, \cond 6550b167463SArd Biesheuvel .endm 6560b167463SArd Biesheuvel 6574e918ab1SArd Biesheuvel .macro __ldst_va, op, reg, tmp, sym, cond 6584e918ab1SArd Biesheuvel #if __LINUX_ARM_ARCH__ >= 7 || \ 6594e918ab1SArd Biesheuvel (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS)) || \ 6604e918ab1SArd Biesheuvel (defined(CONFIG_LD_IS_LLD) && CONFIG_LLD_VERSION < 140000) 6614e918ab1SArd Biesheuvel mov_l \tmp, \sym, \cond 6624e918ab1SArd Biesheuvel \op\cond \reg, [\tmp] 6634e918ab1SArd Biesheuvel #else 6644e918ab1SArd Biesheuvel /* 6654e918ab1SArd Biesheuvel * Avoid a literal load, by emitting a sequence of ADD/LDR instructions 6664e918ab1SArd Biesheuvel * with the appropriate relocations. The combined sequence has a range 6674e918ab1SArd Biesheuvel * of -/+ 256 MiB, which should be sufficient for the core kernel and 6684e918ab1SArd Biesheuvel * for modules loaded into the module region. 6694e918ab1SArd Biesheuvel */ 6704e918ab1SArd Biesheuvel .globl \sym 6714e918ab1SArd Biesheuvel .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym 6724e918ab1SArd Biesheuvel .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym 6734e918ab1SArd Biesheuvel .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym 6744e918ab1SArd Biesheuvel .L0_\@: sub\cond \tmp, pc, #8 6754e918ab1SArd Biesheuvel .L1_\@: sub\cond \tmp, \tmp, #4 6764e918ab1SArd Biesheuvel .L2_\@: \op\cond \reg, [\tmp, #0] 6774e918ab1SArd Biesheuvel #endif 6784e918ab1SArd Biesheuvel .endm 6794e918ab1SArd Biesheuvel 6804e918ab1SArd Biesheuvel /* 6814e918ab1SArd Biesheuvel * ldr_va - load a 32-bit word from the virtual address of \sym 6824e918ab1SArd Biesheuvel */ 6834e918ab1SArd Biesheuvel .macro ldr_va, rd:req, sym:req, cond 6844e918ab1SArd Biesheuvel __ldst_va ldr, \rd, \rd, \sym, \cond 6854e918ab1SArd Biesheuvel .endm 6864e918ab1SArd Biesheuvel 6874e918ab1SArd Biesheuvel /* 6884e918ab1SArd Biesheuvel * str_va - store a 32-bit word to the virtual address of \sym 6894e918ab1SArd Biesheuvel */ 6904e918ab1SArd Biesheuvel .macro str_va, rn:req, sym:req, tmp:req, cond 6914e918ab1SArd Biesheuvel __ldst_va str, \rn, \tmp, \sym, \cond 6924e918ab1SArd Biesheuvel .endm 6934e918ab1SArd Biesheuvel 6946468e898SArd Biesheuvel /* 6957b9896c3SArd Biesheuvel * ldr_this_cpu_armv6 - Load a 32-bit word from the per-CPU variable 'sym', 6967b9896c3SArd Biesheuvel * without using a temp register. Supported in ARM mode 6977b9896c3SArd Biesheuvel * only. 6987b9896c3SArd Biesheuvel */ 6997b9896c3SArd Biesheuvel .macro ldr_this_cpu_armv6, rd:req, sym:req 7007b9896c3SArd Biesheuvel this_cpu_offset \rd 7017b9896c3SArd Biesheuvel .globl \sym 7027b9896c3SArd Biesheuvel .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym 7037b9896c3SArd Biesheuvel .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym 7047b9896c3SArd Biesheuvel .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym 7057b9896c3SArd Biesheuvel add \rd, \rd, pc 7067b9896c3SArd Biesheuvel .L0_\@: sub \rd, \rd, #4 7077b9896c3SArd Biesheuvel .L1_\@: sub \rd, \rd, #0 7087b9896c3SArd Biesheuvel .L2_\@: ldr \rd, [\rd, #4] 7097b9896c3SArd Biesheuvel .endm 7107b9896c3SArd Biesheuvel 7117b9896c3SArd Biesheuvel /* 7127b9896c3SArd Biesheuvel * ldr_this_cpu - Load a 32-bit word from the per-CPU variable 'sym' 7137b9896c3SArd Biesheuvel * into register 'rd', which may be the stack pointer, 7147b9896c3SArd Biesheuvel * using 't1' and 't2' as general temp registers. These 7157b9896c3SArd Biesheuvel * are permitted to overlap with 'rd' if != sp 7167b9896c3SArd Biesheuvel */ 7177b9896c3SArd Biesheuvel .macro ldr_this_cpu, rd:req, sym:req, t1:req, t2:req 7187b9896c3SArd Biesheuvel #if __LINUX_ARM_ARCH__ >= 7 || \ 7197b9896c3SArd Biesheuvel (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS)) || \ 7207b9896c3SArd Biesheuvel (defined(CONFIG_LD_IS_LLD) && CONFIG_LLD_VERSION < 140000) 7217b9896c3SArd Biesheuvel this_cpu_offset \t1 7227b9896c3SArd Biesheuvel mov_l \t2, \sym 7237b9896c3SArd Biesheuvel ldr \rd, [\t1, \t2] 7247b9896c3SArd Biesheuvel #else 7257b9896c3SArd Biesheuvel ldr_this_cpu_armv6 \rd, \sym 7267b9896c3SArd Biesheuvel #endif 7277b9896c3SArd Biesheuvel .endm 7287b9896c3SArd Biesheuvel 7297b9896c3SArd Biesheuvel /* 7306468e898SArd Biesheuvel * rev_l - byte-swap a 32-bit value 7316468e898SArd Biesheuvel * 7326468e898SArd Biesheuvel * @val: source/destination register 7336468e898SArd Biesheuvel * @tmp: scratch register 7346468e898SArd Biesheuvel */ 7356468e898SArd Biesheuvel .macro rev_l, val:req, tmp:req 7366468e898SArd Biesheuvel .if __LINUX_ARM_ARCH__ < 6 7376468e898SArd Biesheuvel eor \tmp, \val, \val, ror #16 7386468e898SArd Biesheuvel bic \tmp, \tmp, #0x00ff0000 7396468e898SArd Biesheuvel mov \val, \val, ror #8 7406468e898SArd Biesheuvel eor \val, \val, \tmp, lsr #8 7416468e898SArd Biesheuvel .else 7426468e898SArd Biesheuvel rev \val, \val 7436468e898SArd Biesheuvel .endif 7446468e898SArd Biesheuvel .endm 7456468e898SArd Biesheuvel 746b3ab60b1SArd Biesheuvel /* 747b3ab60b1SArd Biesheuvel * bl_r - branch and link to register 748b3ab60b1SArd Biesheuvel * 749b3ab60b1SArd Biesheuvel * @dst: target to branch to 750b3ab60b1SArd Biesheuvel * @c: conditional opcode suffix 751b3ab60b1SArd Biesheuvel */ 752b3ab60b1SArd Biesheuvel .macro bl_r, dst:req, c 753b3ab60b1SArd Biesheuvel .if __LINUX_ARM_ARCH__ < 6 754b3ab60b1SArd Biesheuvel mov\c lr, pc 755b3ab60b1SArd Biesheuvel mov\c pc, \dst 756b3ab60b1SArd Biesheuvel .else 757b3ab60b1SArd Biesheuvel blx\c \dst 758b3ab60b1SArd Biesheuvel .endif 759b3ab60b1SArd Biesheuvel .endm 760b3ab60b1SArd Biesheuvel 7612bc58a6fSMagnus Damm #endif /* __ASM_ASSEMBLER_H__ */ 762