14baa9922SRussell King /* 24baa9922SRussell King * arch/arm/include/asm/assembler.h 34baa9922SRussell King * 44baa9922SRussell King * Copyright (C) 1996-2000 Russell King 54baa9922SRussell King * 64baa9922SRussell King * This program is free software; you can redistribute it and/or modify 74baa9922SRussell King * it under the terms of the GNU General Public License version 2 as 84baa9922SRussell King * published by the Free Software Foundation. 94baa9922SRussell King * 104baa9922SRussell King * This file contains arm architecture specific defines 114baa9922SRussell King * for the different processors. 124baa9922SRussell King * 134baa9922SRussell King * Do not include any C declarations in this file - it is included by 144baa9922SRussell King * assembler source. 154baa9922SRussell King */ 162bc58a6fSMagnus Damm #ifndef __ASM_ASSEMBLER_H__ 172bc58a6fSMagnus Damm #define __ASM_ASSEMBLER_H__ 182bc58a6fSMagnus Damm 194baa9922SRussell King #ifndef __ASSEMBLY__ 204baa9922SRussell King #error "Only include this from assembly code" 214baa9922SRussell King #endif 224baa9922SRussell King 234baa9922SRussell King #include <asm/ptrace.h> 24247055aaSCatalin Marinas #include <asm/domain.h> 254baa9922SRussell King 264baa9922SRussell King /* 274baa9922SRussell King * Endian independent macros for shifting bytes within registers. 284baa9922SRussell King */ 294baa9922SRussell King #ifndef __ARMEB__ 304baa9922SRussell King #define pull lsr 314baa9922SRussell King #define push lsl 324baa9922SRussell King #define get_byte_0 lsl #0 334baa9922SRussell King #define get_byte_1 lsr #8 344baa9922SRussell King #define get_byte_2 lsr #16 354baa9922SRussell King #define get_byte_3 lsr #24 364baa9922SRussell King #define put_byte_0 lsl #0 374baa9922SRussell King #define put_byte_1 lsl #8 384baa9922SRussell King #define put_byte_2 lsl #16 394baa9922SRussell King #define put_byte_3 lsl #24 404baa9922SRussell King #else 414baa9922SRussell King #define pull lsl 424baa9922SRussell King #define push lsr 434baa9922SRussell King #define get_byte_0 lsr #24 444baa9922SRussell King #define get_byte_1 lsr #16 454baa9922SRussell King #define get_byte_2 lsr #8 464baa9922SRussell King #define get_byte_3 lsl #0 474baa9922SRussell King #define put_byte_0 lsl #24 484baa9922SRussell King #define put_byte_1 lsl #16 494baa9922SRussell King #define put_byte_2 lsl #8 504baa9922SRussell King #define put_byte_3 lsl #0 514baa9922SRussell King #endif 524baa9922SRussell King 534baa9922SRussell King /* 544baa9922SRussell King * Data preload for architectures that support it 554baa9922SRussell King */ 564baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 5 574baa9922SRussell King #define PLD(code...) code 584baa9922SRussell King #else 594baa9922SRussell King #define PLD(code...) 604baa9922SRussell King #endif 614baa9922SRussell King 624baa9922SRussell King /* 634baa9922SRussell King * This can be used to enable code to cacheline align the destination 644baa9922SRussell King * pointer when bulk writing to memory. Experiments on StrongARM and 654baa9922SRussell King * XScale didn't show this a worthwhile thing to do when the cache is not 664baa9922SRussell King * set to write-allocate (this would need further testing on XScale when WA 674baa9922SRussell King * is used). 684baa9922SRussell King * 694baa9922SRussell King * On Feroceon there is much to gain however, regardless of cache mode. 704baa9922SRussell King */ 714baa9922SRussell King #ifdef CONFIG_CPU_FEROCEON 724baa9922SRussell King #define CALGN(code...) code 734baa9922SRussell King #else 744baa9922SRussell King #define CALGN(code...) 754baa9922SRussell King #endif 764baa9922SRussell King 774baa9922SRussell King /* 784baa9922SRussell King * Enable and disable interrupts 794baa9922SRussell King */ 804baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 6 810d928b0bSUwe Kleine-König .macro disable_irq_notrace 824baa9922SRussell King cpsid i 834baa9922SRussell King .endm 844baa9922SRussell King 850d928b0bSUwe Kleine-König .macro enable_irq_notrace 864baa9922SRussell King cpsie i 874baa9922SRussell King .endm 884baa9922SRussell King #else 890d928b0bSUwe Kleine-König .macro disable_irq_notrace 904baa9922SRussell King msr cpsr_c, #PSR_I_BIT | SVC_MODE 914baa9922SRussell King .endm 924baa9922SRussell King 930d928b0bSUwe Kleine-König .macro enable_irq_notrace 944baa9922SRussell King msr cpsr_c, #SVC_MODE 954baa9922SRussell King .endm 964baa9922SRussell King #endif 974baa9922SRussell King 980d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_off 990d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1000d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1010d928b0bSUwe Kleine-König bl trace_hardirqs_off 1020d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1030d928b0bSUwe Kleine-König #endif 1040d928b0bSUwe Kleine-König .endm 1050d928b0bSUwe Kleine-König 1060d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_on_cond, cond 1070d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1080d928b0bSUwe Kleine-König /* 1090d928b0bSUwe Kleine-König * actually the registers should be pushed and pop'd conditionally, but 1100d928b0bSUwe Kleine-König * after bl the flags are certainly clobbered 1110d928b0bSUwe Kleine-König */ 1120d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1130d928b0bSUwe Kleine-König bl\cond trace_hardirqs_on 1140d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1150d928b0bSUwe Kleine-König #endif 1160d928b0bSUwe Kleine-König .endm 1170d928b0bSUwe Kleine-König 1180d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_on 1190d928b0bSUwe Kleine-König asm_trace_hardirqs_on_cond al 1200d928b0bSUwe Kleine-König .endm 1210d928b0bSUwe Kleine-König 1220d928b0bSUwe Kleine-König .macro disable_irq 1230d928b0bSUwe Kleine-König disable_irq_notrace 1240d928b0bSUwe Kleine-König asm_trace_hardirqs_off 1250d928b0bSUwe Kleine-König .endm 1260d928b0bSUwe Kleine-König 1270d928b0bSUwe Kleine-König .macro enable_irq 1280d928b0bSUwe Kleine-König asm_trace_hardirqs_on 1290d928b0bSUwe Kleine-König enable_irq_notrace 1300d928b0bSUwe Kleine-König .endm 1314baa9922SRussell King /* 1324baa9922SRussell King * Save the current IRQ state and disable IRQs. Note that this macro 1334baa9922SRussell King * assumes FIQs are enabled, and that the processor is in SVC mode. 1344baa9922SRussell King */ 1354baa9922SRussell King .macro save_and_disable_irqs, oldcpsr 1364baa9922SRussell King mrs \oldcpsr, cpsr 1374baa9922SRussell King disable_irq 1384baa9922SRussell King .endm 1394baa9922SRussell King 1408e43a905SRabin Vincent .macro save_and_disable_irqs_notrace, oldcpsr 1418e43a905SRabin Vincent mrs \oldcpsr, cpsr 1428e43a905SRabin Vincent disable_irq_notrace 1438e43a905SRabin Vincent .endm 1448e43a905SRabin Vincent 1454baa9922SRussell King /* 1464baa9922SRussell King * Restore interrupt state previously stored in a register. We don't 1474baa9922SRussell King * guarantee that this will preserve the flags. 1484baa9922SRussell King */ 1490d928b0bSUwe Kleine-König .macro restore_irqs_notrace, oldcpsr 1504baa9922SRussell King msr cpsr_c, \oldcpsr 1514baa9922SRussell King .endm 1524baa9922SRussell King 1530d928b0bSUwe Kleine-König .macro restore_irqs, oldcpsr 1540d928b0bSUwe Kleine-König tst \oldcpsr, #PSR_I_BIT 1550d928b0bSUwe Kleine-König asm_trace_hardirqs_on_cond eq 1560d928b0bSUwe Kleine-König restore_irqs_notrace \oldcpsr 1570d928b0bSUwe Kleine-König .endm 1580d928b0bSUwe Kleine-König 1594baa9922SRussell King #define USER(x...) \ 1604baa9922SRussell King 9999: x; \ 1614260415fSRussell King .pushsection __ex_table,"a"; \ 1624baa9922SRussell King .align 3; \ 1634baa9922SRussell King .long 9999b,9001f; \ 1644260415fSRussell King .popsection 165bac4e960SRussell King 166f00ec48fSRussell King #ifdef CONFIG_SMP 167f00ec48fSRussell King #define ALT_SMP(instr...) \ 168f00ec48fSRussell King 9998: instr 169ed3768a8SDave Martin /* 170ed3768a8SDave Martin * Note: if you get assembler errors from ALT_UP() when building with 171ed3768a8SDave Martin * CONFIG_THUMB2_KERNEL, you almost certainly need to use 172ed3768a8SDave Martin * ALT_SMP( W(instr) ... ) 173ed3768a8SDave Martin */ 174f00ec48fSRussell King #define ALT_UP(instr...) \ 175f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 176f00ec48fSRussell King .long 9998b ;\ 177ed3768a8SDave Martin 9997: instr ;\ 178ed3768a8SDave Martin .if . - 9997b != 4 ;\ 179ed3768a8SDave Martin .error "ALT_UP() content must assemble to exactly 4 bytes";\ 180ed3768a8SDave Martin .endif ;\ 181f00ec48fSRussell King .popsection 182f00ec48fSRussell King #define ALT_UP_B(label) \ 183f00ec48fSRussell King .equ up_b_offset, label - 9998b ;\ 184f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 185f00ec48fSRussell King .long 9998b ;\ 186ed3768a8SDave Martin W(b) . + up_b_offset ;\ 187f00ec48fSRussell King .popsection 188f00ec48fSRussell King #else 189f00ec48fSRussell King #define ALT_SMP(instr...) 190f00ec48fSRussell King #define ALT_UP(instr...) instr 191f00ec48fSRussell King #define ALT_UP_B(label) b label 192f00ec48fSRussell King #endif 193f00ec48fSRussell King 194bac4e960SRussell King /* 195d675d0bcSWill Deacon * Instruction barrier 196d675d0bcSWill Deacon */ 197d675d0bcSWill Deacon .macro instr_sync 198d675d0bcSWill Deacon #if __LINUX_ARM_ARCH__ >= 7 199d675d0bcSWill Deacon isb 200d675d0bcSWill Deacon #elif __LINUX_ARM_ARCH__ == 6 201d675d0bcSWill Deacon mcr p15, 0, r0, c7, c5, 4 202d675d0bcSWill Deacon #endif 203d675d0bcSWill Deacon .endm 204d675d0bcSWill Deacon 205d675d0bcSWill Deacon /* 206bac4e960SRussell King * SMP data memory barrier 207bac4e960SRussell King */ 208ed3768a8SDave Martin .macro smp_dmb mode 209bac4e960SRussell King #ifdef CONFIG_SMP 210bac4e960SRussell King #if __LINUX_ARM_ARCH__ >= 7 211ed3768a8SDave Martin .ifeqs "\mode","arm" 212f00ec48fSRussell King ALT_SMP(dmb) 213ed3768a8SDave Martin .else 214ed3768a8SDave Martin ALT_SMP(W(dmb)) 215ed3768a8SDave Martin .endif 216bac4e960SRussell King #elif __LINUX_ARM_ARCH__ == 6 217f00ec48fSRussell King ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 218f00ec48fSRussell King #else 219f00ec48fSRussell King #error Incompatible SMP platform 220bac4e960SRussell King #endif 221ed3768a8SDave Martin .ifeqs "\mode","arm" 222f00ec48fSRussell King ALT_UP(nop) 223ed3768a8SDave Martin .else 224ed3768a8SDave Martin ALT_UP(W(nop)) 225ed3768a8SDave Martin .endif 226bac4e960SRussell King #endif 227bac4e960SRussell King .endm 228b86040a5SCatalin Marinas 229b86040a5SCatalin Marinas #ifdef CONFIG_THUMB2_KERNEL 230b86040a5SCatalin Marinas .macro setmode, mode, reg 231b86040a5SCatalin Marinas mov \reg, #\mode 232b86040a5SCatalin Marinas msr cpsr_c, \reg 233b86040a5SCatalin Marinas .endm 234b86040a5SCatalin Marinas #else 235b86040a5SCatalin Marinas .macro setmode, mode, reg 236b86040a5SCatalin Marinas msr cpsr_c, #\mode 237b86040a5SCatalin Marinas .endm 238b86040a5SCatalin Marinas #endif 2398b592783SCatalin Marinas 2408b592783SCatalin Marinas /* 2418b592783SCatalin Marinas * STRT/LDRT access macros with ARM and Thumb-2 variants 2428b592783SCatalin Marinas */ 2438b592783SCatalin Marinas #ifdef CONFIG_THUMB2_KERNEL 2448b592783SCatalin Marinas 2454e7682d0SCatalin Marinas .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 2468b592783SCatalin Marinas 9999: 2478b592783SCatalin Marinas .if \inc == 1 248247055aaSCatalin Marinas \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] 2498b592783SCatalin Marinas .elseif \inc == 4 250247055aaSCatalin Marinas \instr\cond\()\t\().w \reg, [\ptr, #\off] 2518b592783SCatalin Marinas .else 2528b592783SCatalin Marinas .error "Unsupported inc macro argument" 2538b592783SCatalin Marinas .endif 2548b592783SCatalin Marinas 2554260415fSRussell King .pushsection __ex_table,"a" 2568b592783SCatalin Marinas .align 3 2578b592783SCatalin Marinas .long 9999b, \abort 2584260415fSRussell King .popsection 2598b592783SCatalin Marinas .endm 2608b592783SCatalin Marinas 2618b592783SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort 2628b592783SCatalin Marinas @ explicit IT instruction needed because of the label 2638b592783SCatalin Marinas @ introduced by the USER macro 2648b592783SCatalin Marinas .ifnc \cond,al 2658b592783SCatalin Marinas .if \rept == 1 2668b592783SCatalin Marinas itt \cond 2678b592783SCatalin Marinas .elseif \rept == 2 2688b592783SCatalin Marinas ittt \cond 2698b592783SCatalin Marinas .else 2708b592783SCatalin Marinas .error "Unsupported rept macro argument" 2718b592783SCatalin Marinas .endif 2728b592783SCatalin Marinas .endif 2738b592783SCatalin Marinas 2748b592783SCatalin Marinas @ Slightly optimised to avoid incrementing the pointer twice 2758b592783SCatalin Marinas usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 2768b592783SCatalin Marinas .if \rept == 2 2771142b71dSWill Deacon usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 2788b592783SCatalin Marinas .endif 2798b592783SCatalin Marinas 2808b592783SCatalin Marinas add\cond \ptr, #\rept * \inc 2818b592783SCatalin Marinas .endm 2828b592783SCatalin Marinas 2838b592783SCatalin Marinas #else /* !CONFIG_THUMB2_KERNEL */ 2848b592783SCatalin Marinas 2854e7682d0SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 2868b592783SCatalin Marinas .rept \rept 2878b592783SCatalin Marinas 9999: 2888b592783SCatalin Marinas .if \inc == 1 289247055aaSCatalin Marinas \instr\cond\()b\()\t \reg, [\ptr], #\inc 2908b592783SCatalin Marinas .elseif \inc == 4 291247055aaSCatalin Marinas \instr\cond\()\t \reg, [\ptr], #\inc 2928b592783SCatalin Marinas .else 2938b592783SCatalin Marinas .error "Unsupported inc macro argument" 2948b592783SCatalin Marinas .endif 2958b592783SCatalin Marinas 2964260415fSRussell King .pushsection __ex_table,"a" 2978b592783SCatalin Marinas .align 3 2988b592783SCatalin Marinas .long 9999b, \abort 2994260415fSRussell King .popsection 3008b592783SCatalin Marinas .endr 3018b592783SCatalin Marinas .endm 3028b592783SCatalin Marinas 3038b592783SCatalin Marinas #endif /* CONFIG_THUMB2_KERNEL */ 3048b592783SCatalin Marinas 3058b592783SCatalin Marinas .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 3068b592783SCatalin Marinas usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 3078b592783SCatalin Marinas .endm 3088b592783SCatalin Marinas 3098b592783SCatalin Marinas .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 3108b592783SCatalin Marinas usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 3118b592783SCatalin Marinas .endm 3128f51965eSDave Martin 3138f51965eSDave Martin /* Utility macro for declaring string literals */ 3148f51965eSDave Martin .macro string name:req, string 3158f51965eSDave Martin .type \name , #object 3168f51965eSDave Martin \name: 3178f51965eSDave Martin .asciz "\string" 3188f51965eSDave Martin .size \name , . - \name 3198f51965eSDave Martin .endm 3208f51965eSDave Martin 3212bc58a6fSMagnus Damm #endif /* __ASM_ASSEMBLER_H__ */ 322