14baa9922SRussell King /* 24baa9922SRussell King * arch/arm/include/asm/assembler.h 34baa9922SRussell King * 44baa9922SRussell King * Copyright (C) 1996-2000 Russell King 54baa9922SRussell King * 64baa9922SRussell King * This program is free software; you can redistribute it and/or modify 74baa9922SRussell King * it under the terms of the GNU General Public License version 2 as 84baa9922SRussell King * published by the Free Software Foundation. 94baa9922SRussell King * 104baa9922SRussell King * This file contains arm architecture specific defines 114baa9922SRussell King * for the different processors. 124baa9922SRussell King * 134baa9922SRussell King * Do not include any C declarations in this file - it is included by 144baa9922SRussell King * assembler source. 154baa9922SRussell King */ 162bc58a6fSMagnus Damm #ifndef __ASM_ASSEMBLER_H__ 172bc58a6fSMagnus Damm #define __ASM_ASSEMBLER_H__ 182bc58a6fSMagnus Damm 194baa9922SRussell King #ifndef __ASSEMBLY__ 204baa9922SRussell King #error "Only include this from assembly code" 214baa9922SRussell King #endif 224baa9922SRussell King 234baa9922SRussell King #include <asm/ptrace.h> 24247055aaSCatalin Marinas #include <asm/domain.h> 254baa9922SRussell King 266f6f6a70SRob Herring #define IOMEM(x) (x) 276f6f6a70SRob Herring 284baa9922SRussell King /* 294baa9922SRussell King * Endian independent macros for shifting bytes within registers. 304baa9922SRussell King */ 314baa9922SRussell King #ifndef __ARMEB__ 324baa9922SRussell King #define pull lsr 334baa9922SRussell King #define push lsl 344baa9922SRussell King #define get_byte_0 lsl #0 354baa9922SRussell King #define get_byte_1 lsr #8 364baa9922SRussell King #define get_byte_2 lsr #16 374baa9922SRussell King #define get_byte_3 lsr #24 384baa9922SRussell King #define put_byte_0 lsl #0 394baa9922SRussell King #define put_byte_1 lsl #8 404baa9922SRussell King #define put_byte_2 lsl #16 414baa9922SRussell King #define put_byte_3 lsl #24 424baa9922SRussell King #else 434baa9922SRussell King #define pull lsl 444baa9922SRussell King #define push lsr 454baa9922SRussell King #define get_byte_0 lsr #24 464baa9922SRussell King #define get_byte_1 lsr #16 474baa9922SRussell King #define get_byte_2 lsr #8 484baa9922SRussell King #define get_byte_3 lsl #0 494baa9922SRussell King #define put_byte_0 lsl #24 504baa9922SRussell King #define put_byte_1 lsl #16 514baa9922SRussell King #define put_byte_2 lsl #8 524baa9922SRussell King #define put_byte_3 lsl #0 534baa9922SRussell King #endif 544baa9922SRussell King 554baa9922SRussell King /* 564baa9922SRussell King * Data preload for architectures that support it 574baa9922SRussell King */ 584baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 5 594baa9922SRussell King #define PLD(code...) code 604baa9922SRussell King #else 614baa9922SRussell King #define PLD(code...) 624baa9922SRussell King #endif 634baa9922SRussell King 644baa9922SRussell King /* 654baa9922SRussell King * This can be used to enable code to cacheline align the destination 664baa9922SRussell King * pointer when bulk writing to memory. Experiments on StrongARM and 674baa9922SRussell King * XScale didn't show this a worthwhile thing to do when the cache is not 684baa9922SRussell King * set to write-allocate (this would need further testing on XScale when WA 694baa9922SRussell King * is used). 704baa9922SRussell King * 714baa9922SRussell King * On Feroceon there is much to gain however, regardless of cache mode. 724baa9922SRussell King */ 734baa9922SRussell King #ifdef CONFIG_CPU_FEROCEON 744baa9922SRussell King #define CALGN(code...) code 754baa9922SRussell King #else 764baa9922SRussell King #define CALGN(code...) 774baa9922SRussell King #endif 784baa9922SRussell King 794baa9922SRussell King /* 804baa9922SRussell King * Enable and disable interrupts 814baa9922SRussell King */ 824baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 6 830d928b0bSUwe Kleine-König .macro disable_irq_notrace 844baa9922SRussell King cpsid i 854baa9922SRussell King .endm 864baa9922SRussell King 870d928b0bSUwe Kleine-König .macro enable_irq_notrace 884baa9922SRussell King cpsie i 894baa9922SRussell King .endm 904baa9922SRussell King #else 910d928b0bSUwe Kleine-König .macro disable_irq_notrace 924baa9922SRussell King msr cpsr_c, #PSR_I_BIT | SVC_MODE 934baa9922SRussell King .endm 944baa9922SRussell King 950d928b0bSUwe Kleine-König .macro enable_irq_notrace 964baa9922SRussell King msr cpsr_c, #SVC_MODE 974baa9922SRussell King .endm 984baa9922SRussell King #endif 994baa9922SRussell King 1000d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_off 1010d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1020d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1030d928b0bSUwe Kleine-König bl trace_hardirqs_off 1040d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1050d928b0bSUwe Kleine-König #endif 1060d928b0bSUwe Kleine-König .endm 1070d928b0bSUwe Kleine-König 1080d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_on_cond, cond 1090d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1100d928b0bSUwe Kleine-König /* 1110d928b0bSUwe Kleine-König * actually the registers should be pushed and pop'd conditionally, but 1120d928b0bSUwe Kleine-König * after bl the flags are certainly clobbered 1130d928b0bSUwe Kleine-König */ 1140d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1150d928b0bSUwe Kleine-König bl\cond trace_hardirqs_on 1160d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1170d928b0bSUwe Kleine-König #endif 1180d928b0bSUwe Kleine-König .endm 1190d928b0bSUwe Kleine-König 1200d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_on 1210d928b0bSUwe Kleine-König asm_trace_hardirqs_on_cond al 1220d928b0bSUwe Kleine-König .endm 1230d928b0bSUwe Kleine-König 1240d928b0bSUwe Kleine-König .macro disable_irq 1250d928b0bSUwe Kleine-König disable_irq_notrace 1260d928b0bSUwe Kleine-König asm_trace_hardirqs_off 1270d928b0bSUwe Kleine-König .endm 1280d928b0bSUwe Kleine-König 1290d928b0bSUwe Kleine-König .macro enable_irq 1300d928b0bSUwe Kleine-König asm_trace_hardirqs_on 1310d928b0bSUwe Kleine-König enable_irq_notrace 1320d928b0bSUwe Kleine-König .endm 1334baa9922SRussell King /* 1344baa9922SRussell King * Save the current IRQ state and disable IRQs. Note that this macro 1354baa9922SRussell King * assumes FIQs are enabled, and that the processor is in SVC mode. 1364baa9922SRussell King */ 1374baa9922SRussell King .macro save_and_disable_irqs, oldcpsr 1384baa9922SRussell King mrs \oldcpsr, cpsr 1394baa9922SRussell King disable_irq 1404baa9922SRussell King .endm 1414baa9922SRussell King 1428e43a905SRabin Vincent .macro save_and_disable_irqs_notrace, oldcpsr 1438e43a905SRabin Vincent mrs \oldcpsr, cpsr 1448e43a905SRabin Vincent disable_irq_notrace 1458e43a905SRabin Vincent .endm 1468e43a905SRabin Vincent 1474baa9922SRussell King /* 1484baa9922SRussell King * Restore interrupt state previously stored in a register. We don't 1494baa9922SRussell King * guarantee that this will preserve the flags. 1504baa9922SRussell King */ 1510d928b0bSUwe Kleine-König .macro restore_irqs_notrace, oldcpsr 1524baa9922SRussell King msr cpsr_c, \oldcpsr 1534baa9922SRussell King .endm 1544baa9922SRussell King 1550d928b0bSUwe Kleine-König .macro restore_irqs, oldcpsr 1560d928b0bSUwe Kleine-König tst \oldcpsr, #PSR_I_BIT 1570d928b0bSUwe Kleine-König asm_trace_hardirqs_on_cond eq 1580d928b0bSUwe Kleine-König restore_irqs_notrace \oldcpsr 1590d928b0bSUwe Kleine-König .endm 1600d928b0bSUwe Kleine-König 1614baa9922SRussell King #define USER(x...) \ 1624baa9922SRussell King 9999: x; \ 1634260415fSRussell King .pushsection __ex_table,"a"; \ 1644baa9922SRussell King .align 3; \ 1654baa9922SRussell King .long 9999b,9001f; \ 1664260415fSRussell King .popsection 167bac4e960SRussell King 168f00ec48fSRussell King #ifdef CONFIG_SMP 169f00ec48fSRussell King #define ALT_SMP(instr...) \ 170f00ec48fSRussell King 9998: instr 171ed3768a8SDave Martin /* 172ed3768a8SDave Martin * Note: if you get assembler errors from ALT_UP() when building with 173ed3768a8SDave Martin * CONFIG_THUMB2_KERNEL, you almost certainly need to use 174ed3768a8SDave Martin * ALT_SMP( W(instr) ... ) 175ed3768a8SDave Martin */ 176f00ec48fSRussell King #define ALT_UP(instr...) \ 177f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 178f00ec48fSRussell King .long 9998b ;\ 179ed3768a8SDave Martin 9997: instr ;\ 180ed3768a8SDave Martin .if . - 9997b != 4 ;\ 181ed3768a8SDave Martin .error "ALT_UP() content must assemble to exactly 4 bytes";\ 182ed3768a8SDave Martin .endif ;\ 183f00ec48fSRussell King .popsection 184f00ec48fSRussell King #define ALT_UP_B(label) \ 185f00ec48fSRussell King .equ up_b_offset, label - 9998b ;\ 186f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 187f00ec48fSRussell King .long 9998b ;\ 188ed3768a8SDave Martin W(b) . + up_b_offset ;\ 189f00ec48fSRussell King .popsection 190f00ec48fSRussell King #else 191f00ec48fSRussell King #define ALT_SMP(instr...) 192f00ec48fSRussell King #define ALT_UP(instr...) instr 193f00ec48fSRussell King #define ALT_UP_B(label) b label 194f00ec48fSRussell King #endif 195f00ec48fSRussell King 196bac4e960SRussell King /* 197d675d0bcSWill Deacon * Instruction barrier 198d675d0bcSWill Deacon */ 199d675d0bcSWill Deacon .macro instr_sync 200d675d0bcSWill Deacon #if __LINUX_ARM_ARCH__ >= 7 201d675d0bcSWill Deacon isb 202d675d0bcSWill Deacon #elif __LINUX_ARM_ARCH__ == 6 203d675d0bcSWill Deacon mcr p15, 0, r0, c7, c5, 4 204d675d0bcSWill Deacon #endif 205d675d0bcSWill Deacon .endm 206d675d0bcSWill Deacon 207d675d0bcSWill Deacon /* 208bac4e960SRussell King * SMP data memory barrier 209bac4e960SRussell King */ 210ed3768a8SDave Martin .macro smp_dmb mode 211bac4e960SRussell King #ifdef CONFIG_SMP 212bac4e960SRussell King #if __LINUX_ARM_ARCH__ >= 7 213ed3768a8SDave Martin .ifeqs "\mode","arm" 214f00ec48fSRussell King ALT_SMP(dmb) 215ed3768a8SDave Martin .else 216ed3768a8SDave Martin ALT_SMP(W(dmb)) 217ed3768a8SDave Martin .endif 218bac4e960SRussell King #elif __LINUX_ARM_ARCH__ == 6 219f00ec48fSRussell King ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 220f00ec48fSRussell King #else 221f00ec48fSRussell King #error Incompatible SMP platform 222bac4e960SRussell King #endif 223ed3768a8SDave Martin .ifeqs "\mode","arm" 224f00ec48fSRussell King ALT_UP(nop) 225ed3768a8SDave Martin .else 226ed3768a8SDave Martin ALT_UP(W(nop)) 227ed3768a8SDave Martin .endif 228bac4e960SRussell King #endif 229bac4e960SRussell King .endm 230b86040a5SCatalin Marinas 231b86040a5SCatalin Marinas #ifdef CONFIG_THUMB2_KERNEL 232b86040a5SCatalin Marinas .macro setmode, mode, reg 233b86040a5SCatalin Marinas mov \reg, #\mode 234b86040a5SCatalin Marinas msr cpsr_c, \reg 235b86040a5SCatalin Marinas .endm 236b86040a5SCatalin Marinas #else 237b86040a5SCatalin Marinas .macro setmode, mode, reg 238b86040a5SCatalin Marinas msr cpsr_c, #\mode 239b86040a5SCatalin Marinas .endm 240b86040a5SCatalin Marinas #endif 2418b592783SCatalin Marinas 2428b592783SCatalin Marinas /* 2438b592783SCatalin Marinas * STRT/LDRT access macros with ARM and Thumb-2 variants 2448b592783SCatalin Marinas */ 2458b592783SCatalin Marinas #ifdef CONFIG_THUMB2_KERNEL 2468b592783SCatalin Marinas 2474e7682d0SCatalin Marinas .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 2488b592783SCatalin Marinas 9999: 2498b592783SCatalin Marinas .if \inc == 1 250247055aaSCatalin Marinas \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] 2518b592783SCatalin Marinas .elseif \inc == 4 252247055aaSCatalin Marinas \instr\cond\()\t\().w \reg, [\ptr, #\off] 2538b592783SCatalin Marinas .else 2548b592783SCatalin Marinas .error "Unsupported inc macro argument" 2558b592783SCatalin Marinas .endif 2568b592783SCatalin Marinas 2574260415fSRussell King .pushsection __ex_table,"a" 2588b592783SCatalin Marinas .align 3 2598b592783SCatalin Marinas .long 9999b, \abort 2604260415fSRussell King .popsection 2618b592783SCatalin Marinas .endm 2628b592783SCatalin Marinas 2638b592783SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort 2648b592783SCatalin Marinas @ explicit IT instruction needed because of the label 2658b592783SCatalin Marinas @ introduced by the USER macro 2668b592783SCatalin Marinas .ifnc \cond,al 2678b592783SCatalin Marinas .if \rept == 1 2688b592783SCatalin Marinas itt \cond 2698b592783SCatalin Marinas .elseif \rept == 2 2708b592783SCatalin Marinas ittt \cond 2718b592783SCatalin Marinas .else 2728b592783SCatalin Marinas .error "Unsupported rept macro argument" 2738b592783SCatalin Marinas .endif 2748b592783SCatalin Marinas .endif 2758b592783SCatalin Marinas 2768b592783SCatalin Marinas @ Slightly optimised to avoid incrementing the pointer twice 2778b592783SCatalin Marinas usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 2788b592783SCatalin Marinas .if \rept == 2 2791142b71dSWill Deacon usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 2808b592783SCatalin Marinas .endif 2818b592783SCatalin Marinas 2828b592783SCatalin Marinas add\cond \ptr, #\rept * \inc 2838b592783SCatalin Marinas .endm 2848b592783SCatalin Marinas 2858b592783SCatalin Marinas #else /* !CONFIG_THUMB2_KERNEL */ 2868b592783SCatalin Marinas 2874e7682d0SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 2888b592783SCatalin Marinas .rept \rept 2898b592783SCatalin Marinas 9999: 2908b592783SCatalin Marinas .if \inc == 1 291247055aaSCatalin Marinas \instr\cond\()b\()\t \reg, [\ptr], #\inc 2928b592783SCatalin Marinas .elseif \inc == 4 293247055aaSCatalin Marinas \instr\cond\()\t \reg, [\ptr], #\inc 2948b592783SCatalin Marinas .else 2958b592783SCatalin Marinas .error "Unsupported inc macro argument" 2968b592783SCatalin Marinas .endif 2978b592783SCatalin Marinas 2984260415fSRussell King .pushsection __ex_table,"a" 2998b592783SCatalin Marinas .align 3 3008b592783SCatalin Marinas .long 9999b, \abort 3014260415fSRussell King .popsection 3028b592783SCatalin Marinas .endr 3038b592783SCatalin Marinas .endm 3048b592783SCatalin Marinas 3058b592783SCatalin Marinas #endif /* CONFIG_THUMB2_KERNEL */ 3068b592783SCatalin Marinas 3078b592783SCatalin Marinas .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 3088b592783SCatalin Marinas usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 3098b592783SCatalin Marinas .endm 3108b592783SCatalin Marinas 3118b592783SCatalin Marinas .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 3128b592783SCatalin Marinas usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 3138b592783SCatalin Marinas .endm 3148f51965eSDave Martin 3158f51965eSDave Martin /* Utility macro for declaring string literals */ 3168f51965eSDave Martin .macro string name:req, string 3178f51965eSDave Martin .type \name , #object 3188f51965eSDave Martin \name: 3198f51965eSDave Martin .asciz "\string" 3208f51965eSDave Martin .size \name , . - \name 3218f51965eSDave Martin .endm 3228f51965eSDave Martin 3238404663fSRussell King .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req 3248404663fSRussell King #ifndef CONFIG_CPU_USE_DOMAINS 3258404663fSRussell King adds \tmp, \addr, #\size - 1 3268404663fSRussell King sbcccs \tmp, \tmp, \limit 3278404663fSRussell King bcs \bad 3288404663fSRussell King #endif 3298404663fSRussell King .endm 3308404663fSRussell King 3312bc58a6fSMagnus Damm #endif /* __ASM_ASSEMBLER_H__ */ 332