1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24baa9922SRussell King /* 34baa9922SRussell King * arch/arm/include/asm/assembler.h 44baa9922SRussell King * 54baa9922SRussell King * Copyright (C) 1996-2000 Russell King 64baa9922SRussell King * 74baa9922SRussell King * This file contains arm architecture specific defines 84baa9922SRussell King * for the different processors. 94baa9922SRussell King * 104baa9922SRussell King * Do not include any C declarations in this file - it is included by 114baa9922SRussell King * assembler source. 124baa9922SRussell King */ 132bc58a6fSMagnus Damm #ifndef __ASM_ASSEMBLER_H__ 142bc58a6fSMagnus Damm #define __ASM_ASSEMBLER_H__ 152bc58a6fSMagnus Damm 164baa9922SRussell King #ifndef __ASSEMBLY__ 174baa9922SRussell King #error "Only include this from assembly code" 184baa9922SRussell King #endif 194baa9922SRussell King 204baa9922SRussell King #include <asm/ptrace.h> 2180c59dafSDave Martin #include <asm/opcodes-virt.h> 220b1f68e8SCatalin Marinas #include <asm/asm-offsets.h> 239a2b51b6SAndrey Ryabinin #include <asm/page.h> 249a2b51b6SAndrey Ryabinin #include <asm/thread_info.h> 25747ffc2fSRussell King #include <asm/uaccess-asm.h> 264baa9922SRussell King 276f6f6a70SRob Herring #define IOMEM(x) (x) 286f6f6a70SRob Herring 294baa9922SRussell King /* 304baa9922SRussell King * Endian independent macros for shifting bytes within registers. 314baa9922SRussell King */ 324baa9922SRussell King #ifndef __ARMEB__ 33d98b90eaSVictor Kamensky #define lspull lsr 34d98b90eaSVictor Kamensky #define lspush lsl 354baa9922SRussell King #define get_byte_0 lsl #0 364baa9922SRussell King #define get_byte_1 lsr #8 374baa9922SRussell King #define get_byte_2 lsr #16 384baa9922SRussell King #define get_byte_3 lsr #24 394baa9922SRussell King #define put_byte_0 lsl #0 404baa9922SRussell King #define put_byte_1 lsl #8 414baa9922SRussell King #define put_byte_2 lsl #16 424baa9922SRussell King #define put_byte_3 lsl #24 434baa9922SRussell King #else 44d98b90eaSVictor Kamensky #define lspull lsl 45d98b90eaSVictor Kamensky #define lspush lsr 464baa9922SRussell King #define get_byte_0 lsr #24 474baa9922SRussell King #define get_byte_1 lsr #16 484baa9922SRussell King #define get_byte_2 lsr #8 494baa9922SRussell King #define get_byte_3 lsl #0 504baa9922SRussell King #define put_byte_0 lsl #24 514baa9922SRussell King #define put_byte_1 lsl #16 524baa9922SRussell King #define put_byte_2 lsl #8 534baa9922SRussell King #define put_byte_3 lsl #0 544baa9922SRussell King #endif 554baa9922SRussell King 56457c2403SBen Dooks /* Select code for any configuration running in BE8 mode */ 57457c2403SBen Dooks #ifdef CONFIG_CPU_ENDIAN_BE8 58457c2403SBen Dooks #define ARM_BE8(code...) code 59457c2403SBen Dooks #else 60457c2403SBen Dooks #define ARM_BE8(code...) 61457c2403SBen Dooks #endif 62457c2403SBen Dooks 634baa9922SRussell King /* 644baa9922SRussell King * Data preload for architectures that support it 654baa9922SRussell King */ 664baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 5 674baa9922SRussell King #define PLD(code...) code 684baa9922SRussell King #else 694baa9922SRussell King #define PLD(code...) 704baa9922SRussell King #endif 714baa9922SRussell King 724baa9922SRussell King /* 734baa9922SRussell King * This can be used to enable code to cacheline align the destination 744baa9922SRussell King * pointer when bulk writing to memory. Experiments on StrongARM and 754baa9922SRussell King * XScale didn't show this a worthwhile thing to do when the cache is not 764baa9922SRussell King * set to write-allocate (this would need further testing on XScale when WA 774baa9922SRussell King * is used). 784baa9922SRussell King * 794baa9922SRussell King * On Feroceon there is much to gain however, regardless of cache mode. 804baa9922SRussell King */ 814baa9922SRussell King #ifdef CONFIG_CPU_FEROCEON 824baa9922SRussell King #define CALGN(code...) code 834baa9922SRussell King #else 844baa9922SRussell King #define CALGN(code...) 854baa9922SRussell King #endif 864baa9922SRussell King 87ffa47aa6SArnd Bergmann #define IMM12_MASK 0xfff 88ffa47aa6SArnd Bergmann 89d4664b6cSArd Biesheuvel /* the frame pointer used for stack unwinding */ 90d4664b6cSArd Biesheuvel ARM( fpreg .req r11 ) 91d4664b6cSArd Biesheuvel THUMB( fpreg .req r7 ) 92d4664b6cSArd Biesheuvel 934baa9922SRussell King /* 944baa9922SRussell King * Enable and disable interrupts 954baa9922SRussell King */ 964baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 6 970d928b0bSUwe Kleine-König .macro disable_irq_notrace 984baa9922SRussell King cpsid i 994baa9922SRussell King .endm 1004baa9922SRussell King 1010d928b0bSUwe Kleine-König .macro enable_irq_notrace 1024baa9922SRussell King cpsie i 1034baa9922SRussell King .endm 1044baa9922SRussell King #else 1050d928b0bSUwe Kleine-König .macro disable_irq_notrace 1064baa9922SRussell King msr cpsr_c, #PSR_I_BIT | SVC_MODE 1074baa9922SRussell King .endm 1084baa9922SRussell King 1090d928b0bSUwe Kleine-König .macro enable_irq_notrace 1104baa9922SRussell King msr cpsr_c, #SVC_MODE 1114baa9922SRussell King .endm 1124baa9922SRussell King #endif 1134baa9922SRussell King 1143302caddSRussell King .macro asm_trace_hardirqs_off, save=1 1150d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1163302caddSRussell King .if \save 1170d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1183302caddSRussell King .endif 1190d928b0bSUwe Kleine-König bl trace_hardirqs_off 1203302caddSRussell King .if \save 1210d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1223302caddSRussell King .endif 1230d928b0bSUwe Kleine-König #endif 1240d928b0bSUwe Kleine-König .endm 1250d928b0bSUwe Kleine-König 1263302caddSRussell King .macro asm_trace_hardirqs_on, cond=al, save=1 1270d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1280d928b0bSUwe Kleine-König /* 1290d928b0bSUwe Kleine-König * actually the registers should be pushed and pop'd conditionally, but 1300d928b0bSUwe Kleine-König * after bl the flags are certainly clobbered 1310d928b0bSUwe Kleine-König */ 1323302caddSRussell King .if \save 1330d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1343302caddSRussell King .endif 1350d928b0bSUwe Kleine-König bl\cond trace_hardirqs_on 1363302caddSRussell King .if \save 1370d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1383302caddSRussell King .endif 1390d928b0bSUwe Kleine-König #endif 1400d928b0bSUwe Kleine-König .endm 1410d928b0bSUwe Kleine-König 1423302caddSRussell King .macro disable_irq, save=1 1430d928b0bSUwe Kleine-König disable_irq_notrace 1443302caddSRussell King asm_trace_hardirqs_off \save 1450d928b0bSUwe Kleine-König .endm 1460d928b0bSUwe Kleine-König 1470d928b0bSUwe Kleine-König .macro enable_irq 1480d928b0bSUwe Kleine-König asm_trace_hardirqs_on 1490d928b0bSUwe Kleine-König enable_irq_notrace 1500d928b0bSUwe Kleine-König .endm 1514baa9922SRussell King /* 1524baa9922SRussell King * Save the current IRQ state and disable IRQs. Note that this macro 1534baa9922SRussell King * assumes FIQs are enabled, and that the processor is in SVC mode. 1544baa9922SRussell King */ 1554baa9922SRussell King .macro save_and_disable_irqs, oldcpsr 15655bdd694SCatalin Marinas #ifdef CONFIG_CPU_V7M 15755bdd694SCatalin Marinas mrs \oldcpsr, primask 15855bdd694SCatalin Marinas #else 1594baa9922SRussell King mrs \oldcpsr, cpsr 16055bdd694SCatalin Marinas #endif 1614baa9922SRussell King disable_irq 1624baa9922SRussell King .endm 1634baa9922SRussell King 1648e43a905SRabin Vincent .macro save_and_disable_irqs_notrace, oldcpsr 165b2bf482aSVladimir Murzin #ifdef CONFIG_CPU_V7M 166b2bf482aSVladimir Murzin mrs \oldcpsr, primask 167b2bf482aSVladimir Murzin #else 1688e43a905SRabin Vincent mrs \oldcpsr, cpsr 169b2bf482aSVladimir Murzin #endif 1708e43a905SRabin Vincent disable_irq_notrace 1718e43a905SRabin Vincent .endm 1728e43a905SRabin Vincent 1734baa9922SRussell King /* 1744baa9922SRussell King * Restore interrupt state previously stored in a register. We don't 1754baa9922SRussell King * guarantee that this will preserve the flags. 1764baa9922SRussell King */ 1770d928b0bSUwe Kleine-König .macro restore_irqs_notrace, oldcpsr 17855bdd694SCatalin Marinas #ifdef CONFIG_CPU_V7M 17955bdd694SCatalin Marinas msr primask, \oldcpsr 18055bdd694SCatalin Marinas #else 1814baa9922SRussell King msr cpsr_c, \oldcpsr 18255bdd694SCatalin Marinas #endif 1834baa9922SRussell King .endm 1844baa9922SRussell King 1850d928b0bSUwe Kleine-König .macro restore_irqs, oldcpsr 1860d928b0bSUwe Kleine-König tst \oldcpsr, #PSR_I_BIT 18701e09a28SRussell King asm_trace_hardirqs_on cond=eq 1880d928b0bSUwe Kleine-König restore_irqs_notrace \oldcpsr 1890d928b0bSUwe Kleine-König .endm 1900d928b0bSUwe Kleine-König 19139ad04ccSCatalin Marinas /* 19214327c66SRussell King * Assembly version of "adr rd, BSYM(sym)". This should only be used to 19314327c66SRussell King * reference local symbols in the same assembly file which are to be 19414327c66SRussell King * resolved by the assembler. Other usage is undefined. 19514327c66SRussell King */ 19614327c66SRussell King .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 19714327c66SRussell King .macro badr\c, rd, sym 19814327c66SRussell King #ifdef CONFIG_THUMB2_KERNEL 19914327c66SRussell King adr\c \rd, \sym + 1 20014327c66SRussell King #else 20114327c66SRussell King adr\c \rd, \sym 20214327c66SRussell King #endif 20314327c66SRussell King .endm 20414327c66SRussell King .endr 20514327c66SRussell King 20650596b75SArd Biesheuvel .macro get_current, rd 20750596b75SArd Biesheuvel #ifdef CONFIG_CURRENT_POINTER_IN_TPIDRURO 20850596b75SArd Biesheuvel mrc p15, 0, \rd, c13, c0, 3 @ get TPIDRURO register 20950596b75SArd Biesheuvel #else 21050596b75SArd Biesheuvel get_thread_info \rd 21150596b75SArd Biesheuvel ldr \rd, [\rd, #TI_TASK] 21250596b75SArd Biesheuvel #endif 21350596b75SArd Biesheuvel .endm 21450596b75SArd Biesheuvel 21550596b75SArd Biesheuvel .macro set_current, rn 21650596b75SArd Biesheuvel #ifdef CONFIG_CURRENT_POINTER_IN_TPIDRURO 21750596b75SArd Biesheuvel mcr p15, 0, \rn, c13, c0, 3 @ set TPIDRURO register 21850596b75SArd Biesheuvel #endif 21950596b75SArd Biesheuvel .endm 22050596b75SArd Biesheuvel 22150596b75SArd Biesheuvel .macro reload_current, t1:req, t2:req 22250596b75SArd Biesheuvel #ifdef CONFIG_CURRENT_POINTER_IN_TPIDRURO 22350596b75SArd Biesheuvel adr_l \t1, __entry_task @ get __entry_task base address 22450596b75SArd Biesheuvel mrc p15, 0, \t2, c13, c0, 4 @ get per-CPU offset 22550596b75SArd Biesheuvel ldr \t1, [\t1, \t2] @ load variable 22650596b75SArd Biesheuvel mcr p15, 0, \t1, c13, c0, 3 @ store in TPIDRURO 22750596b75SArd Biesheuvel #endif 22850596b75SArd Biesheuvel .endm 22950596b75SArd Biesheuvel 23014327c66SRussell King /* 23139ad04ccSCatalin Marinas * Get current thread_info. 23239ad04ccSCatalin Marinas */ 23339ad04ccSCatalin Marinas .macro get_thread_info, rd 23418ed1c01SArd Biesheuvel #ifdef CONFIG_THREAD_INFO_IN_TASK 23518ed1c01SArd Biesheuvel /* thread_info is the first member of struct task_struct */ 23618ed1c01SArd Biesheuvel get_current \rd 23718ed1c01SArd Biesheuvel #else 2389a2b51b6SAndrey Ryabinin ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT ) 23939ad04ccSCatalin Marinas THUMB( mov \rd, sp ) 2409a2b51b6SAndrey Ryabinin THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT ) 2419a2b51b6SAndrey Ryabinin mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT 24218ed1c01SArd Biesheuvel #endif 24339ad04ccSCatalin Marinas .endm 24439ad04ccSCatalin Marinas 2450b1f68e8SCatalin Marinas /* 2460b1f68e8SCatalin Marinas * Increment/decrement the preempt count. 2470b1f68e8SCatalin Marinas */ 2480b1f68e8SCatalin Marinas #ifdef CONFIG_PREEMPT_COUNT 2490b1f68e8SCatalin Marinas .macro inc_preempt_count, ti, tmp 2500b1f68e8SCatalin Marinas ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 2510b1f68e8SCatalin Marinas add \tmp, \tmp, #1 @ increment it 2520b1f68e8SCatalin Marinas str \tmp, [\ti, #TI_PREEMPT] 2530b1f68e8SCatalin Marinas .endm 2540b1f68e8SCatalin Marinas 2550b1f68e8SCatalin Marinas .macro dec_preempt_count, ti, tmp 2560b1f68e8SCatalin Marinas ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 2570b1f68e8SCatalin Marinas sub \tmp, \tmp, #1 @ decrement it 2580b1f68e8SCatalin Marinas str \tmp, [\ti, #TI_PREEMPT] 2590b1f68e8SCatalin Marinas .endm 2600b1f68e8SCatalin Marinas 2610b1f68e8SCatalin Marinas .macro dec_preempt_count_ti, ti, tmp 2620b1f68e8SCatalin Marinas get_thread_info \ti 2630b1f68e8SCatalin Marinas dec_preempt_count \ti, \tmp 2640b1f68e8SCatalin Marinas .endm 2650b1f68e8SCatalin Marinas #else 2660b1f68e8SCatalin Marinas .macro inc_preempt_count, ti, tmp 2670b1f68e8SCatalin Marinas .endm 2680b1f68e8SCatalin Marinas 2690b1f68e8SCatalin Marinas .macro dec_preempt_count, ti, tmp 2700b1f68e8SCatalin Marinas .endm 2710b1f68e8SCatalin Marinas 2720b1f68e8SCatalin Marinas .macro dec_preempt_count_ti, ti, tmp 2730b1f68e8SCatalin Marinas .endm 2740b1f68e8SCatalin Marinas #endif 2750b1f68e8SCatalin Marinas 276f441882aSVincent Whitchurch #define USERL(l, x...) \ 2774baa9922SRussell King 9999: x; \ 2784260415fSRussell King .pushsection __ex_table,"a"; \ 2794baa9922SRussell King .align 3; \ 280f441882aSVincent Whitchurch .long 9999b,l; \ 2814260415fSRussell King .popsection 282bac4e960SRussell King 283f441882aSVincent Whitchurch #define USER(x...) USERL(9001f, x) 284f441882aSVincent Whitchurch 285f00ec48fSRussell King #ifdef CONFIG_SMP 286f00ec48fSRussell King #define ALT_SMP(instr...) \ 287f00ec48fSRussell King 9998: instr 288ed3768a8SDave Martin /* 289ed3768a8SDave Martin * Note: if you get assembler errors from ALT_UP() when building with 290ed3768a8SDave Martin * CONFIG_THUMB2_KERNEL, you almost certainly need to use 291ed3768a8SDave Martin * ALT_SMP( W(instr) ... ) 292ed3768a8SDave Martin */ 293f00ec48fSRussell King #define ALT_UP(instr...) \ 294f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 295450abd38SArd Biesheuvel .long 9998b - . ;\ 296ed3768a8SDave Martin 9997: instr ;\ 29789c6bc58SRussell King .if . - 9997b == 2 ;\ 29889c6bc58SRussell King nop ;\ 29989c6bc58SRussell King .endif ;\ 300ed3768a8SDave Martin .if . - 9997b != 4 ;\ 301ed3768a8SDave Martin .error "ALT_UP() content must assemble to exactly 4 bytes";\ 302ed3768a8SDave Martin .endif ;\ 303f00ec48fSRussell King .popsection 304f00ec48fSRussell King #define ALT_UP_B(label) \ 305f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 306450abd38SArd Biesheuvel .long 9998b - . ;\ 307a780e485SJian Cai W(b) . + (label - 9998b) ;\ 308f00ec48fSRussell King .popsection 309f00ec48fSRussell King #else 310f00ec48fSRussell King #define ALT_SMP(instr...) 311f00ec48fSRussell King #define ALT_UP(instr...) instr 312f00ec48fSRussell King #define ALT_UP_B(label) b label 313f00ec48fSRussell King #endif 314f00ec48fSRussell King 315bac4e960SRussell King /* 316d675d0bcSWill Deacon * Instruction barrier 317d675d0bcSWill Deacon */ 318d675d0bcSWill Deacon .macro instr_sync 319d675d0bcSWill Deacon #if __LINUX_ARM_ARCH__ >= 7 320d675d0bcSWill Deacon isb 321d675d0bcSWill Deacon #elif __LINUX_ARM_ARCH__ == 6 322d675d0bcSWill Deacon mcr p15, 0, r0, c7, c5, 4 323d675d0bcSWill Deacon #endif 324d675d0bcSWill Deacon .endm 325d675d0bcSWill Deacon 326d675d0bcSWill Deacon /* 327bac4e960SRussell King * SMP data memory barrier 328bac4e960SRussell King */ 329ed3768a8SDave Martin .macro smp_dmb mode 330bac4e960SRussell King #ifdef CONFIG_SMP 331bac4e960SRussell King #if __LINUX_ARM_ARCH__ >= 7 332ed3768a8SDave Martin .ifeqs "\mode","arm" 3333ea12806SWill Deacon ALT_SMP(dmb ish) 334ed3768a8SDave Martin .else 3353ea12806SWill Deacon ALT_SMP(W(dmb) ish) 336ed3768a8SDave Martin .endif 337bac4e960SRussell King #elif __LINUX_ARM_ARCH__ == 6 338f00ec48fSRussell King ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 339f00ec48fSRussell King #else 340f00ec48fSRussell King #error Incompatible SMP platform 341bac4e960SRussell King #endif 342ed3768a8SDave Martin .ifeqs "\mode","arm" 343f00ec48fSRussell King ALT_UP(nop) 344ed3768a8SDave Martin .else 345ed3768a8SDave Martin ALT_UP(W(nop)) 346ed3768a8SDave Martin .endif 347bac4e960SRussell King #endif 348bac4e960SRussell King .endm 349b86040a5SCatalin Marinas 35055bdd694SCatalin Marinas #if defined(CONFIG_CPU_V7M) 35155bdd694SCatalin Marinas /* 35255bdd694SCatalin Marinas * setmode is used to assert to be in svc mode during boot. For v7-M 35355bdd694SCatalin Marinas * this is done in __v7m_setup, so setmode can be empty here. 35455bdd694SCatalin Marinas */ 35555bdd694SCatalin Marinas .macro setmode, mode, reg 35655bdd694SCatalin Marinas .endm 35755bdd694SCatalin Marinas #elif defined(CONFIG_THUMB2_KERNEL) 358b86040a5SCatalin Marinas .macro setmode, mode, reg 359b86040a5SCatalin Marinas mov \reg, #\mode 360b86040a5SCatalin Marinas msr cpsr_c, \reg 361b86040a5SCatalin Marinas .endm 362b86040a5SCatalin Marinas #else 363b86040a5SCatalin Marinas .macro setmode, mode, reg 364b86040a5SCatalin Marinas msr cpsr_c, #\mode 365b86040a5SCatalin Marinas .endm 366b86040a5SCatalin Marinas #endif 3678b592783SCatalin Marinas 3688b592783SCatalin Marinas /* 36980c59dafSDave Martin * Helper macro to enter SVC mode cleanly and mask interrupts. reg is 37080c59dafSDave Martin * a scratch register for the macro to overwrite. 37180c59dafSDave Martin * 37280c59dafSDave Martin * This macro is intended for forcing the CPU into SVC mode at boot time. 37380c59dafSDave Martin * you cannot return to the original mode. 37480c59dafSDave Martin */ 37580c59dafSDave Martin .macro safe_svcmode_maskall reg:req 3760e0779daSLorenzo Pieralisi #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M) 37780c59dafSDave Martin mrs \reg , cpsr 3788e9c24a2SRussell King eor \reg, \reg, #HYP_MODE 3798e9c24a2SRussell King tst \reg, #MODE_MASK 38080c59dafSDave Martin bic \reg , \reg , #MODE_MASK 3818e9c24a2SRussell King orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE 38280c59dafSDave Martin THUMB( orr \reg , \reg , #PSR_T_BIT ) 38380c59dafSDave Martin bne 1f 3842a552d5eSMarc Zyngier orr \reg, \reg, #PSR_A_BIT 38514327c66SRussell King badr lr, 2f 3862a552d5eSMarc Zyngier msr spsr_cxsf, \reg 38780c59dafSDave Martin __MSR_ELR_HYP(14) 38880c59dafSDave Martin __ERET 3892a552d5eSMarc Zyngier 1: msr cpsr_c, \reg 39080c59dafSDave Martin 2: 3911ecec696SDave Martin #else 3921ecec696SDave Martin /* 3931ecec696SDave Martin * workaround for possibly broken pre-v6 hardware 3941ecec696SDave Martin * (akita, Sharp Zaurus C-1000, PXA270-based) 3951ecec696SDave Martin */ 3961ecec696SDave Martin setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg 3971ecec696SDave Martin #endif 39880c59dafSDave Martin .endm 39980c59dafSDave Martin 40080c59dafSDave Martin /* 4018b592783SCatalin Marinas * STRT/LDRT access macros with ARM and Thumb-2 variants 4028b592783SCatalin Marinas */ 4038b592783SCatalin Marinas #ifdef CONFIG_THUMB2_KERNEL 4048b592783SCatalin Marinas 4054e7682d0SCatalin Marinas .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 4068b592783SCatalin Marinas 9999: 4078b592783SCatalin Marinas .if \inc == 1 408c001899aSStefan Agner \instr\()b\t\cond\().w \reg, [\ptr, #\off] 4098b592783SCatalin Marinas .elseif \inc == 4 410c001899aSStefan Agner \instr\t\cond\().w \reg, [\ptr, #\off] 4118b592783SCatalin Marinas .else 4128b592783SCatalin Marinas .error "Unsupported inc macro argument" 4138b592783SCatalin Marinas .endif 4148b592783SCatalin Marinas 4154260415fSRussell King .pushsection __ex_table,"a" 4168b592783SCatalin Marinas .align 3 4178b592783SCatalin Marinas .long 9999b, \abort 4184260415fSRussell King .popsection 4198b592783SCatalin Marinas .endm 4208b592783SCatalin Marinas 4218b592783SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort 4228b592783SCatalin Marinas @ explicit IT instruction needed because of the label 4238b592783SCatalin Marinas @ introduced by the USER macro 4248b592783SCatalin Marinas .ifnc \cond,al 4258b592783SCatalin Marinas .if \rept == 1 4268b592783SCatalin Marinas itt \cond 4278b592783SCatalin Marinas .elseif \rept == 2 4288b592783SCatalin Marinas ittt \cond 4298b592783SCatalin Marinas .else 4308b592783SCatalin Marinas .error "Unsupported rept macro argument" 4318b592783SCatalin Marinas .endif 4328b592783SCatalin Marinas .endif 4338b592783SCatalin Marinas 4348b592783SCatalin Marinas @ Slightly optimised to avoid incrementing the pointer twice 4358b592783SCatalin Marinas usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 4368b592783SCatalin Marinas .if \rept == 2 4371142b71dSWill Deacon usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 4388b592783SCatalin Marinas .endif 4398b592783SCatalin Marinas 4408b592783SCatalin Marinas add\cond \ptr, #\rept * \inc 4418b592783SCatalin Marinas .endm 4428b592783SCatalin Marinas 4438b592783SCatalin Marinas #else /* !CONFIG_THUMB2_KERNEL */ 4448b592783SCatalin Marinas 4454e7682d0SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 4468b592783SCatalin Marinas .rept \rept 4478b592783SCatalin Marinas 9999: 4488b592783SCatalin Marinas .if \inc == 1 449c001899aSStefan Agner \instr\()b\t\cond \reg, [\ptr], #\inc 4508b592783SCatalin Marinas .elseif \inc == 4 451c001899aSStefan Agner \instr\t\cond \reg, [\ptr], #\inc 4528b592783SCatalin Marinas .else 4538b592783SCatalin Marinas .error "Unsupported inc macro argument" 4548b592783SCatalin Marinas .endif 4558b592783SCatalin Marinas 4564260415fSRussell King .pushsection __ex_table,"a" 4578b592783SCatalin Marinas .align 3 4588b592783SCatalin Marinas .long 9999b, \abort 4594260415fSRussell King .popsection 4608b592783SCatalin Marinas .endr 4618b592783SCatalin Marinas .endm 4628b592783SCatalin Marinas 4638b592783SCatalin Marinas #endif /* CONFIG_THUMB2_KERNEL */ 4648b592783SCatalin Marinas 4658b592783SCatalin Marinas .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 4668b592783SCatalin Marinas usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 4678b592783SCatalin Marinas .endm 4688b592783SCatalin Marinas 4698b592783SCatalin Marinas .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 4708b592783SCatalin Marinas usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 4718b592783SCatalin Marinas .endm 4728f51965eSDave Martin 4738f51965eSDave Martin /* Utility macro for declaring string literals */ 4748f51965eSDave Martin .macro string name:req, string 4758f51965eSDave Martin .type \name , #object 4768f51965eSDave Martin \name: 4778f51965eSDave Martin .asciz "\string" 4788f51965eSDave Martin .size \name , . - \name 4798f51965eSDave Martin .endm 4808f51965eSDave Martin 4816ebbf2ceSRussell King .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 4826ebbf2ceSRussell King .macro ret\c, reg 4836ebbf2ceSRussell King #if __LINUX_ARM_ARCH__ < 6 4846ebbf2ceSRussell King mov\c pc, \reg 4856ebbf2ceSRussell King #else 4866ebbf2ceSRussell King .ifeqs "\reg", "lr" 4876ebbf2ceSRussell King bx\c \reg 4886ebbf2ceSRussell King .else 4896ebbf2ceSRussell King mov\c pc, \reg 4906ebbf2ceSRussell King .endif 4916ebbf2ceSRussell King #endif 4926ebbf2ceSRussell King .endm 4936ebbf2ceSRussell King .endr 4946ebbf2ceSRussell King 4956ebbf2ceSRussell King .macro ret.w, reg 4966ebbf2ceSRussell King ret \reg 4976ebbf2ceSRussell King #ifdef CONFIG_THUMB2_KERNEL 4986ebbf2ceSRussell King nop 4996ebbf2ceSRussell King #endif 5006ebbf2ceSRussell King .endm 5016ebbf2ceSRussell King 5028bafae20SRussell King .macro bug, msg, line 5038bafae20SRussell King #ifdef CONFIG_THUMB2_KERNEL 5048bafae20SRussell King 1: .inst 0xde02 5058bafae20SRussell King #else 5068bafae20SRussell King 1: .inst 0xe7f001f2 5078bafae20SRussell King #endif 5088bafae20SRussell King #ifdef CONFIG_DEBUG_BUGVERBOSE 5098bafae20SRussell King .pushsection .rodata.str, "aMS", %progbits, 1 5108bafae20SRussell King 2: .asciz "\msg" 5118bafae20SRussell King .popsection 5128bafae20SRussell King .pushsection __bug_table, "aw" 5138bafae20SRussell King .align 2 5148bafae20SRussell King .word 1b, 2b 5158bafae20SRussell King .hword \line 5168bafae20SRussell King .popsection 5178bafae20SRussell King #endif 5188bafae20SRussell King .endm 5198bafae20SRussell King 5200d73c3f8SMasami Hiramatsu #ifdef CONFIG_KPROBES 5210d73c3f8SMasami Hiramatsu #define _ASM_NOKPROBE(entry) \ 5220d73c3f8SMasami Hiramatsu .pushsection "_kprobe_blacklist", "aw" ; \ 5230d73c3f8SMasami Hiramatsu .balign 4 ; \ 5240d73c3f8SMasami Hiramatsu .long entry; \ 5250d73c3f8SMasami Hiramatsu .popsection 5260d73c3f8SMasami Hiramatsu #else 5270d73c3f8SMasami Hiramatsu #define _ASM_NOKPROBE(entry) 5280d73c3f8SMasami Hiramatsu #endif 5290d73c3f8SMasami Hiramatsu 5300b167463SArd Biesheuvel .macro __adldst_l, op, reg, sym, tmp, c 5310b167463SArd Biesheuvel .if __LINUX_ARM_ARCH__ < 7 5320b167463SArd Biesheuvel ldr\c \tmp, .La\@ 5330b167463SArd Biesheuvel .subsection 1 5340b167463SArd Biesheuvel .align 2 5350b167463SArd Biesheuvel .La\@: .long \sym - .Lpc\@ 5360b167463SArd Biesheuvel .previous 5370b167463SArd Biesheuvel .else 5380b167463SArd Biesheuvel .ifnb \c 5390b167463SArd Biesheuvel THUMB( ittt \c ) 5400b167463SArd Biesheuvel .endif 5410b167463SArd Biesheuvel movw\c \tmp, #:lower16:\sym - .Lpc\@ 5420b167463SArd Biesheuvel movt\c \tmp, #:upper16:\sym - .Lpc\@ 5430b167463SArd Biesheuvel .endif 5440b167463SArd Biesheuvel 5450b167463SArd Biesheuvel #ifndef CONFIG_THUMB2_KERNEL 5460b167463SArd Biesheuvel .set .Lpc\@, . + 8 // PC bias 5470b167463SArd Biesheuvel .ifc \op, add 5480b167463SArd Biesheuvel add\c \reg, \tmp, pc 5490b167463SArd Biesheuvel .else 5500b167463SArd Biesheuvel \op\c \reg, [pc, \tmp] 5510b167463SArd Biesheuvel .endif 5520b167463SArd Biesheuvel #else 5530b167463SArd Biesheuvel .Lb\@: add\c \tmp, \tmp, pc 5540b167463SArd Biesheuvel /* 5550b167463SArd Biesheuvel * In Thumb-2 builds, the PC bias depends on whether we are currently 5560b167463SArd Biesheuvel * emitting into a .arm or a .thumb section. The size of the add opcode 5570b167463SArd Biesheuvel * above will be 2 bytes when emitting in Thumb mode and 4 bytes when 5580b167463SArd Biesheuvel * emitting in ARM mode, so let's use this to account for the bias. 5590b167463SArd Biesheuvel */ 5600b167463SArd Biesheuvel .set .Lpc\@, . + (. - .Lb\@) 5610b167463SArd Biesheuvel 5620b167463SArd Biesheuvel .ifnc \op, add 5630b167463SArd Biesheuvel \op\c \reg, [\tmp] 5640b167463SArd Biesheuvel .endif 5650b167463SArd Biesheuvel #endif 5660b167463SArd Biesheuvel .endm 5670b167463SArd Biesheuvel 5680b167463SArd Biesheuvel /* 5690b167463SArd Biesheuvel * mov_l - move a constant value or [relocated] address into a register 5700b167463SArd Biesheuvel */ 571*4e918ab1SArd Biesheuvel .macro mov_l, dst:req, imm:req, cond 5720b167463SArd Biesheuvel .if __LINUX_ARM_ARCH__ < 7 573*4e918ab1SArd Biesheuvel ldr\cond \dst, =\imm 5740b167463SArd Biesheuvel .else 575*4e918ab1SArd Biesheuvel movw\cond \dst, #:lower16:\imm 576*4e918ab1SArd Biesheuvel movt\cond \dst, #:upper16:\imm 5770b167463SArd Biesheuvel .endif 5780b167463SArd Biesheuvel .endm 5790b167463SArd Biesheuvel 5800b167463SArd Biesheuvel /* 5810b167463SArd Biesheuvel * adr_l - adr pseudo-op with unlimited range 5820b167463SArd Biesheuvel * 5830b167463SArd Biesheuvel * @dst: destination register 5840b167463SArd Biesheuvel * @sym: name of the symbol 5850b167463SArd Biesheuvel * @cond: conditional opcode suffix 5860b167463SArd Biesheuvel */ 5870b167463SArd Biesheuvel .macro adr_l, dst:req, sym:req, cond 5880b167463SArd Biesheuvel __adldst_l add, \dst, \sym, \dst, \cond 5890b167463SArd Biesheuvel .endm 5900b167463SArd Biesheuvel 5910b167463SArd Biesheuvel /* 5920b167463SArd Biesheuvel * ldr_l - ldr <literal> pseudo-op with unlimited range 5930b167463SArd Biesheuvel * 5940b167463SArd Biesheuvel * @dst: destination register 5950b167463SArd Biesheuvel * @sym: name of the symbol 5960b167463SArd Biesheuvel * @cond: conditional opcode suffix 5970b167463SArd Biesheuvel */ 5980b167463SArd Biesheuvel .macro ldr_l, dst:req, sym:req, cond 5990b167463SArd Biesheuvel __adldst_l ldr, \dst, \sym, \dst, \cond 6000b167463SArd Biesheuvel .endm 6010b167463SArd Biesheuvel 6020b167463SArd Biesheuvel /* 6030b167463SArd Biesheuvel * str_l - str <literal> pseudo-op with unlimited range 6040b167463SArd Biesheuvel * 6050b167463SArd Biesheuvel * @src: source register 6060b167463SArd Biesheuvel * @sym: name of the symbol 6070b167463SArd Biesheuvel * @tmp: mandatory scratch register 6080b167463SArd Biesheuvel * @cond: conditional opcode suffix 6090b167463SArd Biesheuvel */ 6100b167463SArd Biesheuvel .macro str_l, src:req, sym:req, tmp:req, cond 6110b167463SArd Biesheuvel __adldst_l str, \src, \sym, \tmp, \cond 6120b167463SArd Biesheuvel .endm 6130b167463SArd Biesheuvel 614*4e918ab1SArd Biesheuvel .macro __ldst_va, op, reg, tmp, sym, cond 615*4e918ab1SArd Biesheuvel #if __LINUX_ARM_ARCH__ >= 7 || \ 616*4e918ab1SArd Biesheuvel (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS)) || \ 617*4e918ab1SArd Biesheuvel (defined(CONFIG_LD_IS_LLD) && CONFIG_LLD_VERSION < 140000) 618*4e918ab1SArd Biesheuvel mov_l \tmp, \sym, \cond 619*4e918ab1SArd Biesheuvel \op\cond \reg, [\tmp] 620*4e918ab1SArd Biesheuvel #else 621*4e918ab1SArd Biesheuvel /* 622*4e918ab1SArd Biesheuvel * Avoid a literal load, by emitting a sequence of ADD/LDR instructions 623*4e918ab1SArd Biesheuvel * with the appropriate relocations. The combined sequence has a range 624*4e918ab1SArd Biesheuvel * of -/+ 256 MiB, which should be sufficient for the core kernel and 625*4e918ab1SArd Biesheuvel * for modules loaded into the module region. 626*4e918ab1SArd Biesheuvel */ 627*4e918ab1SArd Biesheuvel .globl \sym 628*4e918ab1SArd Biesheuvel .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym 629*4e918ab1SArd Biesheuvel .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym 630*4e918ab1SArd Biesheuvel .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym 631*4e918ab1SArd Biesheuvel .L0_\@: sub\cond \tmp, pc, #8 632*4e918ab1SArd Biesheuvel .L1_\@: sub\cond \tmp, \tmp, #4 633*4e918ab1SArd Biesheuvel .L2_\@: \op\cond \reg, [\tmp, #0] 634*4e918ab1SArd Biesheuvel #endif 635*4e918ab1SArd Biesheuvel .endm 636*4e918ab1SArd Biesheuvel 637*4e918ab1SArd Biesheuvel /* 638*4e918ab1SArd Biesheuvel * ldr_va - load a 32-bit word from the virtual address of \sym 639*4e918ab1SArd Biesheuvel */ 640*4e918ab1SArd Biesheuvel .macro ldr_va, rd:req, sym:req, cond 641*4e918ab1SArd Biesheuvel __ldst_va ldr, \rd, \rd, \sym, \cond 642*4e918ab1SArd Biesheuvel .endm 643*4e918ab1SArd Biesheuvel 644*4e918ab1SArd Biesheuvel /* 645*4e918ab1SArd Biesheuvel * str_va - store a 32-bit word to the virtual address of \sym 646*4e918ab1SArd Biesheuvel */ 647*4e918ab1SArd Biesheuvel .macro str_va, rn:req, sym:req, tmp:req, cond 648*4e918ab1SArd Biesheuvel __ldst_va str, \rn, \tmp, \sym, \cond 649*4e918ab1SArd Biesheuvel .endm 650*4e918ab1SArd Biesheuvel 6516468e898SArd Biesheuvel /* 6526468e898SArd Biesheuvel * rev_l - byte-swap a 32-bit value 6536468e898SArd Biesheuvel * 6546468e898SArd Biesheuvel * @val: source/destination register 6556468e898SArd Biesheuvel * @tmp: scratch register 6566468e898SArd Biesheuvel */ 6576468e898SArd Biesheuvel .macro rev_l, val:req, tmp:req 6586468e898SArd Biesheuvel .if __LINUX_ARM_ARCH__ < 6 6596468e898SArd Biesheuvel eor \tmp, \val, \val, ror #16 6606468e898SArd Biesheuvel bic \tmp, \tmp, #0x00ff0000 6616468e898SArd Biesheuvel mov \val, \val, ror #8 6626468e898SArd Biesheuvel eor \val, \val, \tmp, lsr #8 6636468e898SArd Biesheuvel .else 6646468e898SArd Biesheuvel rev \val, \val 6656468e898SArd Biesheuvel .endif 6666468e898SArd Biesheuvel .endm 6676468e898SArd Biesheuvel 668b3ab60b1SArd Biesheuvel /* 669b3ab60b1SArd Biesheuvel * bl_r - branch and link to register 670b3ab60b1SArd Biesheuvel * 671b3ab60b1SArd Biesheuvel * @dst: target to branch to 672b3ab60b1SArd Biesheuvel * @c: conditional opcode suffix 673b3ab60b1SArd Biesheuvel */ 674b3ab60b1SArd Biesheuvel .macro bl_r, dst:req, c 675b3ab60b1SArd Biesheuvel .if __LINUX_ARM_ARCH__ < 6 676b3ab60b1SArd Biesheuvel mov\c lr, pc 677b3ab60b1SArd Biesheuvel mov\c pc, \dst 678b3ab60b1SArd Biesheuvel .else 679b3ab60b1SArd Biesheuvel blx\c \dst 680b3ab60b1SArd Biesheuvel .endif 681b3ab60b1SArd Biesheuvel .endm 682b3ab60b1SArd Biesheuvel 6832bc58a6fSMagnus Damm #endif /* __ASM_ASSEMBLER_H__ */ 684