14baa9922SRussell King /* 24baa9922SRussell King * arch/arm/include/asm/assembler.h 34baa9922SRussell King * 44baa9922SRussell King * Copyright (C) 1996-2000 Russell King 54baa9922SRussell King * 64baa9922SRussell King * This program is free software; you can redistribute it and/or modify 74baa9922SRussell King * it under the terms of the GNU General Public License version 2 as 84baa9922SRussell King * published by the Free Software Foundation. 94baa9922SRussell King * 104baa9922SRussell King * This file contains arm architecture specific defines 114baa9922SRussell King * for the different processors. 124baa9922SRussell King * 134baa9922SRussell King * Do not include any C declarations in this file - it is included by 144baa9922SRussell King * assembler source. 154baa9922SRussell King */ 164baa9922SRussell King #ifndef __ASSEMBLY__ 174baa9922SRussell King #error "Only include this from assembly code" 184baa9922SRussell King #endif 194baa9922SRussell King 204baa9922SRussell King #include <asm/ptrace.h> 214baa9922SRussell King 224baa9922SRussell King /* 234baa9922SRussell King * Endian independent macros for shifting bytes within registers. 244baa9922SRussell King */ 254baa9922SRussell King #ifndef __ARMEB__ 264baa9922SRussell King #define pull lsr 274baa9922SRussell King #define push lsl 284baa9922SRussell King #define get_byte_0 lsl #0 294baa9922SRussell King #define get_byte_1 lsr #8 304baa9922SRussell King #define get_byte_2 lsr #16 314baa9922SRussell King #define get_byte_3 lsr #24 324baa9922SRussell King #define put_byte_0 lsl #0 334baa9922SRussell King #define put_byte_1 lsl #8 344baa9922SRussell King #define put_byte_2 lsl #16 354baa9922SRussell King #define put_byte_3 lsl #24 364baa9922SRussell King #else 374baa9922SRussell King #define pull lsl 384baa9922SRussell King #define push lsr 394baa9922SRussell King #define get_byte_0 lsr #24 404baa9922SRussell King #define get_byte_1 lsr #16 414baa9922SRussell King #define get_byte_2 lsr #8 424baa9922SRussell King #define get_byte_3 lsl #0 434baa9922SRussell King #define put_byte_0 lsl #24 444baa9922SRussell King #define put_byte_1 lsl #16 454baa9922SRussell King #define put_byte_2 lsl #8 464baa9922SRussell King #define put_byte_3 lsl #0 474baa9922SRussell King #endif 484baa9922SRussell King 494baa9922SRussell King /* 504baa9922SRussell King * Data preload for architectures that support it 514baa9922SRussell King */ 524baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 5 534baa9922SRussell King #define PLD(code...) code 544baa9922SRussell King #else 554baa9922SRussell King #define PLD(code...) 564baa9922SRussell King #endif 574baa9922SRussell King 584baa9922SRussell King /* 594baa9922SRussell King * This can be used to enable code to cacheline align the destination 604baa9922SRussell King * pointer when bulk writing to memory. Experiments on StrongARM and 614baa9922SRussell King * XScale didn't show this a worthwhile thing to do when the cache is not 624baa9922SRussell King * set to write-allocate (this would need further testing on XScale when WA 634baa9922SRussell King * is used). 644baa9922SRussell King * 654baa9922SRussell King * On Feroceon there is much to gain however, regardless of cache mode. 664baa9922SRussell King */ 674baa9922SRussell King #ifdef CONFIG_CPU_FEROCEON 684baa9922SRussell King #define CALGN(code...) code 694baa9922SRussell King #else 704baa9922SRussell King #define CALGN(code...) 714baa9922SRussell King #endif 724baa9922SRussell King 734baa9922SRussell King /* 744baa9922SRussell King * Enable and disable interrupts 754baa9922SRussell King */ 764baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 6 770d928b0bSUwe Kleine-König .macro disable_irq_notrace 784baa9922SRussell King cpsid i 794baa9922SRussell King .endm 804baa9922SRussell King 810d928b0bSUwe Kleine-König .macro enable_irq_notrace 824baa9922SRussell King cpsie i 834baa9922SRussell King .endm 844baa9922SRussell King #else 850d928b0bSUwe Kleine-König .macro disable_irq_notrace 864baa9922SRussell King msr cpsr_c, #PSR_I_BIT | SVC_MODE 874baa9922SRussell King .endm 884baa9922SRussell King 890d928b0bSUwe Kleine-König .macro enable_irq_notrace 904baa9922SRussell King msr cpsr_c, #SVC_MODE 914baa9922SRussell King .endm 924baa9922SRussell King #endif 934baa9922SRussell King 940d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_off 950d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 960d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 970d928b0bSUwe Kleine-König bl trace_hardirqs_off 980d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 990d928b0bSUwe Kleine-König #endif 1000d928b0bSUwe Kleine-König .endm 1010d928b0bSUwe Kleine-König 1020d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_on_cond, cond 1030d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1040d928b0bSUwe Kleine-König /* 1050d928b0bSUwe Kleine-König * actually the registers should be pushed and pop'd conditionally, but 1060d928b0bSUwe Kleine-König * after bl the flags are certainly clobbered 1070d928b0bSUwe Kleine-König */ 1080d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1090d928b0bSUwe Kleine-König bl\cond trace_hardirqs_on 1100d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1110d928b0bSUwe Kleine-König #endif 1120d928b0bSUwe Kleine-König .endm 1130d928b0bSUwe Kleine-König 1140d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_on 1150d928b0bSUwe Kleine-König asm_trace_hardirqs_on_cond al 1160d928b0bSUwe Kleine-König .endm 1170d928b0bSUwe Kleine-König 1180d928b0bSUwe Kleine-König .macro disable_irq 1190d928b0bSUwe Kleine-König disable_irq_notrace 1200d928b0bSUwe Kleine-König asm_trace_hardirqs_off 1210d928b0bSUwe Kleine-König .endm 1220d928b0bSUwe Kleine-König 1230d928b0bSUwe Kleine-König .macro enable_irq 1240d928b0bSUwe Kleine-König asm_trace_hardirqs_on 1250d928b0bSUwe Kleine-König enable_irq_notrace 1260d928b0bSUwe Kleine-König .endm 1274baa9922SRussell King /* 1284baa9922SRussell King * Save the current IRQ state and disable IRQs. Note that this macro 1294baa9922SRussell King * assumes FIQs are enabled, and that the processor is in SVC mode. 1304baa9922SRussell King */ 1314baa9922SRussell King .macro save_and_disable_irqs, oldcpsr 1324baa9922SRussell King mrs \oldcpsr, cpsr 1334baa9922SRussell King disable_irq 1344baa9922SRussell King .endm 1354baa9922SRussell King 1364baa9922SRussell King /* 1374baa9922SRussell King * Restore interrupt state previously stored in a register. We don't 1384baa9922SRussell King * guarantee that this will preserve the flags. 1394baa9922SRussell King */ 1400d928b0bSUwe Kleine-König .macro restore_irqs_notrace, oldcpsr 1414baa9922SRussell King msr cpsr_c, \oldcpsr 1424baa9922SRussell King .endm 1434baa9922SRussell King 1440d928b0bSUwe Kleine-König .macro restore_irqs, oldcpsr 1450d928b0bSUwe Kleine-König tst \oldcpsr, #PSR_I_BIT 1460d928b0bSUwe Kleine-König asm_trace_hardirqs_on_cond eq 1470d928b0bSUwe Kleine-König restore_irqs_notrace \oldcpsr 1480d928b0bSUwe Kleine-König .endm 1490d928b0bSUwe Kleine-König 1504baa9922SRussell King #define USER(x...) \ 1514baa9922SRussell King 9999: x; \ 1524260415fSRussell King .pushsection __ex_table,"a"; \ 1534baa9922SRussell King .align 3; \ 1544baa9922SRussell King .long 9999b,9001f; \ 1554260415fSRussell King .popsection 156bac4e960SRussell King 157bac4e960SRussell King /* 158bac4e960SRussell King * SMP data memory barrier 159bac4e960SRussell King */ 160bac4e960SRussell King .macro smp_dmb 161bac4e960SRussell King #ifdef CONFIG_SMP 162bac4e960SRussell King #if __LINUX_ARM_ARCH__ >= 7 163bac4e960SRussell King dmb 164bac4e960SRussell King #elif __LINUX_ARM_ARCH__ == 6 165bac4e960SRussell King mcr p15, 0, r0, c7, c10, 5 @ dmb 166bac4e960SRussell King #endif 167bac4e960SRussell King #endif 168bac4e960SRussell King .endm 169b86040a5SCatalin Marinas 170b86040a5SCatalin Marinas #ifdef CONFIG_THUMB2_KERNEL 171b86040a5SCatalin Marinas .macro setmode, mode, reg 172b86040a5SCatalin Marinas mov \reg, #\mode 173b86040a5SCatalin Marinas msr cpsr_c, \reg 174b86040a5SCatalin Marinas .endm 175b86040a5SCatalin Marinas #else 176b86040a5SCatalin Marinas .macro setmode, mode, reg 177b86040a5SCatalin Marinas msr cpsr_c, #\mode 178b86040a5SCatalin Marinas .endm 179b86040a5SCatalin Marinas #endif 1808b592783SCatalin Marinas 1818b592783SCatalin Marinas /* 1828b592783SCatalin Marinas * STRT/LDRT access macros with ARM and Thumb-2 variants 1838b592783SCatalin Marinas */ 1848b592783SCatalin Marinas #ifdef CONFIG_THUMB2_KERNEL 1858b592783SCatalin Marinas 1868b592783SCatalin Marinas .macro usraccoff, instr, reg, ptr, inc, off, cond, abort 1878b592783SCatalin Marinas 9999: 1888b592783SCatalin Marinas .if \inc == 1 1898b592783SCatalin Marinas \instr\cond\()bt \reg, [\ptr, #\off] 1908b592783SCatalin Marinas .elseif \inc == 4 1918b592783SCatalin Marinas \instr\cond\()t \reg, [\ptr, #\off] 1928b592783SCatalin Marinas .else 1938b592783SCatalin Marinas .error "Unsupported inc macro argument" 1948b592783SCatalin Marinas .endif 1958b592783SCatalin Marinas 1964260415fSRussell King .pushsection __ex_table,"a" 1978b592783SCatalin Marinas .align 3 1988b592783SCatalin Marinas .long 9999b, \abort 1994260415fSRussell King .popsection 2008b592783SCatalin Marinas .endm 2018b592783SCatalin Marinas 2028b592783SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort 2038b592783SCatalin Marinas @ explicit IT instruction needed because of the label 2048b592783SCatalin Marinas @ introduced by the USER macro 2058b592783SCatalin Marinas .ifnc \cond,al 2068b592783SCatalin Marinas .if \rept == 1 2078b592783SCatalin Marinas itt \cond 2088b592783SCatalin Marinas .elseif \rept == 2 2098b592783SCatalin Marinas ittt \cond 2108b592783SCatalin Marinas .else 2118b592783SCatalin Marinas .error "Unsupported rept macro argument" 2128b592783SCatalin Marinas .endif 2138b592783SCatalin Marinas .endif 2148b592783SCatalin Marinas 2158b592783SCatalin Marinas @ Slightly optimised to avoid incrementing the pointer twice 2168b592783SCatalin Marinas usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 2178b592783SCatalin Marinas .if \rept == 2 2188b592783SCatalin Marinas usraccoff \instr, \reg, \ptr, \inc, 4, \cond, \abort 2198b592783SCatalin Marinas .endif 2208b592783SCatalin Marinas 2218b592783SCatalin Marinas add\cond \ptr, #\rept * \inc 2228b592783SCatalin Marinas .endm 2238b592783SCatalin Marinas 2248b592783SCatalin Marinas #else /* !CONFIG_THUMB2_KERNEL */ 2258b592783SCatalin Marinas 2268b592783SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort 2278b592783SCatalin Marinas .rept \rept 2288b592783SCatalin Marinas 9999: 2298b592783SCatalin Marinas .if \inc == 1 2308b592783SCatalin Marinas \instr\cond\()bt \reg, [\ptr], #\inc 2318b592783SCatalin Marinas .elseif \inc == 4 2328b592783SCatalin Marinas \instr\cond\()t \reg, [\ptr], #\inc 2338b592783SCatalin Marinas .else 2348b592783SCatalin Marinas .error "Unsupported inc macro argument" 2358b592783SCatalin Marinas .endif 2368b592783SCatalin Marinas 2374260415fSRussell King .pushsection __ex_table,"a" 2388b592783SCatalin Marinas .align 3 2398b592783SCatalin Marinas .long 9999b, \abort 2404260415fSRussell King .popsection 2418b592783SCatalin Marinas .endr 2428b592783SCatalin Marinas .endm 2438b592783SCatalin Marinas 2448b592783SCatalin Marinas #endif /* CONFIG_THUMB2_KERNEL */ 2458b592783SCatalin Marinas 2468b592783SCatalin Marinas .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 2478b592783SCatalin Marinas usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 2488b592783SCatalin Marinas .endm 2498b592783SCatalin Marinas 2508b592783SCatalin Marinas .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 2518b592783SCatalin Marinas usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 2528b592783SCatalin Marinas .endm 253