14baa9922SRussell King /* 24baa9922SRussell King * arch/arm/include/asm/assembler.h 34baa9922SRussell King * 44baa9922SRussell King * Copyright (C) 1996-2000 Russell King 54baa9922SRussell King * 64baa9922SRussell King * This program is free software; you can redistribute it and/or modify 74baa9922SRussell King * it under the terms of the GNU General Public License version 2 as 84baa9922SRussell King * published by the Free Software Foundation. 94baa9922SRussell King * 104baa9922SRussell King * This file contains arm architecture specific defines 114baa9922SRussell King * for the different processors. 124baa9922SRussell King * 134baa9922SRussell King * Do not include any C declarations in this file - it is included by 144baa9922SRussell King * assembler source. 154baa9922SRussell King */ 162bc58a6fSMagnus Damm #ifndef __ASM_ASSEMBLER_H__ 172bc58a6fSMagnus Damm #define __ASM_ASSEMBLER_H__ 182bc58a6fSMagnus Damm 194baa9922SRussell King #ifndef __ASSEMBLY__ 204baa9922SRussell King #error "Only include this from assembly code" 214baa9922SRussell King #endif 224baa9922SRussell King 234baa9922SRussell King #include <asm/ptrace.h> 24247055aaSCatalin Marinas #include <asm/domain.h> 2580c59dafSDave Martin #include <asm/opcodes-virt.h> 260b1f68e8SCatalin Marinas #include <asm/asm-offsets.h> 279a2b51b6SAndrey Ryabinin #include <asm/page.h> 289a2b51b6SAndrey Ryabinin #include <asm/thread_info.h> 294baa9922SRussell King 306f6f6a70SRob Herring #define IOMEM(x) (x) 316f6f6a70SRob Herring 324baa9922SRussell King /* 334baa9922SRussell King * Endian independent macros for shifting bytes within registers. 344baa9922SRussell King */ 354baa9922SRussell King #ifndef __ARMEB__ 36d98b90eaSVictor Kamensky #define lspull lsr 37d98b90eaSVictor Kamensky #define lspush lsl 384baa9922SRussell King #define get_byte_0 lsl #0 394baa9922SRussell King #define get_byte_1 lsr #8 404baa9922SRussell King #define get_byte_2 lsr #16 414baa9922SRussell King #define get_byte_3 lsr #24 424baa9922SRussell King #define put_byte_0 lsl #0 434baa9922SRussell King #define put_byte_1 lsl #8 444baa9922SRussell King #define put_byte_2 lsl #16 454baa9922SRussell King #define put_byte_3 lsl #24 464baa9922SRussell King #else 47d98b90eaSVictor Kamensky #define lspull lsl 48d98b90eaSVictor Kamensky #define lspush lsr 494baa9922SRussell King #define get_byte_0 lsr #24 504baa9922SRussell King #define get_byte_1 lsr #16 514baa9922SRussell King #define get_byte_2 lsr #8 524baa9922SRussell King #define get_byte_3 lsl #0 534baa9922SRussell King #define put_byte_0 lsl #24 544baa9922SRussell King #define put_byte_1 lsl #16 554baa9922SRussell King #define put_byte_2 lsl #8 564baa9922SRussell King #define put_byte_3 lsl #0 574baa9922SRussell King #endif 584baa9922SRussell King 59457c2403SBen Dooks /* Select code for any configuration running in BE8 mode */ 60457c2403SBen Dooks #ifdef CONFIG_CPU_ENDIAN_BE8 61457c2403SBen Dooks #define ARM_BE8(code...) code 62457c2403SBen Dooks #else 63457c2403SBen Dooks #define ARM_BE8(code...) 64457c2403SBen Dooks #endif 65457c2403SBen Dooks 664baa9922SRussell King /* 674baa9922SRussell King * Data preload for architectures that support it 684baa9922SRussell King */ 694baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 5 704baa9922SRussell King #define PLD(code...) code 714baa9922SRussell King #else 724baa9922SRussell King #define PLD(code...) 734baa9922SRussell King #endif 744baa9922SRussell King 754baa9922SRussell King /* 764baa9922SRussell King * This can be used to enable code to cacheline align the destination 774baa9922SRussell King * pointer when bulk writing to memory. Experiments on StrongARM and 784baa9922SRussell King * XScale didn't show this a worthwhile thing to do when the cache is not 794baa9922SRussell King * set to write-allocate (this would need further testing on XScale when WA 804baa9922SRussell King * is used). 814baa9922SRussell King * 824baa9922SRussell King * On Feroceon there is much to gain however, regardless of cache mode. 834baa9922SRussell King */ 844baa9922SRussell King #ifdef CONFIG_CPU_FEROCEON 854baa9922SRussell King #define CALGN(code...) code 864baa9922SRussell King #else 874baa9922SRussell King #define CALGN(code...) 884baa9922SRussell King #endif 894baa9922SRussell King 904baa9922SRussell King /* 914baa9922SRussell King * Enable and disable interrupts 924baa9922SRussell King */ 934baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 6 940d928b0bSUwe Kleine-König .macro disable_irq_notrace 954baa9922SRussell King cpsid i 964baa9922SRussell King .endm 974baa9922SRussell King 980d928b0bSUwe Kleine-König .macro enable_irq_notrace 994baa9922SRussell King cpsie i 1004baa9922SRussell King .endm 1014baa9922SRussell King #else 1020d928b0bSUwe Kleine-König .macro disable_irq_notrace 1034baa9922SRussell King msr cpsr_c, #PSR_I_BIT | SVC_MODE 1044baa9922SRussell King .endm 1054baa9922SRussell King 1060d928b0bSUwe Kleine-König .macro enable_irq_notrace 1074baa9922SRussell King msr cpsr_c, #SVC_MODE 1084baa9922SRussell King .endm 1094baa9922SRussell King #endif 1104baa9922SRussell King 1110d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_off 1120d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1130d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1140d928b0bSUwe Kleine-König bl trace_hardirqs_off 1150d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1160d928b0bSUwe Kleine-König #endif 1170d928b0bSUwe Kleine-König .endm 1180d928b0bSUwe Kleine-König 1190d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_on_cond, cond 1200d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1210d928b0bSUwe Kleine-König /* 1220d928b0bSUwe Kleine-König * actually the registers should be pushed and pop'd conditionally, but 1230d928b0bSUwe Kleine-König * after bl the flags are certainly clobbered 1240d928b0bSUwe Kleine-König */ 1250d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1260d928b0bSUwe Kleine-König bl\cond trace_hardirqs_on 1270d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1280d928b0bSUwe Kleine-König #endif 1290d928b0bSUwe Kleine-König .endm 1300d928b0bSUwe Kleine-König 1310d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_on 1320d928b0bSUwe Kleine-König asm_trace_hardirqs_on_cond al 1330d928b0bSUwe Kleine-König .endm 1340d928b0bSUwe Kleine-König 1350d928b0bSUwe Kleine-König .macro disable_irq 1360d928b0bSUwe Kleine-König disable_irq_notrace 1370d928b0bSUwe Kleine-König asm_trace_hardirqs_off 1380d928b0bSUwe Kleine-König .endm 1390d928b0bSUwe Kleine-König 1400d928b0bSUwe Kleine-König .macro enable_irq 1410d928b0bSUwe Kleine-König asm_trace_hardirqs_on 1420d928b0bSUwe Kleine-König enable_irq_notrace 1430d928b0bSUwe Kleine-König .endm 1444baa9922SRussell King /* 1454baa9922SRussell King * Save the current IRQ state and disable IRQs. Note that this macro 1464baa9922SRussell King * assumes FIQs are enabled, and that the processor is in SVC mode. 1474baa9922SRussell King */ 1484baa9922SRussell King .macro save_and_disable_irqs, oldcpsr 14955bdd694SCatalin Marinas #ifdef CONFIG_CPU_V7M 15055bdd694SCatalin Marinas mrs \oldcpsr, primask 15155bdd694SCatalin Marinas #else 1524baa9922SRussell King mrs \oldcpsr, cpsr 15355bdd694SCatalin Marinas #endif 1544baa9922SRussell King disable_irq 1554baa9922SRussell King .endm 1564baa9922SRussell King 1578e43a905SRabin Vincent .macro save_and_disable_irqs_notrace, oldcpsr 1588e43a905SRabin Vincent mrs \oldcpsr, cpsr 1598e43a905SRabin Vincent disable_irq_notrace 1608e43a905SRabin Vincent .endm 1618e43a905SRabin Vincent 1624baa9922SRussell King /* 1634baa9922SRussell King * Restore interrupt state previously stored in a register. We don't 1644baa9922SRussell King * guarantee that this will preserve the flags. 1654baa9922SRussell King */ 1660d928b0bSUwe Kleine-König .macro restore_irqs_notrace, oldcpsr 16755bdd694SCatalin Marinas #ifdef CONFIG_CPU_V7M 16855bdd694SCatalin Marinas msr primask, \oldcpsr 16955bdd694SCatalin Marinas #else 1704baa9922SRussell King msr cpsr_c, \oldcpsr 17155bdd694SCatalin Marinas #endif 1724baa9922SRussell King .endm 1734baa9922SRussell King 1740d928b0bSUwe Kleine-König .macro restore_irqs, oldcpsr 1750d928b0bSUwe Kleine-König tst \oldcpsr, #PSR_I_BIT 1760d928b0bSUwe Kleine-König asm_trace_hardirqs_on_cond eq 1770d928b0bSUwe Kleine-König restore_irqs_notrace \oldcpsr 1780d928b0bSUwe Kleine-König .endm 1790d928b0bSUwe Kleine-König 18039ad04ccSCatalin Marinas /* 18114327c66SRussell King * Assembly version of "adr rd, BSYM(sym)". This should only be used to 18214327c66SRussell King * reference local symbols in the same assembly file which are to be 18314327c66SRussell King * resolved by the assembler. Other usage is undefined. 18414327c66SRussell King */ 18514327c66SRussell King .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 18614327c66SRussell King .macro badr\c, rd, sym 18714327c66SRussell King #ifdef CONFIG_THUMB2_KERNEL 18814327c66SRussell King adr\c \rd, \sym + 1 18914327c66SRussell King #else 19014327c66SRussell King adr\c \rd, \sym 19114327c66SRussell King #endif 19214327c66SRussell King .endm 19314327c66SRussell King .endr 19414327c66SRussell King 19514327c66SRussell King /* 19639ad04ccSCatalin Marinas * Get current thread_info. 19739ad04ccSCatalin Marinas */ 19839ad04ccSCatalin Marinas .macro get_thread_info, rd 1999a2b51b6SAndrey Ryabinin ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT ) 20039ad04ccSCatalin Marinas THUMB( mov \rd, sp ) 2019a2b51b6SAndrey Ryabinin THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT ) 2029a2b51b6SAndrey Ryabinin mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT 20339ad04ccSCatalin Marinas .endm 20439ad04ccSCatalin Marinas 2050b1f68e8SCatalin Marinas /* 2060b1f68e8SCatalin Marinas * Increment/decrement the preempt count. 2070b1f68e8SCatalin Marinas */ 2080b1f68e8SCatalin Marinas #ifdef CONFIG_PREEMPT_COUNT 2090b1f68e8SCatalin Marinas .macro inc_preempt_count, ti, tmp 2100b1f68e8SCatalin Marinas ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 2110b1f68e8SCatalin Marinas add \tmp, \tmp, #1 @ increment it 2120b1f68e8SCatalin Marinas str \tmp, [\ti, #TI_PREEMPT] 2130b1f68e8SCatalin Marinas .endm 2140b1f68e8SCatalin Marinas 2150b1f68e8SCatalin Marinas .macro dec_preempt_count, ti, tmp 2160b1f68e8SCatalin Marinas ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 2170b1f68e8SCatalin Marinas sub \tmp, \tmp, #1 @ decrement it 2180b1f68e8SCatalin Marinas str \tmp, [\ti, #TI_PREEMPT] 2190b1f68e8SCatalin Marinas .endm 2200b1f68e8SCatalin Marinas 2210b1f68e8SCatalin Marinas .macro dec_preempt_count_ti, ti, tmp 2220b1f68e8SCatalin Marinas get_thread_info \ti 2230b1f68e8SCatalin Marinas dec_preempt_count \ti, \tmp 2240b1f68e8SCatalin Marinas .endm 2250b1f68e8SCatalin Marinas #else 2260b1f68e8SCatalin Marinas .macro inc_preempt_count, ti, tmp 2270b1f68e8SCatalin Marinas .endm 2280b1f68e8SCatalin Marinas 2290b1f68e8SCatalin Marinas .macro dec_preempt_count, ti, tmp 2300b1f68e8SCatalin Marinas .endm 2310b1f68e8SCatalin Marinas 2320b1f68e8SCatalin Marinas .macro dec_preempt_count_ti, ti, tmp 2330b1f68e8SCatalin Marinas .endm 2340b1f68e8SCatalin Marinas #endif 2350b1f68e8SCatalin Marinas 2364baa9922SRussell King #define USER(x...) \ 2374baa9922SRussell King 9999: x; \ 2384260415fSRussell King .pushsection __ex_table,"a"; \ 2394baa9922SRussell King .align 3; \ 2404baa9922SRussell King .long 9999b,9001f; \ 2414260415fSRussell King .popsection 242bac4e960SRussell King 243f00ec48fSRussell King #ifdef CONFIG_SMP 244f00ec48fSRussell King #define ALT_SMP(instr...) \ 245f00ec48fSRussell King 9998: instr 246ed3768a8SDave Martin /* 247ed3768a8SDave Martin * Note: if you get assembler errors from ALT_UP() when building with 248ed3768a8SDave Martin * CONFIG_THUMB2_KERNEL, you almost certainly need to use 249ed3768a8SDave Martin * ALT_SMP( W(instr) ... ) 250ed3768a8SDave Martin */ 251f00ec48fSRussell King #define ALT_UP(instr...) \ 252f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 253f00ec48fSRussell King .long 9998b ;\ 254ed3768a8SDave Martin 9997: instr ;\ 25589c6bc58SRussell King .if . - 9997b == 2 ;\ 25689c6bc58SRussell King nop ;\ 25789c6bc58SRussell King .endif ;\ 258ed3768a8SDave Martin .if . - 9997b != 4 ;\ 259ed3768a8SDave Martin .error "ALT_UP() content must assemble to exactly 4 bytes";\ 260ed3768a8SDave Martin .endif ;\ 261f00ec48fSRussell King .popsection 262f00ec48fSRussell King #define ALT_UP_B(label) \ 263f00ec48fSRussell King .equ up_b_offset, label - 9998b ;\ 264f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 265f00ec48fSRussell King .long 9998b ;\ 266ed3768a8SDave Martin W(b) . + up_b_offset ;\ 267f00ec48fSRussell King .popsection 268f00ec48fSRussell King #else 269f00ec48fSRussell King #define ALT_SMP(instr...) 270f00ec48fSRussell King #define ALT_UP(instr...) instr 271f00ec48fSRussell King #define ALT_UP_B(label) b label 272f00ec48fSRussell King #endif 273f00ec48fSRussell King 274bac4e960SRussell King /* 275d675d0bcSWill Deacon * Instruction barrier 276d675d0bcSWill Deacon */ 277d675d0bcSWill Deacon .macro instr_sync 278d675d0bcSWill Deacon #if __LINUX_ARM_ARCH__ >= 7 279d675d0bcSWill Deacon isb 280d675d0bcSWill Deacon #elif __LINUX_ARM_ARCH__ == 6 281d675d0bcSWill Deacon mcr p15, 0, r0, c7, c5, 4 282d675d0bcSWill Deacon #endif 283d675d0bcSWill Deacon .endm 284d675d0bcSWill Deacon 285d675d0bcSWill Deacon /* 286bac4e960SRussell King * SMP data memory barrier 287bac4e960SRussell King */ 288ed3768a8SDave Martin .macro smp_dmb mode 289bac4e960SRussell King #ifdef CONFIG_SMP 290bac4e960SRussell King #if __LINUX_ARM_ARCH__ >= 7 291ed3768a8SDave Martin .ifeqs "\mode","arm" 2923ea12806SWill Deacon ALT_SMP(dmb ish) 293ed3768a8SDave Martin .else 2943ea12806SWill Deacon ALT_SMP(W(dmb) ish) 295ed3768a8SDave Martin .endif 296bac4e960SRussell King #elif __LINUX_ARM_ARCH__ == 6 297f00ec48fSRussell King ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 298f00ec48fSRussell King #else 299f00ec48fSRussell King #error Incompatible SMP platform 300bac4e960SRussell King #endif 301ed3768a8SDave Martin .ifeqs "\mode","arm" 302f00ec48fSRussell King ALT_UP(nop) 303ed3768a8SDave Martin .else 304ed3768a8SDave Martin ALT_UP(W(nop)) 305ed3768a8SDave Martin .endif 306bac4e960SRussell King #endif 307bac4e960SRussell King .endm 308b86040a5SCatalin Marinas 30955bdd694SCatalin Marinas #if defined(CONFIG_CPU_V7M) 31055bdd694SCatalin Marinas /* 31155bdd694SCatalin Marinas * setmode is used to assert to be in svc mode during boot. For v7-M 31255bdd694SCatalin Marinas * this is done in __v7m_setup, so setmode can be empty here. 31355bdd694SCatalin Marinas */ 31455bdd694SCatalin Marinas .macro setmode, mode, reg 31555bdd694SCatalin Marinas .endm 31655bdd694SCatalin Marinas #elif defined(CONFIG_THUMB2_KERNEL) 317b86040a5SCatalin Marinas .macro setmode, mode, reg 318b86040a5SCatalin Marinas mov \reg, #\mode 319b86040a5SCatalin Marinas msr cpsr_c, \reg 320b86040a5SCatalin Marinas .endm 321b86040a5SCatalin Marinas #else 322b86040a5SCatalin Marinas .macro setmode, mode, reg 323b86040a5SCatalin Marinas msr cpsr_c, #\mode 324b86040a5SCatalin Marinas .endm 325b86040a5SCatalin Marinas #endif 3268b592783SCatalin Marinas 3278b592783SCatalin Marinas /* 32880c59dafSDave Martin * Helper macro to enter SVC mode cleanly and mask interrupts. reg is 32980c59dafSDave Martin * a scratch register for the macro to overwrite. 33080c59dafSDave Martin * 33180c59dafSDave Martin * This macro is intended for forcing the CPU into SVC mode at boot time. 33280c59dafSDave Martin * you cannot return to the original mode. 33380c59dafSDave Martin */ 33480c59dafSDave Martin .macro safe_svcmode_maskall reg:req 3350e0779daSLorenzo Pieralisi #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M) 33680c59dafSDave Martin mrs \reg , cpsr 3378e9c24a2SRussell King eor \reg, \reg, #HYP_MODE 3388e9c24a2SRussell King tst \reg, #MODE_MASK 33980c59dafSDave Martin bic \reg , \reg , #MODE_MASK 3408e9c24a2SRussell King orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE 34180c59dafSDave Martin THUMB( orr \reg , \reg , #PSR_T_BIT ) 34280c59dafSDave Martin bne 1f 3432a552d5eSMarc Zyngier orr \reg, \reg, #PSR_A_BIT 34414327c66SRussell King badr lr, 2f 3452a552d5eSMarc Zyngier msr spsr_cxsf, \reg 34680c59dafSDave Martin __MSR_ELR_HYP(14) 34780c59dafSDave Martin __ERET 3482a552d5eSMarc Zyngier 1: msr cpsr_c, \reg 34980c59dafSDave Martin 2: 3501ecec696SDave Martin #else 3511ecec696SDave Martin /* 3521ecec696SDave Martin * workaround for possibly broken pre-v6 hardware 3531ecec696SDave Martin * (akita, Sharp Zaurus C-1000, PXA270-based) 3541ecec696SDave Martin */ 3551ecec696SDave Martin setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg 3561ecec696SDave Martin #endif 35780c59dafSDave Martin .endm 35880c59dafSDave Martin 35980c59dafSDave Martin /* 3608b592783SCatalin Marinas * STRT/LDRT access macros with ARM and Thumb-2 variants 3618b592783SCatalin Marinas */ 3628b592783SCatalin Marinas #ifdef CONFIG_THUMB2_KERNEL 3638b592783SCatalin Marinas 3644e7682d0SCatalin Marinas .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 3658b592783SCatalin Marinas 9999: 3668b592783SCatalin Marinas .if \inc == 1 367247055aaSCatalin Marinas \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] 3688b592783SCatalin Marinas .elseif \inc == 4 369247055aaSCatalin Marinas \instr\cond\()\t\().w \reg, [\ptr, #\off] 3708b592783SCatalin Marinas .else 3718b592783SCatalin Marinas .error "Unsupported inc macro argument" 3728b592783SCatalin Marinas .endif 3738b592783SCatalin Marinas 3744260415fSRussell King .pushsection __ex_table,"a" 3758b592783SCatalin Marinas .align 3 3768b592783SCatalin Marinas .long 9999b, \abort 3774260415fSRussell King .popsection 3788b592783SCatalin Marinas .endm 3798b592783SCatalin Marinas 3808b592783SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort 3818b592783SCatalin Marinas @ explicit IT instruction needed because of the label 3828b592783SCatalin Marinas @ introduced by the USER macro 3838b592783SCatalin Marinas .ifnc \cond,al 3848b592783SCatalin Marinas .if \rept == 1 3858b592783SCatalin Marinas itt \cond 3868b592783SCatalin Marinas .elseif \rept == 2 3878b592783SCatalin Marinas ittt \cond 3888b592783SCatalin Marinas .else 3898b592783SCatalin Marinas .error "Unsupported rept macro argument" 3908b592783SCatalin Marinas .endif 3918b592783SCatalin Marinas .endif 3928b592783SCatalin Marinas 3938b592783SCatalin Marinas @ Slightly optimised to avoid incrementing the pointer twice 3948b592783SCatalin Marinas usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 3958b592783SCatalin Marinas .if \rept == 2 3961142b71dSWill Deacon usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 3978b592783SCatalin Marinas .endif 3988b592783SCatalin Marinas 3998b592783SCatalin Marinas add\cond \ptr, #\rept * \inc 4008b592783SCatalin Marinas .endm 4018b592783SCatalin Marinas 4028b592783SCatalin Marinas #else /* !CONFIG_THUMB2_KERNEL */ 4038b592783SCatalin Marinas 4044e7682d0SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 4058b592783SCatalin Marinas .rept \rept 4068b592783SCatalin Marinas 9999: 4078b592783SCatalin Marinas .if \inc == 1 408247055aaSCatalin Marinas \instr\cond\()b\()\t \reg, [\ptr], #\inc 4098b592783SCatalin Marinas .elseif \inc == 4 410247055aaSCatalin Marinas \instr\cond\()\t \reg, [\ptr], #\inc 4118b592783SCatalin Marinas .else 4128b592783SCatalin Marinas .error "Unsupported inc macro argument" 4138b592783SCatalin Marinas .endif 4148b592783SCatalin Marinas 4154260415fSRussell King .pushsection __ex_table,"a" 4168b592783SCatalin Marinas .align 3 4178b592783SCatalin Marinas .long 9999b, \abort 4184260415fSRussell King .popsection 4198b592783SCatalin Marinas .endr 4208b592783SCatalin Marinas .endm 4218b592783SCatalin Marinas 4228b592783SCatalin Marinas #endif /* CONFIG_THUMB2_KERNEL */ 4238b592783SCatalin Marinas 4248b592783SCatalin Marinas .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 4258b592783SCatalin Marinas usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 4268b592783SCatalin Marinas .endm 4278b592783SCatalin Marinas 4288b592783SCatalin Marinas .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 4298b592783SCatalin Marinas usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 4308b592783SCatalin Marinas .endm 4318f51965eSDave Martin 4328f51965eSDave Martin /* Utility macro for declaring string literals */ 4338f51965eSDave Martin .macro string name:req, string 4348f51965eSDave Martin .type \name , #object 4358f51965eSDave Martin \name: 4368f51965eSDave Martin .asciz "\string" 4378f51965eSDave Martin .size \name , . - \name 4388f51965eSDave Martin .endm 4398f51965eSDave Martin 4408404663fSRussell King .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req 4418404663fSRussell King #ifndef CONFIG_CPU_USE_DOMAINS 4428404663fSRussell King adds \tmp, \addr, #\size - 1 4438404663fSRussell King sbcccs \tmp, \tmp, \limit 4448404663fSRussell King bcs \bad 4458404663fSRussell King #endif 4468404663fSRussell King .endm 4478404663fSRussell King 4482190fed6SRussell King .macro uaccess_disable, tmp, isb=1 4492190fed6SRussell King .endm 4502190fed6SRussell King 4512190fed6SRussell King .macro uaccess_enable, tmp, isb=1 4522190fed6SRussell King .endm 4532190fed6SRussell King 4542190fed6SRussell King .macro uaccess_save, tmp 4552190fed6SRussell King .endm 4562190fed6SRussell King 4572190fed6SRussell King .macro uaccess_restore 4582190fed6SRussell King .endm 4592190fed6SRussell King 4602190fed6SRussell King .macro uaccess_save_and_disable, tmp 4612190fed6SRussell King uaccess_save \tmp 4622190fed6SRussell King uaccess_disable \tmp 4632190fed6SRussell King .endm 4642190fed6SRussell King 4656ebbf2ceSRussell King .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 4666ebbf2ceSRussell King .macro ret\c, reg 4676ebbf2ceSRussell King #if __LINUX_ARM_ARCH__ < 6 4686ebbf2ceSRussell King mov\c pc, \reg 4696ebbf2ceSRussell King #else 4706ebbf2ceSRussell King .ifeqs "\reg", "lr" 4716ebbf2ceSRussell King bx\c \reg 4726ebbf2ceSRussell King .else 4736ebbf2ceSRussell King mov\c pc, \reg 4746ebbf2ceSRussell King .endif 4756ebbf2ceSRussell King #endif 4766ebbf2ceSRussell King .endm 4776ebbf2ceSRussell King .endr 4786ebbf2ceSRussell King 4796ebbf2ceSRussell King .macro ret.w, reg 4806ebbf2ceSRussell King ret \reg 4816ebbf2ceSRussell King #ifdef CONFIG_THUMB2_KERNEL 4826ebbf2ceSRussell King nop 4836ebbf2ceSRussell King #endif 4846ebbf2ceSRussell King .endm 4856ebbf2ceSRussell King 4862bc58a6fSMagnus Damm #endif /* __ASM_ASSEMBLER_H__ */ 487