14baa9922SRussell King /* 24baa9922SRussell King * arch/arm/include/asm/assembler.h 34baa9922SRussell King * 44baa9922SRussell King * Copyright (C) 1996-2000 Russell King 54baa9922SRussell King * 64baa9922SRussell King * This program is free software; you can redistribute it and/or modify 74baa9922SRussell King * it under the terms of the GNU General Public License version 2 as 84baa9922SRussell King * published by the Free Software Foundation. 94baa9922SRussell King * 104baa9922SRussell King * This file contains arm architecture specific defines 114baa9922SRussell King * for the different processors. 124baa9922SRussell King * 134baa9922SRussell King * Do not include any C declarations in this file - it is included by 144baa9922SRussell King * assembler source. 154baa9922SRussell King */ 162bc58a6fSMagnus Damm #ifndef __ASM_ASSEMBLER_H__ 172bc58a6fSMagnus Damm #define __ASM_ASSEMBLER_H__ 182bc58a6fSMagnus Damm 194baa9922SRussell King #ifndef __ASSEMBLY__ 204baa9922SRussell King #error "Only include this from assembly code" 214baa9922SRussell King #endif 224baa9922SRussell King 234baa9922SRussell King #include <asm/ptrace.h> 24247055aaSCatalin Marinas #include <asm/domain.h> 2580c59dafSDave Martin #include <asm/opcodes-virt.h> 260b1f68e8SCatalin Marinas #include <asm/asm-offsets.h> 274baa9922SRussell King 286f6f6a70SRob Herring #define IOMEM(x) (x) 296f6f6a70SRob Herring 304baa9922SRussell King /* 314baa9922SRussell King * Endian independent macros for shifting bytes within registers. 324baa9922SRussell King */ 334baa9922SRussell King #ifndef __ARMEB__ 34d98b90eaSVictor Kamensky #define lspull lsr 35d98b90eaSVictor Kamensky #define lspush lsl 364baa9922SRussell King #define get_byte_0 lsl #0 374baa9922SRussell King #define get_byte_1 lsr #8 384baa9922SRussell King #define get_byte_2 lsr #16 394baa9922SRussell King #define get_byte_3 lsr #24 404baa9922SRussell King #define put_byte_0 lsl #0 414baa9922SRussell King #define put_byte_1 lsl #8 424baa9922SRussell King #define put_byte_2 lsl #16 434baa9922SRussell King #define put_byte_3 lsl #24 444baa9922SRussell King #else 45d98b90eaSVictor Kamensky #define lspull lsl 46d98b90eaSVictor Kamensky #define lspush lsr 474baa9922SRussell King #define get_byte_0 lsr #24 484baa9922SRussell King #define get_byte_1 lsr #16 494baa9922SRussell King #define get_byte_2 lsr #8 504baa9922SRussell King #define get_byte_3 lsl #0 514baa9922SRussell King #define put_byte_0 lsl #24 524baa9922SRussell King #define put_byte_1 lsl #16 534baa9922SRussell King #define put_byte_2 lsl #8 544baa9922SRussell King #define put_byte_3 lsl #0 554baa9922SRussell King #endif 564baa9922SRussell King 57457c2403SBen Dooks /* Select code for any configuration running in BE8 mode */ 58457c2403SBen Dooks #ifdef CONFIG_CPU_ENDIAN_BE8 59457c2403SBen Dooks #define ARM_BE8(code...) code 60457c2403SBen Dooks #else 61457c2403SBen Dooks #define ARM_BE8(code...) 62457c2403SBen Dooks #endif 63457c2403SBen Dooks 644baa9922SRussell King /* 654baa9922SRussell King * Data preload for architectures that support it 664baa9922SRussell King */ 674baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 5 684baa9922SRussell King #define PLD(code...) code 694baa9922SRussell King #else 704baa9922SRussell King #define PLD(code...) 714baa9922SRussell King #endif 724baa9922SRussell King 734baa9922SRussell King /* 744baa9922SRussell King * This can be used to enable code to cacheline align the destination 754baa9922SRussell King * pointer when bulk writing to memory. Experiments on StrongARM and 764baa9922SRussell King * XScale didn't show this a worthwhile thing to do when the cache is not 774baa9922SRussell King * set to write-allocate (this would need further testing on XScale when WA 784baa9922SRussell King * is used). 794baa9922SRussell King * 804baa9922SRussell King * On Feroceon there is much to gain however, regardless of cache mode. 814baa9922SRussell King */ 824baa9922SRussell King #ifdef CONFIG_CPU_FEROCEON 834baa9922SRussell King #define CALGN(code...) code 844baa9922SRussell King #else 854baa9922SRussell King #define CALGN(code...) 864baa9922SRussell King #endif 874baa9922SRussell King 884baa9922SRussell King /* 894baa9922SRussell King * Enable and disable interrupts 904baa9922SRussell King */ 914baa9922SRussell King #if __LINUX_ARM_ARCH__ >= 6 920d928b0bSUwe Kleine-König .macro disable_irq_notrace 934baa9922SRussell King cpsid i 944baa9922SRussell King .endm 954baa9922SRussell King 960d928b0bSUwe Kleine-König .macro enable_irq_notrace 974baa9922SRussell King cpsie i 984baa9922SRussell King .endm 994baa9922SRussell King #else 1000d928b0bSUwe Kleine-König .macro disable_irq_notrace 1014baa9922SRussell King msr cpsr_c, #PSR_I_BIT | SVC_MODE 1024baa9922SRussell King .endm 1034baa9922SRussell King 1040d928b0bSUwe Kleine-König .macro enable_irq_notrace 1054baa9922SRussell King msr cpsr_c, #SVC_MODE 1064baa9922SRussell King .endm 1074baa9922SRussell King #endif 1084baa9922SRussell King 1090d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_off 1100d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1110d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1120d928b0bSUwe Kleine-König bl trace_hardirqs_off 1130d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1140d928b0bSUwe Kleine-König #endif 1150d928b0bSUwe Kleine-König .endm 1160d928b0bSUwe Kleine-König 1170d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_on_cond, cond 1180d928b0bSUwe Kleine-König #if defined(CONFIG_TRACE_IRQFLAGS) 1190d928b0bSUwe Kleine-König /* 1200d928b0bSUwe Kleine-König * actually the registers should be pushed and pop'd conditionally, but 1210d928b0bSUwe Kleine-König * after bl the flags are certainly clobbered 1220d928b0bSUwe Kleine-König */ 1230d928b0bSUwe Kleine-König stmdb sp!, {r0-r3, ip, lr} 1240d928b0bSUwe Kleine-König bl\cond trace_hardirqs_on 1250d928b0bSUwe Kleine-König ldmia sp!, {r0-r3, ip, lr} 1260d928b0bSUwe Kleine-König #endif 1270d928b0bSUwe Kleine-König .endm 1280d928b0bSUwe Kleine-König 1290d928b0bSUwe Kleine-König .macro asm_trace_hardirqs_on 1300d928b0bSUwe Kleine-König asm_trace_hardirqs_on_cond al 1310d928b0bSUwe Kleine-König .endm 1320d928b0bSUwe Kleine-König 1330d928b0bSUwe Kleine-König .macro disable_irq 1340d928b0bSUwe Kleine-König disable_irq_notrace 1350d928b0bSUwe Kleine-König asm_trace_hardirqs_off 1360d928b0bSUwe Kleine-König .endm 1370d928b0bSUwe Kleine-König 1380d928b0bSUwe Kleine-König .macro enable_irq 1390d928b0bSUwe Kleine-König asm_trace_hardirqs_on 1400d928b0bSUwe Kleine-König enable_irq_notrace 1410d928b0bSUwe Kleine-König .endm 1424baa9922SRussell King /* 1434baa9922SRussell King * Save the current IRQ state and disable IRQs. Note that this macro 1444baa9922SRussell King * assumes FIQs are enabled, and that the processor is in SVC mode. 1454baa9922SRussell King */ 1464baa9922SRussell King .macro save_and_disable_irqs, oldcpsr 14755bdd694SCatalin Marinas #ifdef CONFIG_CPU_V7M 14855bdd694SCatalin Marinas mrs \oldcpsr, primask 14955bdd694SCatalin Marinas #else 1504baa9922SRussell King mrs \oldcpsr, cpsr 15155bdd694SCatalin Marinas #endif 1524baa9922SRussell King disable_irq 1534baa9922SRussell King .endm 1544baa9922SRussell King 1558e43a905SRabin Vincent .macro save_and_disable_irqs_notrace, oldcpsr 1568e43a905SRabin Vincent mrs \oldcpsr, cpsr 1578e43a905SRabin Vincent disable_irq_notrace 1588e43a905SRabin Vincent .endm 1598e43a905SRabin Vincent 1604baa9922SRussell King /* 1614baa9922SRussell King * Restore interrupt state previously stored in a register. We don't 1624baa9922SRussell King * guarantee that this will preserve the flags. 1634baa9922SRussell King */ 1640d928b0bSUwe Kleine-König .macro restore_irqs_notrace, oldcpsr 16555bdd694SCatalin Marinas #ifdef CONFIG_CPU_V7M 16655bdd694SCatalin Marinas msr primask, \oldcpsr 16755bdd694SCatalin Marinas #else 1684baa9922SRussell King msr cpsr_c, \oldcpsr 16955bdd694SCatalin Marinas #endif 1704baa9922SRussell King .endm 1714baa9922SRussell King 1720d928b0bSUwe Kleine-König .macro restore_irqs, oldcpsr 1730d928b0bSUwe Kleine-König tst \oldcpsr, #PSR_I_BIT 1740d928b0bSUwe Kleine-König asm_trace_hardirqs_on_cond eq 1750d928b0bSUwe Kleine-König restore_irqs_notrace \oldcpsr 1760d928b0bSUwe Kleine-König .endm 1770d928b0bSUwe Kleine-König 17839ad04ccSCatalin Marinas /* 17939ad04ccSCatalin Marinas * Get current thread_info. 18039ad04ccSCatalin Marinas */ 18139ad04ccSCatalin Marinas .macro get_thread_info, rd 18239ad04ccSCatalin Marinas ARM( mov \rd, sp, lsr #13 ) 18339ad04ccSCatalin Marinas THUMB( mov \rd, sp ) 18439ad04ccSCatalin Marinas THUMB( lsr \rd, \rd, #13 ) 18539ad04ccSCatalin Marinas mov \rd, \rd, lsl #13 18639ad04ccSCatalin Marinas .endm 18739ad04ccSCatalin Marinas 1880b1f68e8SCatalin Marinas /* 1890b1f68e8SCatalin Marinas * Increment/decrement the preempt count. 1900b1f68e8SCatalin Marinas */ 1910b1f68e8SCatalin Marinas #ifdef CONFIG_PREEMPT_COUNT 1920b1f68e8SCatalin Marinas .macro inc_preempt_count, ti, tmp 1930b1f68e8SCatalin Marinas ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 1940b1f68e8SCatalin Marinas add \tmp, \tmp, #1 @ increment it 1950b1f68e8SCatalin Marinas str \tmp, [\ti, #TI_PREEMPT] 1960b1f68e8SCatalin Marinas .endm 1970b1f68e8SCatalin Marinas 1980b1f68e8SCatalin Marinas .macro dec_preempt_count, ti, tmp 1990b1f68e8SCatalin Marinas ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 2000b1f68e8SCatalin Marinas sub \tmp, \tmp, #1 @ decrement it 2010b1f68e8SCatalin Marinas str \tmp, [\ti, #TI_PREEMPT] 2020b1f68e8SCatalin Marinas .endm 2030b1f68e8SCatalin Marinas 2040b1f68e8SCatalin Marinas .macro dec_preempt_count_ti, ti, tmp 2050b1f68e8SCatalin Marinas get_thread_info \ti 2060b1f68e8SCatalin Marinas dec_preempt_count \ti, \tmp 2070b1f68e8SCatalin Marinas .endm 2080b1f68e8SCatalin Marinas #else 2090b1f68e8SCatalin Marinas .macro inc_preempt_count, ti, tmp 2100b1f68e8SCatalin Marinas .endm 2110b1f68e8SCatalin Marinas 2120b1f68e8SCatalin Marinas .macro dec_preempt_count, ti, tmp 2130b1f68e8SCatalin Marinas .endm 2140b1f68e8SCatalin Marinas 2150b1f68e8SCatalin Marinas .macro dec_preempt_count_ti, ti, tmp 2160b1f68e8SCatalin Marinas .endm 2170b1f68e8SCatalin Marinas #endif 2180b1f68e8SCatalin Marinas 2194baa9922SRussell King #define USER(x...) \ 2204baa9922SRussell King 9999: x; \ 2214260415fSRussell King .pushsection __ex_table,"a"; \ 2224baa9922SRussell King .align 3; \ 2234baa9922SRussell King .long 9999b,9001f; \ 2244260415fSRussell King .popsection 225bac4e960SRussell King 226f00ec48fSRussell King #ifdef CONFIG_SMP 227f00ec48fSRussell King #define ALT_SMP(instr...) \ 228f00ec48fSRussell King 9998: instr 229ed3768a8SDave Martin /* 230ed3768a8SDave Martin * Note: if you get assembler errors from ALT_UP() when building with 231ed3768a8SDave Martin * CONFIG_THUMB2_KERNEL, you almost certainly need to use 232ed3768a8SDave Martin * ALT_SMP( W(instr) ... ) 233ed3768a8SDave Martin */ 234f00ec48fSRussell King #define ALT_UP(instr...) \ 235f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 236f00ec48fSRussell King .long 9998b ;\ 237ed3768a8SDave Martin 9997: instr ;\ 238ed3768a8SDave Martin .if . - 9997b != 4 ;\ 239ed3768a8SDave Martin .error "ALT_UP() content must assemble to exactly 4 bytes";\ 240ed3768a8SDave Martin .endif ;\ 241f00ec48fSRussell King .popsection 242f00ec48fSRussell King #define ALT_UP_B(label) \ 243f00ec48fSRussell King .equ up_b_offset, label - 9998b ;\ 244f00ec48fSRussell King .pushsection ".alt.smp.init", "a" ;\ 245f00ec48fSRussell King .long 9998b ;\ 246ed3768a8SDave Martin W(b) . + up_b_offset ;\ 247f00ec48fSRussell King .popsection 248f00ec48fSRussell King #else 249f00ec48fSRussell King #define ALT_SMP(instr...) 250f00ec48fSRussell King #define ALT_UP(instr...) instr 251f00ec48fSRussell King #define ALT_UP_B(label) b label 252f00ec48fSRussell King #endif 253f00ec48fSRussell King 254bac4e960SRussell King /* 255d675d0bcSWill Deacon * Instruction barrier 256d675d0bcSWill Deacon */ 257d675d0bcSWill Deacon .macro instr_sync 258d675d0bcSWill Deacon #if __LINUX_ARM_ARCH__ >= 7 259d675d0bcSWill Deacon isb 260d675d0bcSWill Deacon #elif __LINUX_ARM_ARCH__ == 6 261d675d0bcSWill Deacon mcr p15, 0, r0, c7, c5, 4 262d675d0bcSWill Deacon #endif 263d675d0bcSWill Deacon .endm 264d675d0bcSWill Deacon 265d675d0bcSWill Deacon /* 266bac4e960SRussell King * SMP data memory barrier 267bac4e960SRussell King */ 268ed3768a8SDave Martin .macro smp_dmb mode 269bac4e960SRussell King #ifdef CONFIG_SMP 270bac4e960SRussell King #if __LINUX_ARM_ARCH__ >= 7 271ed3768a8SDave Martin .ifeqs "\mode","arm" 2723ea12806SWill Deacon ALT_SMP(dmb ish) 273ed3768a8SDave Martin .else 2743ea12806SWill Deacon ALT_SMP(W(dmb) ish) 275ed3768a8SDave Martin .endif 276bac4e960SRussell King #elif __LINUX_ARM_ARCH__ == 6 277f00ec48fSRussell King ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 278f00ec48fSRussell King #else 279f00ec48fSRussell King #error Incompatible SMP platform 280bac4e960SRussell King #endif 281ed3768a8SDave Martin .ifeqs "\mode","arm" 282f00ec48fSRussell King ALT_UP(nop) 283ed3768a8SDave Martin .else 284ed3768a8SDave Martin ALT_UP(W(nop)) 285ed3768a8SDave Martin .endif 286bac4e960SRussell King #endif 287bac4e960SRussell King .endm 288b86040a5SCatalin Marinas 28955bdd694SCatalin Marinas #if defined(CONFIG_CPU_V7M) 29055bdd694SCatalin Marinas /* 29155bdd694SCatalin Marinas * setmode is used to assert to be in svc mode during boot. For v7-M 29255bdd694SCatalin Marinas * this is done in __v7m_setup, so setmode can be empty here. 29355bdd694SCatalin Marinas */ 29455bdd694SCatalin Marinas .macro setmode, mode, reg 29555bdd694SCatalin Marinas .endm 29655bdd694SCatalin Marinas #elif defined(CONFIG_THUMB2_KERNEL) 297b86040a5SCatalin Marinas .macro setmode, mode, reg 298b86040a5SCatalin Marinas mov \reg, #\mode 299b86040a5SCatalin Marinas msr cpsr_c, \reg 300b86040a5SCatalin Marinas .endm 301b86040a5SCatalin Marinas #else 302b86040a5SCatalin Marinas .macro setmode, mode, reg 303b86040a5SCatalin Marinas msr cpsr_c, #\mode 304b86040a5SCatalin Marinas .endm 305b86040a5SCatalin Marinas #endif 3068b592783SCatalin Marinas 3078b592783SCatalin Marinas /* 30880c59dafSDave Martin * Helper macro to enter SVC mode cleanly and mask interrupts. reg is 30980c59dafSDave Martin * a scratch register for the macro to overwrite. 31080c59dafSDave Martin * 31180c59dafSDave Martin * This macro is intended for forcing the CPU into SVC mode at boot time. 31280c59dafSDave Martin * you cannot return to the original mode. 31380c59dafSDave Martin */ 31480c59dafSDave Martin .macro safe_svcmode_maskall reg:req 3150e0779daSLorenzo Pieralisi #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M) 31680c59dafSDave Martin mrs \reg , cpsr 3178e9c24a2SRussell King eor \reg, \reg, #HYP_MODE 3188e9c24a2SRussell King tst \reg, #MODE_MASK 31980c59dafSDave Martin bic \reg , \reg , #MODE_MASK 3208e9c24a2SRussell King orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE 32180c59dafSDave Martin THUMB( orr \reg , \reg , #PSR_T_BIT ) 32280c59dafSDave Martin bne 1f 3232a552d5eSMarc Zyngier orr \reg, \reg, #PSR_A_BIT 3242a552d5eSMarc Zyngier adr lr, BSYM(2f) 3252a552d5eSMarc Zyngier msr spsr_cxsf, \reg 32680c59dafSDave Martin __MSR_ELR_HYP(14) 32780c59dafSDave Martin __ERET 3282a552d5eSMarc Zyngier 1: msr cpsr_c, \reg 32980c59dafSDave Martin 2: 3301ecec696SDave Martin #else 3311ecec696SDave Martin /* 3321ecec696SDave Martin * workaround for possibly broken pre-v6 hardware 3331ecec696SDave Martin * (akita, Sharp Zaurus C-1000, PXA270-based) 3341ecec696SDave Martin */ 3351ecec696SDave Martin setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg 3361ecec696SDave Martin #endif 33780c59dafSDave Martin .endm 33880c59dafSDave Martin 33980c59dafSDave Martin /* 3408b592783SCatalin Marinas * STRT/LDRT access macros with ARM and Thumb-2 variants 3418b592783SCatalin Marinas */ 3428b592783SCatalin Marinas #ifdef CONFIG_THUMB2_KERNEL 3438b592783SCatalin Marinas 3444e7682d0SCatalin Marinas .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 3458b592783SCatalin Marinas 9999: 3468b592783SCatalin Marinas .if \inc == 1 347247055aaSCatalin Marinas \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] 3488b592783SCatalin Marinas .elseif \inc == 4 349247055aaSCatalin Marinas \instr\cond\()\t\().w \reg, [\ptr, #\off] 3508b592783SCatalin Marinas .else 3518b592783SCatalin Marinas .error "Unsupported inc macro argument" 3528b592783SCatalin Marinas .endif 3538b592783SCatalin Marinas 3544260415fSRussell King .pushsection __ex_table,"a" 3558b592783SCatalin Marinas .align 3 3568b592783SCatalin Marinas .long 9999b, \abort 3574260415fSRussell King .popsection 3588b592783SCatalin Marinas .endm 3598b592783SCatalin Marinas 3608b592783SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort 3618b592783SCatalin Marinas @ explicit IT instruction needed because of the label 3628b592783SCatalin Marinas @ introduced by the USER macro 3638b592783SCatalin Marinas .ifnc \cond,al 3648b592783SCatalin Marinas .if \rept == 1 3658b592783SCatalin Marinas itt \cond 3668b592783SCatalin Marinas .elseif \rept == 2 3678b592783SCatalin Marinas ittt \cond 3688b592783SCatalin Marinas .else 3698b592783SCatalin Marinas .error "Unsupported rept macro argument" 3708b592783SCatalin Marinas .endif 3718b592783SCatalin Marinas .endif 3728b592783SCatalin Marinas 3738b592783SCatalin Marinas @ Slightly optimised to avoid incrementing the pointer twice 3748b592783SCatalin Marinas usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 3758b592783SCatalin Marinas .if \rept == 2 3761142b71dSWill Deacon usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 3778b592783SCatalin Marinas .endif 3788b592783SCatalin Marinas 3798b592783SCatalin Marinas add\cond \ptr, #\rept * \inc 3808b592783SCatalin Marinas .endm 3818b592783SCatalin Marinas 3828b592783SCatalin Marinas #else /* !CONFIG_THUMB2_KERNEL */ 3838b592783SCatalin Marinas 3844e7682d0SCatalin Marinas .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 3858b592783SCatalin Marinas .rept \rept 3868b592783SCatalin Marinas 9999: 3878b592783SCatalin Marinas .if \inc == 1 388247055aaSCatalin Marinas \instr\cond\()b\()\t \reg, [\ptr], #\inc 3898b592783SCatalin Marinas .elseif \inc == 4 390247055aaSCatalin Marinas \instr\cond\()\t \reg, [\ptr], #\inc 3918b592783SCatalin Marinas .else 3928b592783SCatalin Marinas .error "Unsupported inc macro argument" 3938b592783SCatalin Marinas .endif 3948b592783SCatalin Marinas 3954260415fSRussell King .pushsection __ex_table,"a" 3968b592783SCatalin Marinas .align 3 3978b592783SCatalin Marinas .long 9999b, \abort 3984260415fSRussell King .popsection 3998b592783SCatalin Marinas .endr 4008b592783SCatalin Marinas .endm 4018b592783SCatalin Marinas 4028b592783SCatalin Marinas #endif /* CONFIG_THUMB2_KERNEL */ 4038b592783SCatalin Marinas 4048b592783SCatalin Marinas .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 4058b592783SCatalin Marinas usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 4068b592783SCatalin Marinas .endm 4078b592783SCatalin Marinas 4088b592783SCatalin Marinas .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 4098b592783SCatalin Marinas usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 4108b592783SCatalin Marinas .endm 4118f51965eSDave Martin 4128f51965eSDave Martin /* Utility macro for declaring string literals */ 4138f51965eSDave Martin .macro string name:req, string 4148f51965eSDave Martin .type \name , #object 4158f51965eSDave Martin \name: 4168f51965eSDave Martin .asciz "\string" 4178f51965eSDave Martin .size \name , . - \name 4188f51965eSDave Martin .endm 4198f51965eSDave Martin 4208404663fSRussell King .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req 4218404663fSRussell King #ifndef CONFIG_CPU_USE_DOMAINS 4228404663fSRussell King adds \tmp, \addr, #\size - 1 4238404663fSRussell King sbcccs \tmp, \tmp, \limit 4248404663fSRussell King bcs \bad 4258404663fSRussell King #endif 4268404663fSRussell King .endm 4278404663fSRussell King 4282bc58a6fSMagnus Damm #endif /* __ASM_ASSEMBLER_H__ */ 429