xref: /openbmc/linux/arch/arm/include/asm/arch_gicv3.h (revision ddc141e5)
1 /*
2  * arch/arm/include/asm/arch_gicv3.h
3  *
4  * Copyright (C) 2015 ARM Ltd.
5  *
6  * This program is free software: you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18 #ifndef __ASM_ARCH_GICV3_H
19 #define __ASM_ARCH_GICV3_H
20 
21 #ifndef __ASSEMBLY__
22 
23 #include <linux/io.h>
24 #include <asm/barrier.h>
25 #include <asm/cacheflush.h>
26 #include <asm/cp15.h>
27 
28 #define ICC_EOIR1			__ACCESS_CP15(c12, 0, c12, 1)
29 #define ICC_DIR				__ACCESS_CP15(c12, 0, c11, 1)
30 #define ICC_IAR1			__ACCESS_CP15(c12, 0, c12, 0)
31 #define ICC_SGI1R			__ACCESS_CP15_64(0, c12)
32 #define ICC_PMR				__ACCESS_CP15(c4, 0, c6, 0)
33 #define ICC_CTLR			__ACCESS_CP15(c12, 0, c12, 4)
34 #define ICC_SRE				__ACCESS_CP15(c12, 0, c12, 5)
35 #define ICC_IGRPEN1			__ACCESS_CP15(c12, 0, c12, 7)
36 #define ICC_BPR1			__ACCESS_CP15(c12, 0, c12, 3)
37 
38 #define ICC_HSRE			__ACCESS_CP15(c12, 4, c9, 5)
39 
40 #define ICH_VSEIR			__ACCESS_CP15(c12, 4, c9, 4)
41 #define ICH_HCR				__ACCESS_CP15(c12, 4, c11, 0)
42 #define ICH_VTR				__ACCESS_CP15(c12, 4, c11, 1)
43 #define ICH_MISR			__ACCESS_CP15(c12, 4, c11, 2)
44 #define ICH_EISR			__ACCESS_CP15(c12, 4, c11, 3)
45 #define ICH_ELSR			__ACCESS_CP15(c12, 4, c11, 5)
46 #define ICH_VMCR			__ACCESS_CP15(c12, 4, c11, 7)
47 
48 #define __LR0(x)			__ACCESS_CP15(c12, 4, c12, x)
49 #define __LR8(x)			__ACCESS_CP15(c12, 4, c13, x)
50 
51 #define ICH_LR0				__LR0(0)
52 #define ICH_LR1				__LR0(1)
53 #define ICH_LR2				__LR0(2)
54 #define ICH_LR3				__LR0(3)
55 #define ICH_LR4				__LR0(4)
56 #define ICH_LR5				__LR0(5)
57 #define ICH_LR6				__LR0(6)
58 #define ICH_LR7				__LR0(7)
59 #define ICH_LR8				__LR8(0)
60 #define ICH_LR9				__LR8(1)
61 #define ICH_LR10			__LR8(2)
62 #define ICH_LR11			__LR8(3)
63 #define ICH_LR12			__LR8(4)
64 #define ICH_LR13			__LR8(5)
65 #define ICH_LR14			__LR8(6)
66 #define ICH_LR15			__LR8(7)
67 
68 /* LR top half */
69 #define __LRC0(x)			__ACCESS_CP15(c12, 4, c14, x)
70 #define __LRC8(x)			__ACCESS_CP15(c12, 4, c15, x)
71 
72 #define ICH_LRC0			__LRC0(0)
73 #define ICH_LRC1			__LRC0(1)
74 #define ICH_LRC2			__LRC0(2)
75 #define ICH_LRC3			__LRC0(3)
76 #define ICH_LRC4			__LRC0(4)
77 #define ICH_LRC5			__LRC0(5)
78 #define ICH_LRC6			__LRC0(6)
79 #define ICH_LRC7			__LRC0(7)
80 #define ICH_LRC8			__LRC8(0)
81 #define ICH_LRC9			__LRC8(1)
82 #define ICH_LRC10			__LRC8(2)
83 #define ICH_LRC11			__LRC8(3)
84 #define ICH_LRC12			__LRC8(4)
85 #define ICH_LRC13			__LRC8(5)
86 #define ICH_LRC14			__LRC8(6)
87 #define ICH_LRC15			__LRC8(7)
88 
89 #define __AP0Rx(x)			__ACCESS_CP15(c12, 4, c8, x)
90 #define ICH_AP0R0			__AP0Rx(0)
91 #define ICH_AP0R1			__AP0Rx(1)
92 #define ICH_AP0R2			__AP0Rx(2)
93 #define ICH_AP0R3			__AP0Rx(3)
94 
95 #define __AP1Rx(x)			__ACCESS_CP15(c12, 4, c9, x)
96 #define ICH_AP1R0			__AP1Rx(0)
97 #define ICH_AP1R1			__AP1Rx(1)
98 #define ICH_AP1R2			__AP1Rx(2)
99 #define ICH_AP1R3			__AP1Rx(3)
100 
101 /* A32-to-A64 mappings used by VGIC save/restore */
102 
103 #define CPUIF_MAP(a32, a64)			\
104 static inline void write_ ## a64(u32 val)	\
105 {						\
106 	write_sysreg(val, a32);			\
107 }						\
108 static inline u32 read_ ## a64(void)		\
109 {						\
110 	return read_sysreg(a32); 		\
111 }						\
112 
113 #define CPUIF_MAP_LO_HI(a32lo, a32hi, a64)	\
114 static inline void write_ ## a64(u64 val)	\
115 {						\
116 	write_sysreg(lower_32_bits(val), a32lo);\
117 	write_sysreg(upper_32_bits(val), a32hi);\
118 }						\
119 static inline u64 read_ ## a64(void)		\
120 {						\
121 	u64 val = read_sysreg(a32lo);		\
122 						\
123 	val |=	(u64)read_sysreg(a32hi) << 32;	\
124 						\
125 	return val; 				\
126 }
127 
128 CPUIF_MAP(ICH_HCR, ICH_HCR_EL2)
129 CPUIF_MAP(ICH_VTR, ICH_VTR_EL2)
130 CPUIF_MAP(ICH_MISR, ICH_MISR_EL2)
131 CPUIF_MAP(ICH_EISR, ICH_EISR_EL2)
132 CPUIF_MAP(ICH_ELSR, ICH_ELSR_EL2)
133 CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2)
134 CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2)
135 CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2)
136 CPUIF_MAP(ICH_AP0R1, ICH_AP0R1_EL2)
137 CPUIF_MAP(ICH_AP0R0, ICH_AP0R0_EL2)
138 CPUIF_MAP(ICH_AP1R3, ICH_AP1R3_EL2)
139 CPUIF_MAP(ICH_AP1R2, ICH_AP1R2_EL2)
140 CPUIF_MAP(ICH_AP1R1, ICH_AP1R1_EL2)
141 CPUIF_MAP(ICH_AP1R0, ICH_AP1R0_EL2)
142 CPUIF_MAP(ICC_HSRE, ICC_SRE_EL2)
143 CPUIF_MAP(ICC_SRE, ICC_SRE_EL1)
144 
145 CPUIF_MAP_LO_HI(ICH_LR15, ICH_LRC15, ICH_LR15_EL2)
146 CPUIF_MAP_LO_HI(ICH_LR14, ICH_LRC14, ICH_LR14_EL2)
147 CPUIF_MAP_LO_HI(ICH_LR13, ICH_LRC13, ICH_LR13_EL2)
148 CPUIF_MAP_LO_HI(ICH_LR12, ICH_LRC12, ICH_LR12_EL2)
149 CPUIF_MAP_LO_HI(ICH_LR11, ICH_LRC11, ICH_LR11_EL2)
150 CPUIF_MAP_LO_HI(ICH_LR10, ICH_LRC10, ICH_LR10_EL2)
151 CPUIF_MAP_LO_HI(ICH_LR9, ICH_LRC9, ICH_LR9_EL2)
152 CPUIF_MAP_LO_HI(ICH_LR8, ICH_LRC8, ICH_LR8_EL2)
153 CPUIF_MAP_LO_HI(ICH_LR7, ICH_LRC7, ICH_LR7_EL2)
154 CPUIF_MAP_LO_HI(ICH_LR6, ICH_LRC6, ICH_LR6_EL2)
155 CPUIF_MAP_LO_HI(ICH_LR5, ICH_LRC5, ICH_LR5_EL2)
156 CPUIF_MAP_LO_HI(ICH_LR4, ICH_LRC4, ICH_LR4_EL2)
157 CPUIF_MAP_LO_HI(ICH_LR3, ICH_LRC3, ICH_LR3_EL2)
158 CPUIF_MAP_LO_HI(ICH_LR2, ICH_LRC2, ICH_LR2_EL2)
159 CPUIF_MAP_LO_HI(ICH_LR1, ICH_LRC1, ICH_LR1_EL2)
160 CPUIF_MAP_LO_HI(ICH_LR0, ICH_LRC0, ICH_LR0_EL2)
161 
162 #define read_gicreg(r)                 read_##r()
163 #define write_gicreg(v, r)             write_##r(v)
164 
165 /* Low-level accessors */
166 
167 static inline void gic_write_eoir(u32 irq)
168 {
169 	write_sysreg(irq, ICC_EOIR1);
170 	isb();
171 }
172 
173 static inline void gic_write_dir(u32 val)
174 {
175 	write_sysreg(val, ICC_DIR);
176 	isb();
177 }
178 
179 static inline u32 gic_read_iar(void)
180 {
181 	u32 irqstat = read_sysreg(ICC_IAR1);
182 
183 	dsb(sy);
184 
185 	return irqstat;
186 }
187 
188 static inline void gic_write_pmr(u32 val)
189 {
190 	write_sysreg(val, ICC_PMR);
191 }
192 
193 static inline void gic_write_ctlr(u32 val)
194 {
195 	write_sysreg(val, ICC_CTLR);
196 	isb();
197 }
198 
199 static inline u32 gic_read_ctlr(void)
200 {
201 	return read_sysreg(ICC_CTLR);
202 }
203 
204 static inline void gic_write_grpen1(u32 val)
205 {
206 	write_sysreg(val, ICC_IGRPEN1);
207 	isb();
208 }
209 
210 static inline void gic_write_sgi1r(u64 val)
211 {
212 	write_sysreg(val, ICC_SGI1R);
213 }
214 
215 static inline u32 gic_read_sre(void)
216 {
217 	return read_sysreg(ICC_SRE);
218 }
219 
220 static inline void gic_write_sre(u32 val)
221 {
222 	write_sysreg(val, ICC_SRE);
223 	isb();
224 }
225 
226 static inline void gic_write_bpr1(u32 val)
227 {
228 	write_sysreg(val, ICC_BPR1);
229 }
230 
231 /*
232  * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
233  * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
234  * make much sense.
235  * Moreover, 64bit I/O emulation is extremely difficult to implement on
236  * AArch32, since the syndrome register doesn't provide any information for
237  * them.
238  * Consequently, the following IO helpers use 32bit accesses.
239  */
240 static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr)
241 {
242 	writel_relaxed((u32)val, addr);
243 	writel_relaxed((u32)(val >> 32), addr + 4);
244 }
245 
246 static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr)
247 {
248 	u64 val;
249 
250 	val = readl_relaxed(addr);
251 	val |= (u64)readl_relaxed(addr + 4) << 32;
252 	return val;
253 }
254 
255 #define gic_flush_dcache_to_poc(a,l)    __cpuc_flush_dcache_area((a), (l))
256 
257 /*
258  *  GICD_IROUTERn, contain the affinity values associated to each interrupt.
259  *  The upper-word (aff3) will always be 0, so there is no need for a lock.
260  */
261 #define gic_write_irouter(v, c)		__gic_writeq_nonatomic(v, c)
262 
263 /*
264  * GICR_TYPER is an ID register and doesn't need atomicity.
265  */
266 #define gic_read_typer(c)		__gic_readq_nonatomic(c)
267 
268 /*
269  * GITS_BASER - hi and lo bits may be accessed independently.
270  */
271 #define gits_read_baser(c)		__gic_readq_nonatomic(c)
272 #define gits_write_baser(v, c)		__gic_writeq_nonatomic(v, c)
273 
274 /*
275  * GICR_PENDBASER and GICR_PROPBASE are changed with LPIs disabled, so they
276  * won't be being used during any updates and can be changed non-atomically
277  */
278 #define gicr_read_propbaser(c)		__gic_readq_nonatomic(c)
279 #define gicr_write_propbaser(v, c)	__gic_writeq_nonatomic(v, c)
280 #define gicr_read_pendbaser(c)		__gic_readq_nonatomic(c)
281 #define gicr_write_pendbaser(v, c)	__gic_writeq_nonatomic(v, c)
282 
283 /*
284  * GICR_xLPIR - only the lower bits are significant
285  */
286 #define gic_read_lpir(c)		readl_relaxed(c)
287 #define gic_write_lpir(v, c)		writel_relaxed(lower_32_bits(v), c)
288 
289 /*
290  * GITS_TYPER is an ID register and doesn't need atomicity.
291  */
292 #define gits_read_typer(c)		__gic_readq_nonatomic(c)
293 
294 /*
295  * GITS_CBASER - hi and lo bits may be accessed independently.
296  */
297 #define gits_read_cbaser(c)		__gic_readq_nonatomic(c)
298 #define gits_write_cbaser(v, c)		__gic_writeq_nonatomic(v, c)
299 
300 /*
301  * GITS_CWRITER - hi and lo bits may be accessed independently.
302  */
303 #define gits_write_cwriter(v, c)	__gic_writeq_nonatomic(v, c)
304 
305 /*
306  * GITS_VPROPBASER - hi and lo bits may be accessed independently.
307  */
308 #define gits_write_vpropbaser(v, c)	__gic_writeq_nonatomic(v, c)
309 
310 /*
311  * GITS_VPENDBASER - the Valid bit must be cleared before changing
312  * anything else.
313  */
314 static inline void gits_write_vpendbaser(u64 val, void * __iomem addr)
315 {
316 	u32 tmp;
317 
318 	tmp = readl_relaxed(addr + 4);
319 	if (tmp & (GICR_VPENDBASER_Valid >> 32)) {
320 		tmp &= ~(GICR_VPENDBASER_Valid >> 32);
321 		writel_relaxed(tmp, addr + 4);
322 	}
323 
324 	/*
325 	 * Use the fact that __gic_writeq_nonatomic writes the second
326 	 * half of the 64bit quantity after the first.
327 	 */
328 	__gic_writeq_nonatomic(val, addr);
329 }
330 
331 #define gits_read_vpendbaser(c)		__gic_readq_nonatomic(c)
332 
333 #endif /* !__ASSEMBLY__ */
334 #endif /* !__ASM_ARCH_GICV3_H */
335