1 /* 2 * arch/arm/include/asm/arch_gicv3.h 3 * 4 * Copyright (C) 2015 ARM Ltd. 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 #ifndef __ASM_ARCH_GICV3_H 19 #define __ASM_ARCH_GICV3_H 20 21 #ifndef __ASSEMBLY__ 22 23 #include <linux/io.h> 24 #include <asm/barrier.h> 25 #include <asm/cp15.h> 26 27 #define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1) 28 #define ICC_DIR __ACCESS_CP15(c12, 0, c11, 1) 29 #define ICC_IAR1 __ACCESS_CP15(c12, 0, c12, 0) 30 #define ICC_SGI1R __ACCESS_CP15_64(0, c12) 31 #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0) 32 #define ICC_CTLR __ACCESS_CP15(c12, 0, c12, 4) 33 #define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5) 34 #define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7) 35 #define ICC_BPR1 __ACCESS_CP15(c12, 0, c12, 3) 36 37 #define ICC_HSRE __ACCESS_CP15(c12, 4, c9, 5) 38 39 #define ICH_VSEIR __ACCESS_CP15(c12, 4, c9, 4) 40 #define ICH_HCR __ACCESS_CP15(c12, 4, c11, 0) 41 #define ICH_VTR __ACCESS_CP15(c12, 4, c11, 1) 42 #define ICH_MISR __ACCESS_CP15(c12, 4, c11, 2) 43 #define ICH_EISR __ACCESS_CP15(c12, 4, c11, 3) 44 #define ICH_ELSR __ACCESS_CP15(c12, 4, c11, 5) 45 #define ICH_VMCR __ACCESS_CP15(c12, 4, c11, 7) 46 47 #define __LR0(x) __ACCESS_CP15(c12, 4, c12, x) 48 #define __LR8(x) __ACCESS_CP15(c12, 4, c13, x) 49 50 #define ICH_LR0 __LR0(0) 51 #define ICH_LR1 __LR0(1) 52 #define ICH_LR2 __LR0(2) 53 #define ICH_LR3 __LR0(3) 54 #define ICH_LR4 __LR0(4) 55 #define ICH_LR5 __LR0(5) 56 #define ICH_LR6 __LR0(6) 57 #define ICH_LR7 __LR0(7) 58 #define ICH_LR8 __LR8(0) 59 #define ICH_LR9 __LR8(1) 60 #define ICH_LR10 __LR8(2) 61 #define ICH_LR11 __LR8(3) 62 #define ICH_LR12 __LR8(4) 63 #define ICH_LR13 __LR8(5) 64 #define ICH_LR14 __LR8(6) 65 #define ICH_LR15 __LR8(7) 66 67 /* LR top half */ 68 #define __LRC0(x) __ACCESS_CP15(c12, 4, c14, x) 69 #define __LRC8(x) __ACCESS_CP15(c12, 4, c15, x) 70 71 #define ICH_LRC0 __LRC0(0) 72 #define ICH_LRC1 __LRC0(1) 73 #define ICH_LRC2 __LRC0(2) 74 #define ICH_LRC3 __LRC0(3) 75 #define ICH_LRC4 __LRC0(4) 76 #define ICH_LRC5 __LRC0(5) 77 #define ICH_LRC6 __LRC0(6) 78 #define ICH_LRC7 __LRC0(7) 79 #define ICH_LRC8 __LRC8(0) 80 #define ICH_LRC9 __LRC8(1) 81 #define ICH_LRC10 __LRC8(2) 82 #define ICH_LRC11 __LRC8(3) 83 #define ICH_LRC12 __LRC8(4) 84 #define ICH_LRC13 __LRC8(5) 85 #define ICH_LRC14 __LRC8(6) 86 #define ICH_LRC15 __LRC8(7) 87 88 #define __AP0Rx(x) __ACCESS_CP15(c12, 4, c8, x) 89 #define ICH_AP0R0 __AP0Rx(0) 90 #define ICH_AP0R1 __AP0Rx(1) 91 #define ICH_AP0R2 __AP0Rx(2) 92 #define ICH_AP0R3 __AP0Rx(3) 93 94 #define __AP1Rx(x) __ACCESS_CP15(c12, 4, c9, x) 95 #define ICH_AP1R0 __AP1Rx(0) 96 #define ICH_AP1R1 __AP1Rx(1) 97 #define ICH_AP1R2 __AP1Rx(2) 98 #define ICH_AP1R3 __AP1Rx(3) 99 100 /* A32-to-A64 mappings used by VGIC save/restore */ 101 102 #define CPUIF_MAP(a32, a64) \ 103 static inline void write_ ## a64(u32 val) \ 104 { \ 105 write_sysreg(val, a32); \ 106 } \ 107 static inline u32 read_ ## a64(void) \ 108 { \ 109 return read_sysreg(a32); \ 110 } \ 111 112 #define CPUIF_MAP_LO_HI(a32lo, a32hi, a64) \ 113 static inline void write_ ## a64(u64 val) \ 114 { \ 115 write_sysreg(lower_32_bits(val), a32lo);\ 116 write_sysreg(upper_32_bits(val), a32hi);\ 117 } \ 118 static inline u64 read_ ## a64(void) \ 119 { \ 120 u64 val = read_sysreg(a32lo); \ 121 \ 122 val |= (u64)read_sysreg(a32hi) << 32; \ 123 \ 124 return val; \ 125 } 126 127 CPUIF_MAP(ICH_HCR, ICH_HCR_EL2) 128 CPUIF_MAP(ICH_VTR, ICH_VTR_EL2) 129 CPUIF_MAP(ICH_MISR, ICH_MISR_EL2) 130 CPUIF_MAP(ICH_EISR, ICH_EISR_EL2) 131 CPUIF_MAP(ICH_ELSR, ICH_ELSR_EL2) 132 CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2) 133 CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2) 134 CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2) 135 CPUIF_MAP(ICH_AP0R1, ICH_AP0R1_EL2) 136 CPUIF_MAP(ICH_AP0R0, ICH_AP0R0_EL2) 137 CPUIF_MAP(ICH_AP1R3, ICH_AP1R3_EL2) 138 CPUIF_MAP(ICH_AP1R2, ICH_AP1R2_EL2) 139 CPUIF_MAP(ICH_AP1R1, ICH_AP1R1_EL2) 140 CPUIF_MAP(ICH_AP1R0, ICH_AP1R0_EL2) 141 CPUIF_MAP(ICC_HSRE, ICC_SRE_EL2) 142 CPUIF_MAP(ICC_SRE, ICC_SRE_EL1) 143 144 CPUIF_MAP_LO_HI(ICH_LR15, ICH_LRC15, ICH_LR15_EL2) 145 CPUIF_MAP_LO_HI(ICH_LR14, ICH_LRC14, ICH_LR14_EL2) 146 CPUIF_MAP_LO_HI(ICH_LR13, ICH_LRC13, ICH_LR13_EL2) 147 CPUIF_MAP_LO_HI(ICH_LR12, ICH_LRC12, ICH_LR12_EL2) 148 CPUIF_MAP_LO_HI(ICH_LR11, ICH_LRC11, ICH_LR11_EL2) 149 CPUIF_MAP_LO_HI(ICH_LR10, ICH_LRC10, ICH_LR10_EL2) 150 CPUIF_MAP_LO_HI(ICH_LR9, ICH_LRC9, ICH_LR9_EL2) 151 CPUIF_MAP_LO_HI(ICH_LR8, ICH_LRC8, ICH_LR8_EL2) 152 CPUIF_MAP_LO_HI(ICH_LR7, ICH_LRC7, ICH_LR7_EL2) 153 CPUIF_MAP_LO_HI(ICH_LR6, ICH_LRC6, ICH_LR6_EL2) 154 CPUIF_MAP_LO_HI(ICH_LR5, ICH_LRC5, ICH_LR5_EL2) 155 CPUIF_MAP_LO_HI(ICH_LR4, ICH_LRC4, ICH_LR4_EL2) 156 CPUIF_MAP_LO_HI(ICH_LR3, ICH_LRC3, ICH_LR3_EL2) 157 CPUIF_MAP_LO_HI(ICH_LR2, ICH_LRC2, ICH_LR2_EL2) 158 CPUIF_MAP_LO_HI(ICH_LR1, ICH_LRC1, ICH_LR1_EL2) 159 CPUIF_MAP_LO_HI(ICH_LR0, ICH_LRC0, ICH_LR0_EL2) 160 161 #define read_gicreg(r) read_##r() 162 #define write_gicreg(v, r) write_##r(v) 163 164 /* Low-level accessors */ 165 166 static inline void gic_write_eoir(u32 irq) 167 { 168 write_sysreg(irq, ICC_EOIR1); 169 isb(); 170 } 171 172 static inline void gic_write_dir(u32 val) 173 { 174 write_sysreg(val, ICC_DIR); 175 isb(); 176 } 177 178 static inline u32 gic_read_iar(void) 179 { 180 u32 irqstat = read_sysreg(ICC_IAR1); 181 182 dsb(sy); 183 184 return irqstat; 185 } 186 187 static inline void gic_write_pmr(u32 val) 188 { 189 write_sysreg(val, ICC_PMR); 190 } 191 192 static inline void gic_write_ctlr(u32 val) 193 { 194 write_sysreg(val, ICC_CTLR); 195 isb(); 196 } 197 198 static inline void gic_write_grpen1(u32 val) 199 { 200 write_sysreg(val, ICC_IGRPEN1); 201 isb(); 202 } 203 204 static inline void gic_write_sgi1r(u64 val) 205 { 206 write_sysreg(val, ICC_SGI1R); 207 } 208 209 static inline u32 gic_read_sre(void) 210 { 211 return read_sysreg(ICC_SRE); 212 } 213 214 static inline void gic_write_sre(u32 val) 215 { 216 write_sysreg(val, ICC_SRE); 217 isb(); 218 } 219 220 static inline void gic_write_bpr1(u32 val) 221 { 222 write_sysreg(val, ICC_BPR1); 223 } 224 225 /* 226 * Even in 32bit systems that use LPAE, there is no guarantee that the I/O 227 * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't 228 * make much sense. 229 * Moreover, 64bit I/O emulation is extremely difficult to implement on 230 * AArch32, since the syndrome register doesn't provide any information for 231 * them. 232 * Consequently, the following IO helpers use 32bit accesses. 233 * 234 * There are only two registers that need 64bit accesses in this driver: 235 * - GICD_IROUTERn, contain the affinity values associated to each interrupt. 236 * The upper-word (aff3) will always be 0, so there is no need for a lock. 237 * - GICR_TYPER is an ID register and doesn't need atomicity. 238 */ 239 static inline void gic_write_irouter(u64 val, volatile void __iomem *addr) 240 { 241 writel_relaxed((u32)val, addr); 242 writel_relaxed((u32)(val >> 32), addr + 4); 243 } 244 245 static inline u64 gic_read_typer(const volatile void __iomem *addr) 246 { 247 u64 val; 248 249 val = readl_relaxed(addr); 250 val |= (u64)readl_relaxed(addr + 4) << 32; 251 return val; 252 } 253 254 #endif /* !__ASSEMBLY__ */ 255 #endif /* !__ASM_ARCH_GICV3_H */ 256