1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * arch/arm/include/asm/arch_gicv3.h 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 */ 7 #ifndef __ASM_ARCH_GICV3_H 8 #define __ASM_ARCH_GICV3_H 9 10 #ifndef __ASSEMBLY__ 11 12 #include <linux/io.h> 13 #include <linux/io-64-nonatomic-lo-hi.h> 14 #include <asm/barrier.h> 15 #include <asm/cacheflush.h> 16 #include <asm/cp15.h> 17 18 #define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1) 19 #define ICC_DIR __ACCESS_CP15(c12, 0, c11, 1) 20 #define ICC_IAR1 __ACCESS_CP15(c12, 0, c12, 0) 21 #define ICC_SGI1R __ACCESS_CP15_64(0, c12) 22 #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0) 23 #define ICC_CTLR __ACCESS_CP15(c12, 0, c12, 4) 24 #define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5) 25 #define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7) 26 #define ICC_BPR1 __ACCESS_CP15(c12, 0, c12, 3) 27 #define ICC_RPR __ACCESS_CP15(c12, 0, c11, 3) 28 29 #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) 30 #define ICC_AP0R0 __ICC_AP0Rx(0) 31 #define ICC_AP0R1 __ICC_AP0Rx(1) 32 #define ICC_AP0R2 __ICC_AP0Rx(2) 33 #define ICC_AP0R3 __ICC_AP0Rx(3) 34 35 #define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x) 36 #define ICC_AP1R0 __ICC_AP1Rx(0) 37 #define ICC_AP1R1 __ICC_AP1Rx(1) 38 #define ICC_AP1R2 __ICC_AP1Rx(2) 39 #define ICC_AP1R3 __ICC_AP1Rx(3) 40 41 #define ICC_HSRE __ACCESS_CP15(c12, 4, c9, 5) 42 43 #define ICH_VSEIR __ACCESS_CP15(c12, 4, c9, 4) 44 #define ICH_HCR __ACCESS_CP15(c12, 4, c11, 0) 45 #define ICH_VTR __ACCESS_CP15(c12, 4, c11, 1) 46 #define ICH_MISR __ACCESS_CP15(c12, 4, c11, 2) 47 #define ICH_EISR __ACCESS_CP15(c12, 4, c11, 3) 48 #define ICH_ELRSR __ACCESS_CP15(c12, 4, c11, 5) 49 #define ICH_VMCR __ACCESS_CP15(c12, 4, c11, 7) 50 51 #define __LR0(x) __ACCESS_CP15(c12, 4, c12, x) 52 #define __LR8(x) __ACCESS_CP15(c12, 4, c13, x) 53 54 #define ICH_LR0 __LR0(0) 55 #define ICH_LR1 __LR0(1) 56 #define ICH_LR2 __LR0(2) 57 #define ICH_LR3 __LR0(3) 58 #define ICH_LR4 __LR0(4) 59 #define ICH_LR5 __LR0(5) 60 #define ICH_LR6 __LR0(6) 61 #define ICH_LR7 __LR0(7) 62 #define ICH_LR8 __LR8(0) 63 #define ICH_LR9 __LR8(1) 64 #define ICH_LR10 __LR8(2) 65 #define ICH_LR11 __LR8(3) 66 #define ICH_LR12 __LR8(4) 67 #define ICH_LR13 __LR8(5) 68 #define ICH_LR14 __LR8(6) 69 #define ICH_LR15 __LR8(7) 70 71 /* LR top half */ 72 #define __LRC0(x) __ACCESS_CP15(c12, 4, c14, x) 73 #define __LRC8(x) __ACCESS_CP15(c12, 4, c15, x) 74 75 #define ICH_LRC0 __LRC0(0) 76 #define ICH_LRC1 __LRC0(1) 77 #define ICH_LRC2 __LRC0(2) 78 #define ICH_LRC3 __LRC0(3) 79 #define ICH_LRC4 __LRC0(4) 80 #define ICH_LRC5 __LRC0(5) 81 #define ICH_LRC6 __LRC0(6) 82 #define ICH_LRC7 __LRC0(7) 83 #define ICH_LRC8 __LRC8(0) 84 #define ICH_LRC9 __LRC8(1) 85 #define ICH_LRC10 __LRC8(2) 86 #define ICH_LRC11 __LRC8(3) 87 #define ICH_LRC12 __LRC8(4) 88 #define ICH_LRC13 __LRC8(5) 89 #define ICH_LRC14 __LRC8(6) 90 #define ICH_LRC15 __LRC8(7) 91 92 #define __ICH_AP0Rx(x) __ACCESS_CP15(c12, 4, c8, x) 93 #define ICH_AP0R0 __ICH_AP0Rx(0) 94 #define ICH_AP0R1 __ICH_AP0Rx(1) 95 #define ICH_AP0R2 __ICH_AP0Rx(2) 96 #define ICH_AP0R3 __ICH_AP0Rx(3) 97 98 #define __ICH_AP1Rx(x) __ACCESS_CP15(c12, 4, c9, x) 99 #define ICH_AP1R0 __ICH_AP1Rx(0) 100 #define ICH_AP1R1 __ICH_AP1Rx(1) 101 #define ICH_AP1R2 __ICH_AP1Rx(2) 102 #define ICH_AP1R3 __ICH_AP1Rx(3) 103 104 /* A32-to-A64 mappings used by VGIC save/restore */ 105 106 #define CPUIF_MAP(a32, a64) \ 107 static inline void write_ ## a64(u32 val) \ 108 { \ 109 write_sysreg(val, a32); \ 110 } \ 111 static inline u32 read_ ## a64(void) \ 112 { \ 113 return read_sysreg(a32); \ 114 } \ 115 116 #define CPUIF_MAP_LO_HI(a32lo, a32hi, a64) \ 117 static inline void write_ ## a64(u64 val) \ 118 { \ 119 write_sysreg(lower_32_bits(val), a32lo);\ 120 write_sysreg(upper_32_bits(val), a32hi);\ 121 } \ 122 static inline u64 read_ ## a64(void) \ 123 { \ 124 u64 val = read_sysreg(a32lo); \ 125 \ 126 val |= (u64)read_sysreg(a32hi) << 32; \ 127 \ 128 return val; \ 129 } 130 131 CPUIF_MAP(ICC_PMR, ICC_PMR_EL1) 132 CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1) 133 CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1) 134 CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1) 135 CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1) 136 CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1) 137 CPUIF_MAP(ICC_AP1R1, ICC_AP1R1_EL1) 138 CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1) 139 CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1) 140 141 CPUIF_MAP(ICH_HCR, ICH_HCR_EL2) 142 CPUIF_MAP(ICH_VTR, ICH_VTR_EL2) 143 CPUIF_MAP(ICH_MISR, ICH_MISR_EL2) 144 CPUIF_MAP(ICH_EISR, ICH_EISR_EL2) 145 CPUIF_MAP(ICH_ELRSR, ICH_ELRSR_EL2) 146 CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2) 147 CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2) 148 CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2) 149 CPUIF_MAP(ICH_AP0R1, ICH_AP0R1_EL2) 150 CPUIF_MAP(ICH_AP0R0, ICH_AP0R0_EL2) 151 CPUIF_MAP(ICH_AP1R3, ICH_AP1R3_EL2) 152 CPUIF_MAP(ICH_AP1R2, ICH_AP1R2_EL2) 153 CPUIF_MAP(ICH_AP1R1, ICH_AP1R1_EL2) 154 CPUIF_MAP(ICH_AP1R0, ICH_AP1R0_EL2) 155 CPUIF_MAP(ICC_HSRE, ICC_SRE_EL2) 156 CPUIF_MAP(ICC_SRE, ICC_SRE_EL1) 157 158 CPUIF_MAP_LO_HI(ICH_LR15, ICH_LRC15, ICH_LR15_EL2) 159 CPUIF_MAP_LO_HI(ICH_LR14, ICH_LRC14, ICH_LR14_EL2) 160 CPUIF_MAP_LO_HI(ICH_LR13, ICH_LRC13, ICH_LR13_EL2) 161 CPUIF_MAP_LO_HI(ICH_LR12, ICH_LRC12, ICH_LR12_EL2) 162 CPUIF_MAP_LO_HI(ICH_LR11, ICH_LRC11, ICH_LR11_EL2) 163 CPUIF_MAP_LO_HI(ICH_LR10, ICH_LRC10, ICH_LR10_EL2) 164 CPUIF_MAP_LO_HI(ICH_LR9, ICH_LRC9, ICH_LR9_EL2) 165 CPUIF_MAP_LO_HI(ICH_LR8, ICH_LRC8, ICH_LR8_EL2) 166 CPUIF_MAP_LO_HI(ICH_LR7, ICH_LRC7, ICH_LR7_EL2) 167 CPUIF_MAP_LO_HI(ICH_LR6, ICH_LRC6, ICH_LR6_EL2) 168 CPUIF_MAP_LO_HI(ICH_LR5, ICH_LRC5, ICH_LR5_EL2) 169 CPUIF_MAP_LO_HI(ICH_LR4, ICH_LRC4, ICH_LR4_EL2) 170 CPUIF_MAP_LO_HI(ICH_LR3, ICH_LRC3, ICH_LR3_EL2) 171 CPUIF_MAP_LO_HI(ICH_LR2, ICH_LRC2, ICH_LR2_EL2) 172 CPUIF_MAP_LO_HI(ICH_LR1, ICH_LRC1, ICH_LR1_EL2) 173 CPUIF_MAP_LO_HI(ICH_LR0, ICH_LRC0, ICH_LR0_EL2) 174 175 #define read_gicreg(r) read_##r() 176 #define write_gicreg(v, r) write_##r(v) 177 178 /* Low-level accessors */ 179 180 static inline void gic_write_eoir(u32 irq) 181 { 182 write_sysreg(irq, ICC_EOIR1); 183 isb(); 184 } 185 186 static inline void gic_write_dir(u32 val) 187 { 188 write_sysreg(val, ICC_DIR); 189 isb(); 190 } 191 192 static inline u32 gic_read_iar(void) 193 { 194 u32 irqstat = read_sysreg(ICC_IAR1); 195 196 dsb(sy); 197 198 return irqstat; 199 } 200 201 static inline void gic_write_ctlr(u32 val) 202 { 203 write_sysreg(val, ICC_CTLR); 204 isb(); 205 } 206 207 static inline u32 gic_read_ctlr(void) 208 { 209 return read_sysreg(ICC_CTLR); 210 } 211 212 static inline void gic_write_grpen1(u32 val) 213 { 214 write_sysreg(val, ICC_IGRPEN1); 215 isb(); 216 } 217 218 static inline void gic_write_sgi1r(u64 val) 219 { 220 write_sysreg(val, ICC_SGI1R); 221 } 222 223 static inline u32 gic_read_sre(void) 224 { 225 return read_sysreg(ICC_SRE); 226 } 227 228 static inline void gic_write_sre(u32 val) 229 { 230 write_sysreg(val, ICC_SRE); 231 isb(); 232 } 233 234 static inline void gic_write_bpr1(u32 val) 235 { 236 write_sysreg(val, ICC_BPR1); 237 } 238 239 static inline u32 gic_read_pmr(void) 240 { 241 return read_sysreg(ICC_PMR); 242 } 243 244 static inline void gic_write_pmr(u32 val) 245 { 246 write_sysreg(val, ICC_PMR); 247 } 248 249 static inline u32 gic_read_rpr(void) 250 { 251 return read_sysreg(ICC_RPR); 252 } 253 254 /* 255 * Even in 32bit systems that use LPAE, there is no guarantee that the I/O 256 * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't 257 * make much sense. 258 * Moreover, 64bit I/O emulation is extremely difficult to implement on 259 * AArch32, since the syndrome register doesn't provide any information for 260 * them. 261 * Consequently, the following IO helpers use 32bit accesses. 262 */ 263 static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr) 264 { 265 writel_relaxed((u32)val, addr); 266 writel_relaxed((u32)(val >> 32), addr + 4); 267 } 268 269 static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr) 270 { 271 u64 val; 272 273 val = readl_relaxed(addr); 274 val |= (u64)readl_relaxed(addr + 4) << 32; 275 return val; 276 } 277 278 #define gic_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l)) 279 280 /* 281 * GICD_IROUTERn, contain the affinity values associated to each interrupt. 282 * The upper-word (aff3) will always be 0, so there is no need for a lock. 283 */ 284 #define gic_write_irouter(v, c) __gic_writeq_nonatomic(v, c) 285 286 /* 287 * GICR_TYPER is an ID register and doesn't need atomicity. 288 */ 289 #define gic_read_typer(c) __gic_readq_nonatomic(c) 290 291 /* 292 * GITS_BASER - hi and lo bits may be accessed independently. 293 */ 294 #define gits_read_baser(c) __gic_readq_nonatomic(c) 295 #define gits_write_baser(v, c) __gic_writeq_nonatomic(v, c) 296 297 /* 298 * GICR_PENDBASER and GICR_PROPBASE are changed with LPIs disabled, so they 299 * won't be being used during any updates and can be changed non-atomically 300 */ 301 #define gicr_read_propbaser(c) __gic_readq_nonatomic(c) 302 #define gicr_write_propbaser(v, c) __gic_writeq_nonatomic(v, c) 303 #define gicr_read_pendbaser(c) __gic_readq_nonatomic(c) 304 #define gicr_write_pendbaser(v, c) __gic_writeq_nonatomic(v, c) 305 306 /* 307 * GICR_xLPIR - only the lower bits are significant 308 */ 309 #define gic_read_lpir(c) readl_relaxed(c) 310 #define gic_write_lpir(v, c) writel_relaxed(lower_32_bits(v), c) 311 312 /* 313 * GITS_TYPER is an ID register and doesn't need atomicity. 314 */ 315 #define gits_read_typer(c) __gic_readq_nonatomic(c) 316 317 /* 318 * GITS_CBASER - hi and lo bits may be accessed independently. 319 */ 320 #define gits_read_cbaser(c) __gic_readq_nonatomic(c) 321 #define gits_write_cbaser(v, c) __gic_writeq_nonatomic(v, c) 322 323 /* 324 * GITS_CWRITER - hi and lo bits may be accessed independently. 325 */ 326 #define gits_write_cwriter(v, c) __gic_writeq_nonatomic(v, c) 327 328 /* 329 * GICR_VPROPBASER - hi and lo bits may be accessed independently. 330 */ 331 #define gicr_read_vpropbaser(c) __gic_readq_nonatomic(c) 332 #define gicr_write_vpropbaser(v, c) __gic_writeq_nonatomic(v, c) 333 334 /* 335 * GICR_VPENDBASER - the Valid bit must be cleared before changing 336 * anything else. 337 */ 338 static inline void gicr_write_vpendbaser(u64 val, void __iomem *addr) 339 { 340 u32 tmp; 341 342 tmp = readl_relaxed(addr + 4); 343 if (tmp & (GICR_VPENDBASER_Valid >> 32)) { 344 tmp &= ~(GICR_VPENDBASER_Valid >> 32); 345 writel_relaxed(tmp, addr + 4); 346 } 347 348 /* 349 * Use the fact that __gic_writeq_nonatomic writes the second 350 * half of the 64bit quantity after the first. 351 */ 352 __gic_writeq_nonatomic(val, addr); 353 } 354 355 #define gicr_read_vpendbaser(c) __gic_readq_nonatomic(c) 356 357 static inline bool gic_prio_masking_enabled(void) 358 { 359 return false; 360 } 361 362 static inline void gic_pmr_mask_irqs(void) 363 { 364 /* Should not get called. */ 365 WARN_ON_ONCE(true); 366 } 367 368 static inline void gic_arch_enable_irqs(void) 369 { 370 /* Should not get called. */ 371 WARN_ON_ONCE(true); 372 } 373 374 #endif /* !__ASSEMBLY__ */ 375 #endif /* !__ASM_ARCH_GICV3_H */ 376