1 /* 2 * arch/arm/include/asm/arch_gicv3.h 3 * 4 * Copyright (C) 2015 ARM Ltd. 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 #ifndef __ASM_ARCH_GICV3_H 19 #define __ASM_ARCH_GICV3_H 20 21 #ifndef __ASSEMBLY__ 22 23 #include <linux/io.h> 24 #include <asm/barrier.h> 25 26 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) p15, Op1, %0, CRn, CRm, Op2 27 #define __ACCESS_CP15_64(Op1, CRm) p15, Op1, %Q0, %R0, CRm 28 29 #define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1) 30 #define ICC_DIR __ACCESS_CP15(c12, 0, c11, 1) 31 #define ICC_IAR1 __ACCESS_CP15(c12, 0, c12, 0) 32 #define ICC_SGI1R __ACCESS_CP15_64(0, c12) 33 #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0) 34 #define ICC_CTLR __ACCESS_CP15(c12, 0, c12, 4) 35 #define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5) 36 #define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7) 37 38 #define ICC_HSRE __ACCESS_CP15(c12, 4, c9, 5) 39 40 #define ICH_VSEIR __ACCESS_CP15(c12, 4, c9, 4) 41 #define ICH_HCR __ACCESS_CP15(c12, 4, c11, 0) 42 #define ICH_VTR __ACCESS_CP15(c12, 4, c11, 1) 43 #define ICH_MISR __ACCESS_CP15(c12, 4, c11, 2) 44 #define ICH_EISR __ACCESS_CP15(c12, 4, c11, 3) 45 #define ICH_ELSR __ACCESS_CP15(c12, 4, c11, 5) 46 #define ICH_VMCR __ACCESS_CP15(c12, 4, c11, 7) 47 48 #define __LR0(x) __ACCESS_CP15(c12, 4, c12, x) 49 #define __LR8(x) __ACCESS_CP15(c12, 4, c13, x) 50 51 #define ICH_LR0 __LR0(0) 52 #define ICH_LR1 __LR0(1) 53 #define ICH_LR2 __LR0(2) 54 #define ICH_LR3 __LR0(3) 55 #define ICH_LR4 __LR0(4) 56 #define ICH_LR5 __LR0(5) 57 #define ICH_LR6 __LR0(6) 58 #define ICH_LR7 __LR0(7) 59 #define ICH_LR8 __LR8(0) 60 #define ICH_LR9 __LR8(1) 61 #define ICH_LR10 __LR8(2) 62 #define ICH_LR11 __LR8(3) 63 #define ICH_LR12 __LR8(4) 64 #define ICH_LR13 __LR8(5) 65 #define ICH_LR14 __LR8(6) 66 #define ICH_LR15 __LR8(7) 67 68 /* LR top half */ 69 #define __LRC0(x) __ACCESS_CP15(c12, 4, c14, x) 70 #define __LRC8(x) __ACCESS_CP15(c12, 4, c15, x) 71 72 #define ICH_LRC0 __LRC0(0) 73 #define ICH_LRC1 __LRC0(1) 74 #define ICH_LRC2 __LRC0(2) 75 #define ICH_LRC3 __LRC0(3) 76 #define ICH_LRC4 __LRC0(4) 77 #define ICH_LRC5 __LRC0(5) 78 #define ICH_LRC6 __LRC0(6) 79 #define ICH_LRC7 __LRC0(7) 80 #define ICH_LRC8 __LRC8(0) 81 #define ICH_LRC9 __LRC8(1) 82 #define ICH_LRC10 __LRC8(2) 83 #define ICH_LRC11 __LRC8(3) 84 #define ICH_LRC12 __LRC8(4) 85 #define ICH_LRC13 __LRC8(5) 86 #define ICH_LRC14 __LRC8(6) 87 #define ICH_LRC15 __LRC8(7) 88 89 #define __AP0Rx(x) __ACCESS_CP15(c12, 4, c8, x) 90 #define ICH_AP0R0 __AP0Rx(0) 91 #define ICH_AP0R1 __AP0Rx(1) 92 #define ICH_AP0R2 __AP0Rx(2) 93 #define ICH_AP0R3 __AP0Rx(3) 94 95 #define __AP1Rx(x) __ACCESS_CP15(c12, 4, c9, x) 96 #define ICH_AP1R0 __AP1Rx(0) 97 #define ICH_AP1R1 __AP1Rx(1) 98 #define ICH_AP1R2 __AP1Rx(2) 99 #define ICH_AP1R3 __AP1Rx(3) 100 101 /* Low-level accessors */ 102 103 static inline void gic_write_eoir(u32 irq) 104 { 105 asm volatile("mcr " __stringify(ICC_EOIR1) : : "r" (irq)); 106 isb(); 107 } 108 109 static inline void gic_write_dir(u32 val) 110 { 111 asm volatile("mcr " __stringify(ICC_DIR) : : "r" (val)); 112 isb(); 113 } 114 115 static inline u32 gic_read_iar(void) 116 { 117 u32 irqstat; 118 119 asm volatile("mrc " __stringify(ICC_IAR1) : "=r" (irqstat)); 120 return irqstat; 121 } 122 123 static inline void gic_write_pmr(u32 val) 124 { 125 asm volatile("mcr " __stringify(ICC_PMR) : : "r" (val)); 126 } 127 128 static inline void gic_write_ctlr(u32 val) 129 { 130 asm volatile("mcr " __stringify(ICC_CTLR) : : "r" (val)); 131 isb(); 132 } 133 134 static inline void gic_write_grpen1(u32 val) 135 { 136 asm volatile("mcr " __stringify(ICC_IGRPEN1) : : "r" (val)); 137 isb(); 138 } 139 140 static inline void gic_write_sgi1r(u64 val) 141 { 142 asm volatile("mcrr " __stringify(ICC_SGI1R) : : "r" (val)); 143 } 144 145 static inline u32 gic_read_sre(void) 146 { 147 u32 val; 148 149 asm volatile("mrc " __stringify(ICC_SRE) : "=r" (val)); 150 return val; 151 } 152 153 static inline void gic_write_sre(u32 val) 154 { 155 asm volatile("mcr " __stringify(ICC_SRE) : : "r" (val)); 156 isb(); 157 } 158 159 /* 160 * Even in 32bit systems that use LPAE, there is no guarantee that the I/O 161 * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't 162 * make much sense. 163 * Moreover, 64bit I/O emulation is extremely difficult to implement on 164 * AArch32, since the syndrome register doesn't provide any information for 165 * them. 166 * Consequently, the following IO helpers use 32bit accesses. 167 * 168 * There are only two registers that need 64bit accesses in this driver: 169 * - GICD_IROUTERn, contain the affinity values associated to each interrupt. 170 * The upper-word (aff3) will always be 0, so there is no need for a lock. 171 * - GICR_TYPER is an ID register and doesn't need atomicity. 172 */ 173 static inline void gic_write_irouter(u64 val, volatile void __iomem *addr) 174 { 175 writel_relaxed((u32)val, addr); 176 writel_relaxed((u32)(val >> 32), addr + 4); 177 } 178 179 static inline u64 gic_read_typer(const volatile void __iomem *addr) 180 { 181 u64 val; 182 183 val = readl_relaxed(addr); 184 val |= (u64)readl_relaxed(addr + 4) << 32; 185 return val; 186 } 187 188 #endif /* !__ASSEMBLY__ */ 189 #endif /* !__ASM_ARCH_GICV3_H */ 190