1d5cd50d3SJean-Philippe Brucker /* 2d5cd50d3SJean-Philippe Brucker * arch/arm/include/asm/arch_gicv3.h 3d5cd50d3SJean-Philippe Brucker * 4d5cd50d3SJean-Philippe Brucker * Copyright (C) 2015 ARM Ltd. 5d5cd50d3SJean-Philippe Brucker * 6d5cd50d3SJean-Philippe Brucker * This program is free software: you can redistribute it and/or modify 7d5cd50d3SJean-Philippe Brucker * it under the terms of the GNU General Public License version 2 as 8d5cd50d3SJean-Philippe Brucker * published by the Free Software Foundation. 9d5cd50d3SJean-Philippe Brucker * 10d5cd50d3SJean-Philippe Brucker * This program is distributed in the hope that it will be useful, 11d5cd50d3SJean-Philippe Brucker * but WITHOUT ANY WARRANTY; without even the implied warranty of 12d5cd50d3SJean-Philippe Brucker * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13d5cd50d3SJean-Philippe Brucker * GNU General Public License for more details. 14d5cd50d3SJean-Philippe Brucker * 15d5cd50d3SJean-Philippe Brucker * You should have received a copy of the GNU General Public License 16d5cd50d3SJean-Philippe Brucker * along with this program. If not, see <http://www.gnu.org/licenses/>. 17d5cd50d3SJean-Philippe Brucker */ 18d5cd50d3SJean-Philippe Brucker #ifndef __ASM_ARCH_GICV3_H 19d5cd50d3SJean-Philippe Brucker #define __ASM_ARCH_GICV3_H 20d5cd50d3SJean-Philippe Brucker 21d5cd50d3SJean-Philippe Brucker #ifndef __ASSEMBLY__ 22d5cd50d3SJean-Philippe Brucker 23d5cd50d3SJean-Philippe Brucker #include <linux/io.h> 248e31ed9cSMarc Zyngier #include <asm/barrier.h> 2592116b80SVladimir Murzin #include <asm/cacheflush.h> 264f254638SVladimir Murzin #include <asm/cp15.h> 27d5cd50d3SJean-Philippe Brucker 28d5cd50d3SJean-Philippe Brucker #define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1) 29d5cd50d3SJean-Philippe Brucker #define ICC_DIR __ACCESS_CP15(c12, 0, c11, 1) 30d5cd50d3SJean-Philippe Brucker #define ICC_IAR1 __ACCESS_CP15(c12, 0, c12, 0) 31d5cd50d3SJean-Philippe Brucker #define ICC_SGI1R __ACCESS_CP15_64(0, c12) 32d5cd50d3SJean-Philippe Brucker #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0) 33d5cd50d3SJean-Philippe Brucker #define ICC_CTLR __ACCESS_CP15(c12, 0, c12, 4) 34d5cd50d3SJean-Philippe Brucker #define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5) 35d5cd50d3SJean-Philippe Brucker #define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7) 3691ef8442SDaniel Thompson #define ICC_BPR1 __ACCESS_CP15(c12, 0, c12, 3) 37d5cd50d3SJean-Philippe Brucker 38d6062a6dSMarc Zyngier #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) 39d6062a6dSMarc Zyngier #define ICC_AP0R0 __ICC_AP0Rx(0) 40d6062a6dSMarc Zyngier #define ICC_AP0R1 __ICC_AP0Rx(1) 41d6062a6dSMarc Zyngier #define ICC_AP0R2 __ICC_AP0Rx(2) 42d6062a6dSMarc Zyngier #define ICC_AP0R3 __ICC_AP0Rx(3) 43d6062a6dSMarc Zyngier 44d6062a6dSMarc Zyngier #define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x) 45d6062a6dSMarc Zyngier #define ICC_AP1R0 __ICC_AP1Rx(0) 46d6062a6dSMarc Zyngier #define ICC_AP1R1 __ICC_AP1Rx(1) 47d6062a6dSMarc Zyngier #define ICC_AP1R2 __ICC_AP1Rx(2) 48d6062a6dSMarc Zyngier #define ICC_AP1R3 __ICC_AP1Rx(3) 49d6062a6dSMarc Zyngier 50d5cd50d3SJean-Philippe Brucker #define ICC_HSRE __ACCESS_CP15(c12, 4, c9, 5) 51d5cd50d3SJean-Philippe Brucker 52d5cd50d3SJean-Philippe Brucker #define ICH_VSEIR __ACCESS_CP15(c12, 4, c9, 4) 53d5cd50d3SJean-Philippe Brucker #define ICH_HCR __ACCESS_CP15(c12, 4, c11, 0) 54d5cd50d3SJean-Philippe Brucker #define ICH_VTR __ACCESS_CP15(c12, 4, c11, 1) 55d5cd50d3SJean-Philippe Brucker #define ICH_MISR __ACCESS_CP15(c12, 4, c11, 2) 56d5cd50d3SJean-Philippe Brucker #define ICH_EISR __ACCESS_CP15(c12, 4, c11, 3) 57d5cd50d3SJean-Philippe Brucker #define ICH_ELSR __ACCESS_CP15(c12, 4, c11, 5) 58d5cd50d3SJean-Philippe Brucker #define ICH_VMCR __ACCESS_CP15(c12, 4, c11, 7) 59d5cd50d3SJean-Philippe Brucker 60d5cd50d3SJean-Philippe Brucker #define __LR0(x) __ACCESS_CP15(c12, 4, c12, x) 61d5cd50d3SJean-Philippe Brucker #define __LR8(x) __ACCESS_CP15(c12, 4, c13, x) 62d5cd50d3SJean-Philippe Brucker 63d5cd50d3SJean-Philippe Brucker #define ICH_LR0 __LR0(0) 64d5cd50d3SJean-Philippe Brucker #define ICH_LR1 __LR0(1) 65d5cd50d3SJean-Philippe Brucker #define ICH_LR2 __LR0(2) 66d5cd50d3SJean-Philippe Brucker #define ICH_LR3 __LR0(3) 67d5cd50d3SJean-Philippe Brucker #define ICH_LR4 __LR0(4) 68d5cd50d3SJean-Philippe Brucker #define ICH_LR5 __LR0(5) 69d5cd50d3SJean-Philippe Brucker #define ICH_LR6 __LR0(6) 70d5cd50d3SJean-Philippe Brucker #define ICH_LR7 __LR0(7) 71d5cd50d3SJean-Philippe Brucker #define ICH_LR8 __LR8(0) 72d5cd50d3SJean-Philippe Brucker #define ICH_LR9 __LR8(1) 73d5cd50d3SJean-Philippe Brucker #define ICH_LR10 __LR8(2) 74d5cd50d3SJean-Philippe Brucker #define ICH_LR11 __LR8(3) 75d5cd50d3SJean-Philippe Brucker #define ICH_LR12 __LR8(4) 76d5cd50d3SJean-Philippe Brucker #define ICH_LR13 __LR8(5) 77d5cd50d3SJean-Philippe Brucker #define ICH_LR14 __LR8(6) 78d5cd50d3SJean-Philippe Brucker #define ICH_LR15 __LR8(7) 79d5cd50d3SJean-Philippe Brucker 80d5cd50d3SJean-Philippe Brucker /* LR top half */ 81d5cd50d3SJean-Philippe Brucker #define __LRC0(x) __ACCESS_CP15(c12, 4, c14, x) 82d5cd50d3SJean-Philippe Brucker #define __LRC8(x) __ACCESS_CP15(c12, 4, c15, x) 83d5cd50d3SJean-Philippe Brucker 84d5cd50d3SJean-Philippe Brucker #define ICH_LRC0 __LRC0(0) 85d5cd50d3SJean-Philippe Brucker #define ICH_LRC1 __LRC0(1) 86d5cd50d3SJean-Philippe Brucker #define ICH_LRC2 __LRC0(2) 87d5cd50d3SJean-Philippe Brucker #define ICH_LRC3 __LRC0(3) 88d5cd50d3SJean-Philippe Brucker #define ICH_LRC4 __LRC0(4) 89d5cd50d3SJean-Philippe Brucker #define ICH_LRC5 __LRC0(5) 90d5cd50d3SJean-Philippe Brucker #define ICH_LRC6 __LRC0(6) 91d5cd50d3SJean-Philippe Brucker #define ICH_LRC7 __LRC0(7) 92d5cd50d3SJean-Philippe Brucker #define ICH_LRC8 __LRC8(0) 93d5cd50d3SJean-Philippe Brucker #define ICH_LRC9 __LRC8(1) 94d5cd50d3SJean-Philippe Brucker #define ICH_LRC10 __LRC8(2) 95d5cd50d3SJean-Philippe Brucker #define ICH_LRC11 __LRC8(3) 96d5cd50d3SJean-Philippe Brucker #define ICH_LRC12 __LRC8(4) 97d5cd50d3SJean-Philippe Brucker #define ICH_LRC13 __LRC8(5) 98d5cd50d3SJean-Philippe Brucker #define ICH_LRC14 __LRC8(6) 99d5cd50d3SJean-Philippe Brucker #define ICH_LRC15 __LRC8(7) 100d5cd50d3SJean-Philippe Brucker 101d6062a6dSMarc Zyngier #define __ICH_AP0Rx(x) __ACCESS_CP15(c12, 4, c8, x) 102d6062a6dSMarc Zyngier #define ICH_AP0R0 __ICH_AP0Rx(0) 103d6062a6dSMarc Zyngier #define ICH_AP0R1 __ICH_AP0Rx(1) 104d6062a6dSMarc Zyngier #define ICH_AP0R2 __ICH_AP0Rx(2) 105d6062a6dSMarc Zyngier #define ICH_AP0R3 __ICH_AP0Rx(3) 106d5cd50d3SJean-Philippe Brucker 107d6062a6dSMarc Zyngier #define __ICH_AP1Rx(x) __ACCESS_CP15(c12, 4, c9, x) 108d6062a6dSMarc Zyngier #define ICH_AP1R0 __ICH_AP1Rx(0) 109d6062a6dSMarc Zyngier #define ICH_AP1R1 __ICH_AP1Rx(1) 110d6062a6dSMarc Zyngier #define ICH_AP1R2 __ICH_AP1Rx(2) 111d6062a6dSMarc Zyngier #define ICH_AP1R3 __ICH_AP1Rx(3) 112d5cd50d3SJean-Philippe Brucker 113a078bedfSVladimir Murzin /* A32-to-A64 mappings used by VGIC save/restore */ 114a078bedfSVladimir Murzin 115a078bedfSVladimir Murzin #define CPUIF_MAP(a32, a64) \ 116a078bedfSVladimir Murzin static inline void write_ ## a64(u32 val) \ 117a078bedfSVladimir Murzin { \ 118a078bedfSVladimir Murzin write_sysreg(val, a32); \ 119a078bedfSVladimir Murzin } \ 120a078bedfSVladimir Murzin static inline u32 read_ ## a64(void) \ 121a078bedfSVladimir Murzin { \ 122a078bedfSVladimir Murzin return read_sysreg(a32); \ 123a078bedfSVladimir Murzin } \ 124a078bedfSVladimir Murzin 125a078bedfSVladimir Murzin #define CPUIF_MAP_LO_HI(a32lo, a32hi, a64) \ 126a078bedfSVladimir Murzin static inline void write_ ## a64(u64 val) \ 127a078bedfSVladimir Murzin { \ 128a078bedfSVladimir Murzin write_sysreg(lower_32_bits(val), a32lo);\ 129a078bedfSVladimir Murzin write_sysreg(upper_32_bits(val), a32hi);\ 130a078bedfSVladimir Murzin } \ 131a078bedfSVladimir Murzin static inline u64 read_ ## a64(void) \ 132a078bedfSVladimir Murzin { \ 133a078bedfSVladimir Murzin u64 val = read_sysreg(a32lo); \ 134a078bedfSVladimir Murzin \ 135a078bedfSVladimir Murzin val |= (u64)read_sysreg(a32hi) << 32; \ 136a078bedfSVladimir Murzin \ 137a078bedfSVladimir Murzin return val; \ 138a078bedfSVladimir Murzin } 139a078bedfSVladimir Murzin 14033625282SMarc Zyngier CPUIF_MAP(ICC_PMR, ICC_PMR_EL1) 141d6062a6dSMarc Zyngier CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1) 142d6062a6dSMarc Zyngier CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1) 143d6062a6dSMarc Zyngier CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1) 144d6062a6dSMarc Zyngier CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1) 145d6062a6dSMarc Zyngier CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1) 146d6062a6dSMarc Zyngier CPUIF_MAP(ICC_AP1R1, ICC_AP1R1_EL1) 147d6062a6dSMarc Zyngier CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1) 148d6062a6dSMarc Zyngier CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1) 149d6062a6dSMarc Zyngier 150a078bedfSVladimir Murzin CPUIF_MAP(ICH_HCR, ICH_HCR_EL2) 151a078bedfSVladimir Murzin CPUIF_MAP(ICH_VTR, ICH_VTR_EL2) 152a078bedfSVladimir Murzin CPUIF_MAP(ICH_MISR, ICH_MISR_EL2) 153a078bedfSVladimir Murzin CPUIF_MAP(ICH_EISR, ICH_EISR_EL2) 154a078bedfSVladimir Murzin CPUIF_MAP(ICH_ELSR, ICH_ELSR_EL2) 155a078bedfSVladimir Murzin CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2) 156a078bedfSVladimir Murzin CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2) 157a078bedfSVladimir Murzin CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2) 158a078bedfSVladimir Murzin CPUIF_MAP(ICH_AP0R1, ICH_AP0R1_EL2) 159a078bedfSVladimir Murzin CPUIF_MAP(ICH_AP0R0, ICH_AP0R0_EL2) 160a078bedfSVladimir Murzin CPUIF_MAP(ICH_AP1R3, ICH_AP1R3_EL2) 161a078bedfSVladimir Murzin CPUIF_MAP(ICH_AP1R2, ICH_AP1R2_EL2) 162a078bedfSVladimir Murzin CPUIF_MAP(ICH_AP1R1, ICH_AP1R1_EL2) 163a078bedfSVladimir Murzin CPUIF_MAP(ICH_AP1R0, ICH_AP1R0_EL2) 164a078bedfSVladimir Murzin CPUIF_MAP(ICC_HSRE, ICC_SRE_EL2) 165a078bedfSVladimir Murzin CPUIF_MAP(ICC_SRE, ICC_SRE_EL1) 166a078bedfSVladimir Murzin 167a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR15, ICH_LRC15, ICH_LR15_EL2) 168a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR14, ICH_LRC14, ICH_LR14_EL2) 169a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR13, ICH_LRC13, ICH_LR13_EL2) 170a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR12, ICH_LRC12, ICH_LR12_EL2) 171a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR11, ICH_LRC11, ICH_LR11_EL2) 172a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR10, ICH_LRC10, ICH_LR10_EL2) 173a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR9, ICH_LRC9, ICH_LR9_EL2) 174a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR8, ICH_LRC8, ICH_LR8_EL2) 175a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR7, ICH_LRC7, ICH_LR7_EL2) 176a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR6, ICH_LRC6, ICH_LR6_EL2) 177a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR5, ICH_LRC5, ICH_LR5_EL2) 178a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR4, ICH_LRC4, ICH_LR4_EL2) 179a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR3, ICH_LRC3, ICH_LR3_EL2) 180a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR2, ICH_LRC2, ICH_LR2_EL2) 181a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR1, ICH_LRC1, ICH_LR1_EL2) 182a078bedfSVladimir Murzin CPUIF_MAP_LO_HI(ICH_LR0, ICH_LRC0, ICH_LR0_EL2) 183a078bedfSVladimir Murzin 184a078bedfSVladimir Murzin #define read_gicreg(r) read_##r() 185a078bedfSVladimir Murzin #define write_gicreg(v, r) write_##r(v) 186a078bedfSVladimir Murzin 187d5cd50d3SJean-Philippe Brucker /* Low-level accessors */ 188d5cd50d3SJean-Philippe Brucker 189d5cd50d3SJean-Philippe Brucker static inline void gic_write_eoir(u32 irq) 190d5cd50d3SJean-Philippe Brucker { 1914f254638SVladimir Murzin write_sysreg(irq, ICC_EOIR1); 192d5cd50d3SJean-Philippe Brucker isb(); 193d5cd50d3SJean-Philippe Brucker } 194d5cd50d3SJean-Philippe Brucker 195d5cd50d3SJean-Philippe Brucker static inline void gic_write_dir(u32 val) 196d5cd50d3SJean-Philippe Brucker { 1974f254638SVladimir Murzin write_sysreg(val, ICC_DIR); 198d5cd50d3SJean-Philippe Brucker isb(); 199d5cd50d3SJean-Philippe Brucker } 200d5cd50d3SJean-Philippe Brucker 201d5cd50d3SJean-Philippe Brucker static inline u32 gic_read_iar(void) 202d5cd50d3SJean-Philippe Brucker { 2034f254638SVladimir Murzin u32 irqstat = read_sysreg(ICC_IAR1); 204d5cd50d3SJean-Philippe Brucker 2058f318526SMarc Zyngier dsb(sy); 2064f254638SVladimir Murzin 207d5cd50d3SJean-Philippe Brucker return irqstat; 208d5cd50d3SJean-Philippe Brucker } 209d5cd50d3SJean-Philippe Brucker 210d5cd50d3SJean-Philippe Brucker static inline void gic_write_ctlr(u32 val) 211d5cd50d3SJean-Philippe Brucker { 2124f254638SVladimir Murzin write_sysreg(val, ICC_CTLR); 213d5cd50d3SJean-Philippe Brucker isb(); 214d5cd50d3SJean-Philippe Brucker } 215d5cd50d3SJean-Philippe Brucker 216eda0d04aSShanker Donthineni static inline u32 gic_read_ctlr(void) 217eda0d04aSShanker Donthineni { 218eda0d04aSShanker Donthineni return read_sysreg(ICC_CTLR); 219eda0d04aSShanker Donthineni } 220eda0d04aSShanker Donthineni 221d5cd50d3SJean-Philippe Brucker static inline void gic_write_grpen1(u32 val) 222d5cd50d3SJean-Philippe Brucker { 2234f254638SVladimir Murzin write_sysreg(val, ICC_IGRPEN1); 224d5cd50d3SJean-Philippe Brucker isb(); 225d5cd50d3SJean-Philippe Brucker } 226d5cd50d3SJean-Philippe Brucker 227d5cd50d3SJean-Philippe Brucker static inline void gic_write_sgi1r(u64 val) 228d5cd50d3SJean-Philippe Brucker { 2294f254638SVladimir Murzin write_sysreg(val, ICC_SGI1R); 230d5cd50d3SJean-Philippe Brucker } 231d5cd50d3SJean-Philippe Brucker 232d5cd50d3SJean-Philippe Brucker static inline u32 gic_read_sre(void) 233d5cd50d3SJean-Philippe Brucker { 2344f254638SVladimir Murzin return read_sysreg(ICC_SRE); 235d5cd50d3SJean-Philippe Brucker } 236d5cd50d3SJean-Philippe Brucker 237d5cd50d3SJean-Philippe Brucker static inline void gic_write_sre(u32 val) 238d5cd50d3SJean-Philippe Brucker { 2394f254638SVladimir Murzin write_sysreg(val, ICC_SRE); 240d5cd50d3SJean-Philippe Brucker isb(); 241d5cd50d3SJean-Philippe Brucker } 242d5cd50d3SJean-Philippe Brucker 24391ef8442SDaniel Thompson static inline void gic_write_bpr1(u32 val) 24491ef8442SDaniel Thompson { 2453d9cd95fSMarc Zyngier write_sysreg(val, ICC_BPR1); 24691ef8442SDaniel Thompson } 24791ef8442SDaniel Thompson 248d5cd50d3SJean-Philippe Brucker /* 249d5cd50d3SJean-Philippe Brucker * Even in 32bit systems that use LPAE, there is no guarantee that the I/O 250d5cd50d3SJean-Philippe Brucker * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't 251d5cd50d3SJean-Philippe Brucker * make much sense. 252d5cd50d3SJean-Philippe Brucker * Moreover, 64bit I/O emulation is extremely difficult to implement on 253d5cd50d3SJean-Philippe Brucker * AArch32, since the syndrome register doesn't provide any information for 254d5cd50d3SJean-Philippe Brucker * them. 255d5cd50d3SJean-Philippe Brucker * Consequently, the following IO helpers use 32bit accesses. 256d5cd50d3SJean-Philippe Brucker */ 25792116b80SVladimir Murzin static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr) 258d5cd50d3SJean-Philippe Brucker { 259d5cd50d3SJean-Philippe Brucker writel_relaxed((u32)val, addr); 260d5cd50d3SJean-Philippe Brucker writel_relaxed((u32)(val >> 32), addr + 4); 261d5cd50d3SJean-Philippe Brucker } 262d5cd50d3SJean-Philippe Brucker 26392116b80SVladimir Murzin static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr) 264d5cd50d3SJean-Philippe Brucker { 265d5cd50d3SJean-Philippe Brucker u64 val; 266d5cd50d3SJean-Philippe Brucker 267d5cd50d3SJean-Philippe Brucker val = readl_relaxed(addr); 268d5cd50d3SJean-Philippe Brucker val |= (u64)readl_relaxed(addr + 4) << 32; 269d5cd50d3SJean-Philippe Brucker return val; 270d5cd50d3SJean-Philippe Brucker } 271d5cd50d3SJean-Philippe Brucker 27292116b80SVladimir Murzin #define gic_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l)) 27392116b80SVladimir Murzin 27492116b80SVladimir Murzin /* 27592116b80SVladimir Murzin * GICD_IROUTERn, contain the affinity values associated to each interrupt. 27692116b80SVladimir Murzin * The upper-word (aff3) will always be 0, so there is no need for a lock. 27792116b80SVladimir Murzin */ 27892116b80SVladimir Murzin #define gic_write_irouter(v, c) __gic_writeq_nonatomic(v, c) 27992116b80SVladimir Murzin 28092116b80SVladimir Murzin /* 28192116b80SVladimir Murzin * GICR_TYPER is an ID register and doesn't need atomicity. 28292116b80SVladimir Murzin */ 28392116b80SVladimir Murzin #define gic_read_typer(c) __gic_readq_nonatomic(c) 28492116b80SVladimir Murzin 28592116b80SVladimir Murzin /* 28692116b80SVladimir Murzin * GITS_BASER - hi and lo bits may be accessed independently. 28792116b80SVladimir Murzin */ 28892116b80SVladimir Murzin #define gits_read_baser(c) __gic_readq_nonatomic(c) 28992116b80SVladimir Murzin #define gits_write_baser(v, c) __gic_writeq_nonatomic(v, c) 29092116b80SVladimir Murzin 29192116b80SVladimir Murzin /* 29292116b80SVladimir Murzin * GICR_PENDBASER and GICR_PROPBASE are changed with LPIs disabled, so they 29392116b80SVladimir Murzin * won't be being used during any updates and can be changed non-atomically 29492116b80SVladimir Murzin */ 29592116b80SVladimir Murzin #define gicr_read_propbaser(c) __gic_readq_nonatomic(c) 29692116b80SVladimir Murzin #define gicr_write_propbaser(v, c) __gic_writeq_nonatomic(v, c) 29792116b80SVladimir Murzin #define gicr_read_pendbaser(c) __gic_readq_nonatomic(c) 29892116b80SVladimir Murzin #define gicr_write_pendbaser(v, c) __gic_writeq_nonatomic(v, c) 29992116b80SVladimir Murzin 30092116b80SVladimir Murzin /* 301f6a91da7SMarc Zyngier * GICR_xLPIR - only the lower bits are significant 302f6a91da7SMarc Zyngier */ 303f6a91da7SMarc Zyngier #define gic_read_lpir(c) readl_relaxed(c) 304f6a91da7SMarc Zyngier #define gic_write_lpir(v, c) writel_relaxed(lower_32_bits(v), c) 305f6a91da7SMarc Zyngier 306f6a91da7SMarc Zyngier /* 30792116b80SVladimir Murzin * GITS_TYPER is an ID register and doesn't need atomicity. 30892116b80SVladimir Murzin */ 30992116b80SVladimir Murzin #define gits_read_typer(c) __gic_readq_nonatomic(c) 31092116b80SVladimir Murzin 31192116b80SVladimir Murzin /* 31292116b80SVladimir Murzin * GITS_CBASER - hi and lo bits may be accessed independently. 31392116b80SVladimir Murzin */ 31492116b80SVladimir Murzin #define gits_read_cbaser(c) __gic_readq_nonatomic(c) 31592116b80SVladimir Murzin #define gits_write_cbaser(v, c) __gic_writeq_nonatomic(v, c) 31692116b80SVladimir Murzin 31792116b80SVladimir Murzin /* 31892116b80SVladimir Murzin * GITS_CWRITER - hi and lo bits may be accessed independently. 31992116b80SVladimir Murzin */ 32092116b80SVladimir Murzin #define gits_write_cwriter(v, c) __gic_writeq_nonatomic(v, c) 32192116b80SVladimir Murzin 3223ca63f36SMarc Zyngier /* 3233ca63f36SMarc Zyngier * GITS_VPROPBASER - hi and lo bits may be accessed independently. 3243ca63f36SMarc Zyngier */ 3253ca63f36SMarc Zyngier #define gits_write_vpropbaser(v, c) __gic_writeq_nonatomic(v, c) 3263ca63f36SMarc Zyngier 3273ca63f36SMarc Zyngier /* 3283ca63f36SMarc Zyngier * GITS_VPENDBASER - the Valid bit must be cleared before changing 3293ca63f36SMarc Zyngier * anything else. 3303ca63f36SMarc Zyngier */ 3313ca63f36SMarc Zyngier static inline void gits_write_vpendbaser(u64 val, void * __iomem addr) 3323ca63f36SMarc Zyngier { 3333ca63f36SMarc Zyngier u32 tmp; 3343ca63f36SMarc Zyngier 3353ca63f36SMarc Zyngier tmp = readl_relaxed(addr + 4); 3363ca63f36SMarc Zyngier if (tmp & (GICR_VPENDBASER_Valid >> 32)) { 3373ca63f36SMarc Zyngier tmp &= ~(GICR_VPENDBASER_Valid >> 32); 3383ca63f36SMarc Zyngier writel_relaxed(tmp, addr + 4); 3393ca63f36SMarc Zyngier } 3403ca63f36SMarc Zyngier 3413ca63f36SMarc Zyngier /* 3423ca63f36SMarc Zyngier * Use the fact that __gic_writeq_nonatomic writes the second 3433ca63f36SMarc Zyngier * half of the 64bit quantity after the first. 3443ca63f36SMarc Zyngier */ 3453ca63f36SMarc Zyngier __gic_writeq_nonatomic(val, addr); 3463ca63f36SMarc Zyngier } 3473ca63f36SMarc Zyngier 3483ca63f36SMarc Zyngier #define gits_read_vpendbaser(c) __gic_readq_nonatomic(c) 3493ca63f36SMarc Zyngier 350d5cd50d3SJean-Philippe Brucker #endif /* !__ASSEMBLY__ */ 351d5cd50d3SJean-Philippe Brucker #endif /* !__ASM_ARCH_GICV3_H */ 352