1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * sha1-ce-core.S - SHA-1 secure hash using ARMv8 Crypto Extensions 4 * 5 * Copyright (C) 2015 Linaro Ltd. 6 * Author: Ard Biesheuvel <ard.biesheuvel@linaro.org> 7 */ 8 9#include <linux/linkage.h> 10#include <asm/assembler.h> 11 12 .text 13 .fpu crypto-neon-fp-armv8 14 15 k0 .req q0 16 k1 .req q1 17 k2 .req q2 18 k3 .req q3 19 20 ta0 .req q4 21 ta1 .req q5 22 tb0 .req q5 23 tb1 .req q4 24 25 dga .req q6 26 dgb .req q7 27 dgbs .req s28 28 29 dg0 .req q12 30 dg1a0 .req q13 31 dg1a1 .req q14 32 dg1b0 .req q14 33 dg1b1 .req q13 34 35 .macro add_only, op, ev, rc, s0, dg1 36 .ifnb \s0 37 vadd.u32 tb\ev, q\s0, \rc 38 .endif 39 sha1h.32 dg1b\ev, dg0 40 .ifb \dg1 41 sha1\op\().32 dg0, dg1a\ev, ta\ev 42 .else 43 sha1\op\().32 dg0, \dg1, ta\ev 44 .endif 45 .endm 46 47 .macro add_update, op, ev, rc, s0, s1, s2, s3, dg1 48 sha1su0.32 q\s0, q\s1, q\s2 49 add_only \op, \ev, \rc, \s1, \dg1 50 sha1su1.32 q\s0, q\s3 51 .endm 52 53 .align 6 54.Lsha1_rcon: 55 .word 0x5a827999, 0x5a827999, 0x5a827999, 0x5a827999 56 .word 0x6ed9eba1, 0x6ed9eba1, 0x6ed9eba1, 0x6ed9eba1 57 .word 0x8f1bbcdc, 0x8f1bbcdc, 0x8f1bbcdc, 0x8f1bbcdc 58 .word 0xca62c1d6, 0xca62c1d6, 0xca62c1d6, 0xca62c1d6 59 60 /* 61 * void sha1_ce_transform(struct sha1_state *sst, u8 const *src, 62 * int blocks); 63 */ 64ENTRY(sha1_ce_transform) 65 /* load round constants */ 66 adr ip, .Lsha1_rcon 67 vld1.32 {k0-k1}, [ip, :128]! 68 vld1.32 {k2-k3}, [ip, :128] 69 70 /* load state */ 71 vld1.32 {dga}, [r0] 72 vldr dgbs, [r0, #16] 73 74 /* load input */ 750: vld1.32 {q8-q9}, [r1]! 76 vld1.32 {q10-q11}, [r1]! 77 subs r2, r2, #1 78 79#ifndef CONFIG_CPU_BIG_ENDIAN 80 vrev32.8 q8, q8 81 vrev32.8 q9, q9 82 vrev32.8 q10, q10 83 vrev32.8 q11, q11 84#endif 85 86 vadd.u32 ta0, q8, k0 87 vmov dg0, dga 88 89 add_update c, 0, k0, 8, 9, 10, 11, dgb 90 add_update c, 1, k0, 9, 10, 11, 8 91 add_update c, 0, k0, 10, 11, 8, 9 92 add_update c, 1, k0, 11, 8, 9, 10 93 add_update c, 0, k1, 8, 9, 10, 11 94 95 add_update p, 1, k1, 9, 10, 11, 8 96 add_update p, 0, k1, 10, 11, 8, 9 97 add_update p, 1, k1, 11, 8, 9, 10 98 add_update p, 0, k1, 8, 9, 10, 11 99 add_update p, 1, k2, 9, 10, 11, 8 100 101 add_update m, 0, k2, 10, 11, 8, 9 102 add_update m, 1, k2, 11, 8, 9, 10 103 add_update m, 0, k2, 8, 9, 10, 11 104 add_update m, 1, k2, 9, 10, 11, 8 105 add_update m, 0, k3, 10, 11, 8, 9 106 107 add_update p, 1, k3, 11, 8, 9, 10 108 add_only p, 0, k3, 9 109 add_only p, 1, k3, 10 110 add_only p, 0, k3, 11 111 add_only p, 1 112 113 /* update state */ 114 vadd.u32 dga, dga, dg0 115 vadd.u32 dgb, dgb, dg1a0 116 bne 0b 117 118 /* store new state */ 119 vst1.32 {dga}, [r0] 120 vstr dgbs, [r0, #16] 121 bx lr 122ENDPROC(sha1_ce_transform) 123