1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/common/sa1111.c 4 * 5 * SA1111 support 6 * 7 * Original code by John Dorsey 8 * 9 * This file contains all generic SA1111 support. 10 * 11 * All initialization functions provided here are intended to be called 12 * from machine specific code with proper arguments when required. 13 */ 14 #include <linux/module.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/init.h> 17 #include <linux/irq.h> 18 #include <linux/kernel.h> 19 #include <linux/delay.h> 20 #include <linux/errno.h> 21 #include <linux/ioport.h> 22 #include <linux/platform_device.h> 23 #include <linux/slab.h> 24 #include <linux/spinlock.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/clk.h> 27 #include <linux/io.h> 28 29 #include <mach/hardware.h> 30 #include <asm/mach/irq.h> 31 #include <asm/mach-types.h> 32 #include <linux/sizes.h> 33 34 #include <asm/hardware/sa1111.h> 35 36 /* SA1111 IRQs */ 37 #define IRQ_GPAIN0 (0) 38 #define IRQ_GPAIN1 (1) 39 #define IRQ_GPAIN2 (2) 40 #define IRQ_GPAIN3 (3) 41 #define IRQ_GPBIN0 (4) 42 #define IRQ_GPBIN1 (5) 43 #define IRQ_GPBIN2 (6) 44 #define IRQ_GPBIN3 (7) 45 #define IRQ_GPBIN4 (8) 46 #define IRQ_GPBIN5 (9) 47 #define IRQ_GPCIN0 (10) 48 #define IRQ_GPCIN1 (11) 49 #define IRQ_GPCIN2 (12) 50 #define IRQ_GPCIN3 (13) 51 #define IRQ_GPCIN4 (14) 52 #define IRQ_GPCIN5 (15) 53 #define IRQ_GPCIN6 (16) 54 #define IRQ_GPCIN7 (17) 55 #define IRQ_MSTXINT (18) 56 #define IRQ_MSRXINT (19) 57 #define IRQ_MSSTOPERRINT (20) 58 #define IRQ_TPTXINT (21) 59 #define IRQ_TPRXINT (22) 60 #define IRQ_TPSTOPERRINT (23) 61 #define SSPXMTINT (24) 62 #define SSPRCVINT (25) 63 #define SSPROR (26) 64 #define AUDXMTDMADONEA (32) 65 #define AUDRCVDMADONEA (33) 66 #define AUDXMTDMADONEB (34) 67 #define AUDRCVDMADONEB (35) 68 #define AUDTFSR (36) 69 #define AUDRFSR (37) 70 #define AUDTUR (38) 71 #define AUDROR (39) 72 #define AUDDTS (40) 73 #define AUDRDD (41) 74 #define AUDSTO (42) 75 #define IRQ_USBPWR (43) 76 #define IRQ_HCIM (44) 77 #define IRQ_HCIBUFFACC (45) 78 #define IRQ_HCIRMTWKP (46) 79 #define IRQ_NHCIMFCIR (47) 80 #define IRQ_USB_PORT_RESUME (48) 81 #define IRQ_S0_READY_NINT (49) 82 #define IRQ_S1_READY_NINT (50) 83 #define IRQ_S0_CD_VALID (51) 84 #define IRQ_S1_CD_VALID (52) 85 #define IRQ_S0_BVD1_STSCHG (53) 86 #define IRQ_S1_BVD1_STSCHG (54) 87 #define SA1111_IRQ_NR (55) 88 89 extern void sa1110_mb_enable(void); 90 extern void sa1110_mb_disable(void); 91 92 /* 93 * We keep the following data for the overall SA1111. Note that the 94 * struct device and struct resource are "fake"; they should be supplied 95 * by the bus above us. However, in the interests of getting all SA1111 96 * drivers converted over to the device model, we provide this as an 97 * anchor point for all the other drivers. 98 */ 99 struct sa1111 { 100 struct device *dev; 101 struct clk *clk; 102 unsigned long phys; 103 int irq; 104 int irq_base; /* base for cascaded on-chip IRQs */ 105 spinlock_t lock; 106 void __iomem *base; 107 struct sa1111_platform_data *pdata; 108 struct irq_domain *irqdomain; 109 struct gpio_chip gc; 110 #ifdef CONFIG_PM 111 void *saved_state; 112 #endif 113 }; 114 115 /* 116 * We _really_ need to eliminate this. Its only users 117 * are the PWM and DMA checking code. 118 */ 119 static struct sa1111 *g_sa1111; 120 121 struct sa1111_dev_info { 122 unsigned long offset; 123 unsigned long skpcr_mask; 124 bool dma; 125 unsigned int devid; 126 unsigned int hwirq[6]; 127 }; 128 129 static struct sa1111_dev_info sa1111_devices[] = { 130 { 131 .offset = SA1111_USB, 132 .skpcr_mask = SKPCR_UCLKEN, 133 .dma = true, 134 .devid = SA1111_DEVID_USB, 135 .hwirq = { 136 IRQ_USBPWR, 137 IRQ_HCIM, 138 IRQ_HCIBUFFACC, 139 IRQ_HCIRMTWKP, 140 IRQ_NHCIMFCIR, 141 IRQ_USB_PORT_RESUME 142 }, 143 }, 144 { 145 .offset = 0x0600, 146 .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN, 147 .dma = true, 148 .devid = SA1111_DEVID_SAC, 149 .hwirq = { 150 AUDXMTDMADONEA, 151 AUDXMTDMADONEB, 152 AUDRCVDMADONEA, 153 AUDRCVDMADONEB 154 }, 155 }, 156 { 157 .offset = 0x0800, 158 .skpcr_mask = SKPCR_SCLKEN, 159 .devid = SA1111_DEVID_SSP, 160 }, 161 { 162 .offset = SA1111_KBD, 163 .skpcr_mask = SKPCR_PTCLKEN, 164 .devid = SA1111_DEVID_PS2_KBD, 165 .hwirq = { 166 IRQ_TPRXINT, 167 IRQ_TPTXINT 168 }, 169 }, 170 { 171 .offset = SA1111_MSE, 172 .skpcr_mask = SKPCR_PMCLKEN, 173 .devid = SA1111_DEVID_PS2_MSE, 174 .hwirq = { 175 IRQ_MSRXINT, 176 IRQ_MSTXINT 177 }, 178 }, 179 { 180 .offset = 0x1800, 181 .skpcr_mask = 0, 182 .devid = SA1111_DEVID_PCMCIA, 183 .hwirq = { 184 IRQ_S0_READY_NINT, 185 IRQ_S0_CD_VALID, 186 IRQ_S0_BVD1_STSCHG, 187 IRQ_S1_READY_NINT, 188 IRQ_S1_CD_VALID, 189 IRQ_S1_BVD1_STSCHG, 190 }, 191 }, 192 }; 193 194 static int sa1111_map_irq(struct sa1111 *sachip, irq_hw_number_t hwirq) 195 { 196 return irq_create_mapping(sachip->irqdomain, hwirq); 197 } 198 199 static void sa1111_handle_irqdomain(struct irq_domain *irqdomain, int irq) 200 { 201 struct irq_desc *d = irq_to_desc(irq_linear_revmap(irqdomain, irq)); 202 203 if (d) 204 generic_handle_irq_desc(d); 205 } 206 207 /* 208 * SA1111 interrupt support. Since clearing an IRQ while there are 209 * active IRQs causes the interrupt output to pulse, the upper levels 210 * will call us again if there are more interrupts to process. 211 */ 212 static void sa1111_irq_handler(struct irq_desc *desc) 213 { 214 unsigned int stat0, stat1, i; 215 struct sa1111 *sachip = irq_desc_get_handler_data(desc); 216 struct irq_domain *irqdomain; 217 void __iomem *mapbase = sachip->base + SA1111_INTC; 218 219 stat0 = readl_relaxed(mapbase + SA1111_INTSTATCLR0); 220 stat1 = readl_relaxed(mapbase + SA1111_INTSTATCLR1); 221 222 writel_relaxed(stat0, mapbase + SA1111_INTSTATCLR0); 223 224 desc->irq_data.chip->irq_ack(&desc->irq_data); 225 226 writel_relaxed(stat1, mapbase + SA1111_INTSTATCLR1); 227 228 if (stat0 == 0 && stat1 == 0) { 229 do_bad_IRQ(desc); 230 return; 231 } 232 233 irqdomain = sachip->irqdomain; 234 235 for (i = 0; stat0; i++, stat0 >>= 1) 236 if (stat0 & 1) 237 sa1111_handle_irqdomain(irqdomain, i); 238 239 for (i = 32; stat1; i++, stat1 >>= 1) 240 if (stat1 & 1) 241 sa1111_handle_irqdomain(irqdomain, i); 242 243 /* For level-based interrupts */ 244 desc->irq_data.chip->irq_unmask(&desc->irq_data); 245 } 246 247 static u32 sa1111_irqmask(struct irq_data *d) 248 { 249 return BIT(irqd_to_hwirq(d) & 31); 250 } 251 252 static int sa1111_irqbank(struct irq_data *d) 253 { 254 return (irqd_to_hwirq(d) / 32) * 4; 255 } 256 257 static void sa1111_ack_irq(struct irq_data *d) 258 { 259 } 260 261 static void sa1111_mask_irq(struct irq_data *d) 262 { 263 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 264 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d); 265 u32 ie; 266 267 ie = readl_relaxed(mapbase + SA1111_INTEN0); 268 ie &= ~sa1111_irqmask(d); 269 writel(ie, mapbase + SA1111_INTEN0); 270 } 271 272 static void sa1111_unmask_irq(struct irq_data *d) 273 { 274 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 275 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d); 276 u32 ie; 277 278 ie = readl_relaxed(mapbase + SA1111_INTEN0); 279 ie |= sa1111_irqmask(d); 280 writel_relaxed(ie, mapbase + SA1111_INTEN0); 281 } 282 283 /* 284 * Attempt to re-trigger the interrupt. The SA1111 contains a register 285 * (INTSET) which claims to do this. However, in practice no amount of 286 * manipulation of INTEN and INTSET guarantees that the interrupt will 287 * be triggered. In fact, its very difficult, if not impossible to get 288 * INTSET to re-trigger the interrupt. 289 */ 290 static int sa1111_retrigger_irq(struct irq_data *d) 291 { 292 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 293 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d); 294 u32 ip, mask = sa1111_irqmask(d); 295 int i; 296 297 ip = readl_relaxed(mapbase + SA1111_INTPOL0); 298 for (i = 0; i < 8; i++) { 299 writel_relaxed(ip ^ mask, mapbase + SA1111_INTPOL0); 300 writel_relaxed(ip, mapbase + SA1111_INTPOL0); 301 if (readl_relaxed(mapbase + SA1111_INTSTATCLR0) & mask) 302 break; 303 } 304 305 if (i == 8) 306 pr_err("Danger Will Robinson: failed to re-trigger IRQ%d\n", 307 d->irq); 308 return i == 8 ? -1 : 0; 309 } 310 311 static int sa1111_type_irq(struct irq_data *d, unsigned int flags) 312 { 313 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 314 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d); 315 u32 ip, mask = sa1111_irqmask(d); 316 317 if (flags == IRQ_TYPE_PROBE) 318 return 0; 319 320 if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0) 321 return -EINVAL; 322 323 ip = readl_relaxed(mapbase + SA1111_INTPOL0); 324 if (flags & IRQ_TYPE_EDGE_RISING) 325 ip &= ~mask; 326 else 327 ip |= mask; 328 writel_relaxed(ip, mapbase + SA1111_INTPOL0); 329 writel_relaxed(ip, mapbase + SA1111_WAKEPOL0); 330 331 return 0; 332 } 333 334 static int sa1111_wake_irq(struct irq_data *d, unsigned int on) 335 { 336 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 337 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d); 338 u32 we, mask = sa1111_irqmask(d); 339 340 we = readl_relaxed(mapbase + SA1111_WAKEEN0); 341 if (on) 342 we |= mask; 343 else 344 we &= ~mask; 345 writel_relaxed(we, mapbase + SA1111_WAKEEN0); 346 347 return 0; 348 } 349 350 static struct irq_chip sa1111_irq_chip = { 351 .name = "SA1111", 352 .irq_ack = sa1111_ack_irq, 353 .irq_mask = sa1111_mask_irq, 354 .irq_unmask = sa1111_unmask_irq, 355 .irq_retrigger = sa1111_retrigger_irq, 356 .irq_set_type = sa1111_type_irq, 357 .irq_set_wake = sa1111_wake_irq, 358 }; 359 360 static int sa1111_irqdomain_map(struct irq_domain *d, unsigned int irq, 361 irq_hw_number_t hwirq) 362 { 363 struct sa1111 *sachip = d->host_data; 364 365 /* Disallow unavailable interrupts */ 366 if (hwirq > SSPROR && hwirq < AUDXMTDMADONEA) 367 return -EINVAL; 368 369 irq_set_chip_data(irq, sachip); 370 irq_set_chip_and_handler(irq, &sa1111_irq_chip, handle_edge_irq); 371 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); 372 373 return 0; 374 } 375 376 static const struct irq_domain_ops sa1111_irqdomain_ops = { 377 .map = sa1111_irqdomain_map, 378 .xlate = irq_domain_xlate_twocell, 379 }; 380 381 static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base) 382 { 383 void __iomem *irqbase = sachip->base + SA1111_INTC; 384 int ret; 385 386 /* 387 * We're guaranteed that this region hasn't been taken. 388 */ 389 request_mem_region(sachip->phys + SA1111_INTC, 512, "irq"); 390 391 ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1); 392 if (ret <= 0) { 393 dev_err(sachip->dev, "unable to allocate %u irqs: %d\n", 394 SA1111_IRQ_NR, ret); 395 if (ret == 0) 396 ret = -EINVAL; 397 return ret; 398 } 399 400 sachip->irq_base = ret; 401 402 /* disable all IRQs */ 403 writel_relaxed(0, irqbase + SA1111_INTEN0); 404 writel_relaxed(0, irqbase + SA1111_INTEN1); 405 writel_relaxed(0, irqbase + SA1111_WAKEEN0); 406 writel_relaxed(0, irqbase + SA1111_WAKEEN1); 407 408 /* 409 * detect on rising edge. Note: Feb 2001 Errata for SA1111 410 * specifies that S0ReadyInt and S1ReadyInt should be '1'. 411 */ 412 writel_relaxed(0, irqbase + SA1111_INTPOL0); 413 writel_relaxed(BIT(IRQ_S0_READY_NINT & 31) | 414 BIT(IRQ_S1_READY_NINT & 31), 415 irqbase + SA1111_INTPOL1); 416 417 /* clear all IRQs */ 418 writel_relaxed(~0, irqbase + SA1111_INTSTATCLR0); 419 writel_relaxed(~0, irqbase + SA1111_INTSTATCLR1); 420 421 sachip->irqdomain = irq_domain_add_linear(NULL, SA1111_IRQ_NR, 422 &sa1111_irqdomain_ops, 423 sachip); 424 if (!sachip->irqdomain) { 425 irq_free_descs(sachip->irq_base, SA1111_IRQ_NR); 426 return -ENOMEM; 427 } 428 429 irq_domain_associate_many(sachip->irqdomain, 430 sachip->irq_base + IRQ_GPAIN0, 431 IRQ_GPAIN0, SSPROR + 1 - IRQ_GPAIN0); 432 irq_domain_associate_many(sachip->irqdomain, 433 sachip->irq_base + AUDXMTDMADONEA, 434 AUDXMTDMADONEA, 435 IRQ_S1_BVD1_STSCHG + 1 - AUDXMTDMADONEA); 436 437 /* 438 * Register SA1111 interrupt 439 */ 440 irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); 441 irq_set_chained_handler_and_data(sachip->irq, sa1111_irq_handler, 442 sachip); 443 444 dev_info(sachip->dev, "Providing IRQ%u-%u\n", 445 sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1); 446 447 return 0; 448 } 449 450 static void sa1111_remove_irq(struct sa1111 *sachip) 451 { 452 struct irq_domain *domain = sachip->irqdomain; 453 void __iomem *irqbase = sachip->base + SA1111_INTC; 454 int i; 455 456 /* disable all IRQs */ 457 writel_relaxed(0, irqbase + SA1111_INTEN0); 458 writel_relaxed(0, irqbase + SA1111_INTEN1); 459 writel_relaxed(0, irqbase + SA1111_WAKEEN0); 460 writel_relaxed(0, irqbase + SA1111_WAKEEN1); 461 462 irq_set_chained_handler_and_data(sachip->irq, NULL, NULL); 463 for (i = 0; i < SA1111_IRQ_NR; i++) 464 irq_dispose_mapping(irq_find_mapping(domain, i)); 465 irq_domain_remove(domain); 466 467 release_mem_region(sachip->phys + SA1111_INTC, 512); 468 } 469 470 enum { 471 SA1111_GPIO_PXDDR = (SA1111_GPIO_PADDR - SA1111_GPIO_PADDR), 472 SA1111_GPIO_PXDRR = (SA1111_GPIO_PADRR - SA1111_GPIO_PADDR), 473 SA1111_GPIO_PXDWR = (SA1111_GPIO_PADWR - SA1111_GPIO_PADDR), 474 SA1111_GPIO_PXSDR = (SA1111_GPIO_PASDR - SA1111_GPIO_PADDR), 475 SA1111_GPIO_PXSSR = (SA1111_GPIO_PASSR - SA1111_GPIO_PADDR), 476 }; 477 478 static struct sa1111 *gc_to_sa1111(struct gpio_chip *gc) 479 { 480 return container_of(gc, struct sa1111, gc); 481 } 482 483 static void __iomem *sa1111_gpio_map_reg(struct sa1111 *sachip, unsigned offset) 484 { 485 void __iomem *reg = sachip->base + SA1111_GPIO; 486 487 if (offset < 4) 488 return reg + SA1111_GPIO_PADDR; 489 if (offset < 10) 490 return reg + SA1111_GPIO_PBDDR; 491 if (offset < 18) 492 return reg + SA1111_GPIO_PCDDR; 493 return NULL; 494 } 495 496 static u32 sa1111_gpio_map_bit(unsigned offset) 497 { 498 if (offset < 4) 499 return BIT(offset); 500 if (offset < 10) 501 return BIT(offset - 4); 502 if (offset < 18) 503 return BIT(offset - 10); 504 return 0; 505 } 506 507 static void sa1111_gpio_modify(void __iomem *reg, u32 mask, u32 set) 508 { 509 u32 val; 510 511 val = readl_relaxed(reg); 512 val &= ~mask; 513 val |= mask & set; 514 writel_relaxed(val, reg); 515 } 516 517 static int sa1111_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 518 { 519 struct sa1111 *sachip = gc_to_sa1111(gc); 520 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset); 521 u32 mask = sa1111_gpio_map_bit(offset); 522 523 return !!(readl_relaxed(reg + SA1111_GPIO_PXDDR) & mask); 524 } 525 526 static int sa1111_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 527 { 528 struct sa1111 *sachip = gc_to_sa1111(gc); 529 unsigned long flags; 530 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset); 531 u32 mask = sa1111_gpio_map_bit(offset); 532 533 spin_lock_irqsave(&sachip->lock, flags); 534 sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, mask); 535 sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, mask); 536 spin_unlock_irqrestore(&sachip->lock, flags); 537 538 return 0; 539 } 540 541 static int sa1111_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 542 int value) 543 { 544 struct sa1111 *sachip = gc_to_sa1111(gc); 545 unsigned long flags; 546 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset); 547 u32 mask = sa1111_gpio_map_bit(offset); 548 549 spin_lock_irqsave(&sachip->lock, flags); 550 sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0); 551 sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0); 552 sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, 0); 553 sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, 0); 554 spin_unlock_irqrestore(&sachip->lock, flags); 555 556 return 0; 557 } 558 559 static int sa1111_gpio_get(struct gpio_chip *gc, unsigned offset) 560 { 561 struct sa1111 *sachip = gc_to_sa1111(gc); 562 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset); 563 u32 mask = sa1111_gpio_map_bit(offset); 564 565 return !!(readl_relaxed(reg + SA1111_GPIO_PXDRR) & mask); 566 } 567 568 static void sa1111_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 569 { 570 struct sa1111 *sachip = gc_to_sa1111(gc); 571 unsigned long flags; 572 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset); 573 u32 mask = sa1111_gpio_map_bit(offset); 574 575 spin_lock_irqsave(&sachip->lock, flags); 576 sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0); 577 sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0); 578 spin_unlock_irqrestore(&sachip->lock, flags); 579 } 580 581 static void sa1111_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 582 unsigned long *bits) 583 { 584 struct sa1111 *sachip = gc_to_sa1111(gc); 585 unsigned long flags; 586 void __iomem *reg = sachip->base + SA1111_GPIO; 587 u32 msk, val; 588 589 msk = *mask; 590 val = *bits; 591 592 spin_lock_irqsave(&sachip->lock, flags); 593 sa1111_gpio_modify(reg + SA1111_GPIO_PADWR, msk & 15, val); 594 sa1111_gpio_modify(reg + SA1111_GPIO_PASSR, msk & 15, val); 595 sa1111_gpio_modify(reg + SA1111_GPIO_PBDWR, (msk >> 4) & 255, val >> 4); 596 sa1111_gpio_modify(reg + SA1111_GPIO_PBSSR, (msk >> 4) & 255, val >> 4); 597 sa1111_gpio_modify(reg + SA1111_GPIO_PCDWR, (msk >> 12) & 255, val >> 12); 598 sa1111_gpio_modify(reg + SA1111_GPIO_PCSSR, (msk >> 12) & 255, val >> 12); 599 spin_unlock_irqrestore(&sachip->lock, flags); 600 } 601 602 static int sa1111_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 603 { 604 struct sa1111 *sachip = gc_to_sa1111(gc); 605 606 return sa1111_map_irq(sachip, offset); 607 } 608 609 static int sa1111_setup_gpios(struct sa1111 *sachip) 610 { 611 sachip->gc.label = "sa1111"; 612 sachip->gc.parent = sachip->dev; 613 sachip->gc.owner = THIS_MODULE; 614 sachip->gc.get_direction = sa1111_gpio_get_direction; 615 sachip->gc.direction_input = sa1111_gpio_direction_input; 616 sachip->gc.direction_output = sa1111_gpio_direction_output; 617 sachip->gc.get = sa1111_gpio_get; 618 sachip->gc.set = sa1111_gpio_set; 619 sachip->gc.set_multiple = sa1111_gpio_set_multiple; 620 sachip->gc.to_irq = sa1111_gpio_to_irq; 621 sachip->gc.base = -1; 622 sachip->gc.ngpio = 18; 623 624 return devm_gpiochip_add_data(sachip->dev, &sachip->gc, sachip); 625 } 626 627 /* 628 * Bring the SA1111 out of reset. This requires a set procedure: 629 * 1. nRESET asserted (by hardware) 630 * 2. CLK turned on from SA1110 631 * 3. nRESET deasserted 632 * 4. VCO turned on, PLL_BYPASS turned off 633 * 5. Wait lock time, then assert RCLKEn 634 * 7. PCR set to allow clocking of individual functions 635 * 636 * Until we've done this, the only registers we can access are: 637 * SBI_SKCR 638 * SBI_SMCR 639 * SBI_SKID 640 */ 641 static void sa1111_wake(struct sa1111 *sachip) 642 { 643 unsigned long flags, r; 644 645 spin_lock_irqsave(&sachip->lock, flags); 646 647 clk_enable(sachip->clk); 648 649 /* 650 * Turn VCO on, and disable PLL Bypass. 651 */ 652 r = readl_relaxed(sachip->base + SA1111_SKCR); 653 r &= ~SKCR_VCO_OFF; 654 writel_relaxed(r, sachip->base + SA1111_SKCR); 655 r |= SKCR_PLL_BYPASS | SKCR_OE_EN; 656 writel_relaxed(r, sachip->base + SA1111_SKCR); 657 658 /* 659 * Wait lock time. SA1111 manual _doesn't_ 660 * specify a figure for this! We choose 100us. 661 */ 662 udelay(100); 663 664 /* 665 * Enable RCLK. We also ensure that RDYEN is set. 666 */ 667 r |= SKCR_RCLKEN | SKCR_RDYEN; 668 writel_relaxed(r, sachip->base + SA1111_SKCR); 669 670 /* 671 * Wait 14 RCLK cycles for the chip to finish coming out 672 * of reset. (RCLK=24MHz). This is 590ns. 673 */ 674 udelay(1); 675 676 /* 677 * Ensure all clocks are initially off. 678 */ 679 writel_relaxed(0, sachip->base + SA1111_SKPCR); 680 681 spin_unlock_irqrestore(&sachip->lock, flags); 682 } 683 684 #ifdef CONFIG_ARCH_SA1100 685 686 static u32 sa1111_dma_mask[] = { 687 ~0, 688 ~(1 << 20), 689 ~(1 << 23), 690 ~(1 << 24), 691 ~(1 << 25), 692 ~(1 << 20), 693 ~(1 << 20), 694 0, 695 }; 696 697 /* 698 * Configure the SA1111 shared memory controller. 699 */ 700 void 701 sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac, 702 unsigned int cas_latency) 703 { 704 unsigned int smcr = SMCR_DTIM | SMCR_MBGE | FInsrt(drac, SMCR_DRAC); 705 706 if (cas_latency == 3) 707 smcr |= SMCR_CLAT; 708 709 writel_relaxed(smcr, sachip->base + SA1111_SMCR); 710 711 /* 712 * Now clear the bits in the DMA mask to work around the SA1111 713 * DMA erratum (Intel StrongARM SA-1111 Microprocessor Companion 714 * Chip Specification Update, June 2000, Erratum #7). 715 */ 716 if (sachip->dev->dma_mask) 717 *sachip->dev->dma_mask &= sa1111_dma_mask[drac >> 2]; 718 719 sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2]; 720 } 721 #endif 722 723 static void sa1111_dev_release(struct device *_dev) 724 { 725 struct sa1111_dev *dev = to_sa1111_device(_dev); 726 727 kfree(dev); 728 } 729 730 static int 731 sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent, 732 struct sa1111_dev_info *info) 733 { 734 struct sa1111_dev *dev; 735 unsigned i; 736 int ret; 737 738 dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL); 739 if (!dev) { 740 ret = -ENOMEM; 741 goto err_alloc; 742 } 743 744 device_initialize(&dev->dev); 745 dev_set_name(&dev->dev, "%4.4lx", info->offset); 746 dev->devid = info->devid; 747 dev->dev.parent = sachip->dev; 748 dev->dev.bus = &sa1111_bus_type; 749 dev->dev.release = sa1111_dev_release; 750 dev->res.start = sachip->phys + info->offset; 751 dev->res.end = dev->res.start + 511; 752 dev->res.name = dev_name(&dev->dev); 753 dev->res.flags = IORESOURCE_MEM; 754 dev->mapbase = sachip->base + info->offset; 755 dev->skpcr_mask = info->skpcr_mask; 756 757 for (i = 0; i < ARRAY_SIZE(info->hwirq); i++) 758 dev->hwirq[i] = info->hwirq[i]; 759 760 /* 761 * If the parent device has a DMA mask associated with it, and 762 * this child supports DMA, propagate it down to the children. 763 */ 764 if (info->dma && sachip->dev->dma_mask) { 765 dev->dma_mask = *sachip->dev->dma_mask; 766 dev->dev.dma_mask = &dev->dma_mask; 767 dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask; 768 } 769 770 ret = request_resource(parent, &dev->res); 771 if (ret) { 772 dev_err(sachip->dev, "failed to allocate resource for %s\n", 773 dev->res.name); 774 goto err_resource; 775 } 776 777 ret = device_add(&dev->dev); 778 if (ret) 779 goto err_add; 780 return 0; 781 782 err_add: 783 release_resource(&dev->res); 784 err_resource: 785 put_device(&dev->dev); 786 err_alloc: 787 return ret; 788 } 789 790 /** 791 * sa1111_probe - probe for a single SA1111 chip. 792 * @phys_addr: physical address of device. 793 * 794 * Probe for a SA1111 chip. This must be called 795 * before any other SA1111-specific code. 796 * 797 * Returns: 798 * %-ENODEV device not found. 799 * %-EBUSY physical address already marked in-use. 800 * %-EINVAL no platform data passed 801 * %0 successful. 802 */ 803 static int __sa1111_probe(struct device *me, struct resource *mem, int irq) 804 { 805 struct sa1111_platform_data *pd = me->platform_data; 806 struct sa1111 *sachip; 807 unsigned long id; 808 unsigned int has_devs; 809 int i, ret = -ENODEV; 810 811 if (!pd) 812 return -EINVAL; 813 814 sachip = devm_kzalloc(me, sizeof(struct sa1111), GFP_KERNEL); 815 if (!sachip) 816 return -ENOMEM; 817 818 sachip->clk = devm_clk_get(me, "SA1111_CLK"); 819 if (IS_ERR(sachip->clk)) 820 return PTR_ERR(sachip->clk); 821 822 ret = clk_prepare(sachip->clk); 823 if (ret) 824 return ret; 825 826 spin_lock_init(&sachip->lock); 827 828 sachip->dev = me; 829 dev_set_drvdata(sachip->dev, sachip); 830 831 sachip->pdata = pd; 832 sachip->phys = mem->start; 833 sachip->irq = irq; 834 835 /* 836 * Map the whole region. This also maps the 837 * registers for our children. 838 */ 839 sachip->base = ioremap(mem->start, PAGE_SIZE * 2); 840 if (!sachip->base) { 841 ret = -ENOMEM; 842 goto err_clk_unprep; 843 } 844 845 /* 846 * Probe for the chip. Only touch the SBI registers. 847 */ 848 id = readl_relaxed(sachip->base + SA1111_SKID); 849 if ((id & SKID_ID_MASK) != SKID_SA1111_ID) { 850 printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id); 851 ret = -ENODEV; 852 goto err_unmap; 853 } 854 855 pr_info("SA1111 Microprocessor Companion Chip: silicon revision %lx, metal revision %lx\n", 856 (id & SKID_SIREV_MASK) >> 4, id & SKID_MTREV_MASK); 857 858 /* 859 * We found it. Wake the chip up, and initialise. 860 */ 861 sa1111_wake(sachip); 862 863 /* 864 * The interrupt controller must be initialised before any 865 * other device to ensure that the interrupts are available. 866 */ 867 ret = sa1111_setup_irq(sachip, pd->irq_base); 868 if (ret) 869 goto err_clk; 870 871 /* Setup the GPIOs - should really be done after the IRQ setup */ 872 ret = sa1111_setup_gpios(sachip); 873 if (ret) 874 goto err_irq; 875 876 #ifdef CONFIG_ARCH_SA1100 877 { 878 unsigned int val; 879 880 /* 881 * The SDRAM configuration of the SA1110 and the SA1111 must 882 * match. This is very important to ensure that SA1111 accesses 883 * don't corrupt the SDRAM. Note that this ungates the SA1111's 884 * MBGNT signal, so we must have called sa1110_mb_disable() 885 * beforehand. 886 */ 887 sa1111_configure_smc(sachip, 1, 888 FExtr(MDCNFG, MDCNFG_SA1110_DRAC0), 889 FExtr(MDCNFG, MDCNFG_SA1110_TDL0)); 890 891 /* 892 * We only need to turn on DCLK whenever we want to use the 893 * DMA. It can otherwise be held firmly in the off position. 894 * (currently, we always enable it.) 895 */ 896 val = readl_relaxed(sachip->base + SA1111_SKPCR); 897 writel_relaxed(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR); 898 899 /* 900 * Enable the SA1110 memory bus request and grant signals. 901 */ 902 sa1110_mb_enable(); 903 } 904 #endif 905 906 g_sa1111 = sachip; 907 908 has_devs = ~0; 909 if (pd) 910 has_devs &= ~pd->disable_devs; 911 912 for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++) 913 if (sa1111_devices[i].devid & has_devs) 914 sa1111_init_one_child(sachip, mem, &sa1111_devices[i]); 915 916 return 0; 917 918 err_irq: 919 sa1111_remove_irq(sachip); 920 err_clk: 921 clk_disable(sachip->clk); 922 err_unmap: 923 iounmap(sachip->base); 924 err_clk_unprep: 925 clk_unprepare(sachip->clk); 926 return ret; 927 } 928 929 static int sa1111_remove_one(struct device *dev, void *data) 930 { 931 struct sa1111_dev *sadev = to_sa1111_device(dev); 932 if (dev->bus != &sa1111_bus_type) 933 return 0; 934 device_del(&sadev->dev); 935 release_resource(&sadev->res); 936 put_device(&sadev->dev); 937 return 0; 938 } 939 940 static void __sa1111_remove(struct sa1111 *sachip) 941 { 942 device_for_each_child(sachip->dev, NULL, sa1111_remove_one); 943 944 sa1111_remove_irq(sachip); 945 946 clk_disable(sachip->clk); 947 clk_unprepare(sachip->clk); 948 949 iounmap(sachip->base); 950 } 951 952 struct sa1111_save_data { 953 unsigned int skcr; 954 unsigned int skpcr; 955 unsigned int skcdr; 956 unsigned char skaud; 957 unsigned char skpwm0; 958 unsigned char skpwm1; 959 960 /* 961 * Interrupt controller 962 */ 963 unsigned int intpol0; 964 unsigned int intpol1; 965 unsigned int inten0; 966 unsigned int inten1; 967 unsigned int wakepol0; 968 unsigned int wakepol1; 969 unsigned int wakeen0; 970 unsigned int wakeen1; 971 }; 972 973 #ifdef CONFIG_PM 974 975 static int sa1111_suspend_noirq(struct device *dev) 976 { 977 struct sa1111 *sachip = dev_get_drvdata(dev); 978 struct sa1111_save_data *save; 979 unsigned long flags; 980 unsigned int val; 981 void __iomem *base; 982 983 save = kmalloc(sizeof(struct sa1111_save_data), GFP_KERNEL); 984 if (!save) 985 return -ENOMEM; 986 sachip->saved_state = save; 987 988 spin_lock_irqsave(&sachip->lock, flags); 989 990 /* 991 * Save state. 992 */ 993 base = sachip->base; 994 save->skcr = readl_relaxed(base + SA1111_SKCR); 995 save->skpcr = readl_relaxed(base + SA1111_SKPCR); 996 save->skcdr = readl_relaxed(base + SA1111_SKCDR); 997 save->skaud = readl_relaxed(base + SA1111_SKAUD); 998 save->skpwm0 = readl_relaxed(base + SA1111_SKPWM0); 999 save->skpwm1 = readl_relaxed(base + SA1111_SKPWM1); 1000 1001 writel_relaxed(0, sachip->base + SA1111_SKPWM0); 1002 writel_relaxed(0, sachip->base + SA1111_SKPWM1); 1003 1004 base = sachip->base + SA1111_INTC; 1005 save->intpol0 = readl_relaxed(base + SA1111_INTPOL0); 1006 save->intpol1 = readl_relaxed(base + SA1111_INTPOL1); 1007 save->inten0 = readl_relaxed(base + SA1111_INTEN0); 1008 save->inten1 = readl_relaxed(base + SA1111_INTEN1); 1009 save->wakepol0 = readl_relaxed(base + SA1111_WAKEPOL0); 1010 save->wakepol1 = readl_relaxed(base + SA1111_WAKEPOL1); 1011 save->wakeen0 = readl_relaxed(base + SA1111_WAKEEN0); 1012 save->wakeen1 = readl_relaxed(base + SA1111_WAKEEN1); 1013 1014 /* 1015 * Disable. 1016 */ 1017 val = readl_relaxed(sachip->base + SA1111_SKCR); 1018 writel_relaxed(val | SKCR_SLEEP, sachip->base + SA1111_SKCR); 1019 1020 clk_disable(sachip->clk); 1021 1022 spin_unlock_irqrestore(&sachip->lock, flags); 1023 1024 #ifdef CONFIG_ARCH_SA1100 1025 sa1110_mb_disable(); 1026 #endif 1027 1028 return 0; 1029 } 1030 1031 /* 1032 * sa1111_resume - Restore the SA1111 device state. 1033 * @dev: device to restore 1034 * 1035 * Restore the general state of the SA1111; clock control and 1036 * interrupt controller. Other parts of the SA1111 must be 1037 * restored by their respective drivers, and must be called 1038 * via LDM after this function. 1039 */ 1040 static int sa1111_resume_noirq(struct device *dev) 1041 { 1042 struct sa1111 *sachip = dev_get_drvdata(dev); 1043 struct sa1111_save_data *save; 1044 unsigned long flags, id; 1045 void __iomem *base; 1046 1047 save = sachip->saved_state; 1048 if (!save) 1049 return 0; 1050 1051 /* 1052 * Ensure that the SA1111 is still here. 1053 * FIXME: shouldn't do this here. 1054 */ 1055 id = readl_relaxed(sachip->base + SA1111_SKID); 1056 if ((id & SKID_ID_MASK) != SKID_SA1111_ID) { 1057 __sa1111_remove(sachip); 1058 dev_set_drvdata(dev, NULL); 1059 kfree(save); 1060 return 0; 1061 } 1062 1063 /* 1064 * First of all, wake up the chip. 1065 */ 1066 sa1111_wake(sachip); 1067 1068 #ifdef CONFIG_ARCH_SA1100 1069 /* Enable the memory bus request/grant signals */ 1070 sa1110_mb_enable(); 1071 #endif 1072 1073 /* 1074 * Only lock for write ops. Also, sa1111_wake must be called with 1075 * released spinlock! 1076 */ 1077 spin_lock_irqsave(&sachip->lock, flags); 1078 1079 writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN0); 1080 writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN1); 1081 1082 base = sachip->base; 1083 writel_relaxed(save->skcr, base + SA1111_SKCR); 1084 writel_relaxed(save->skpcr, base + SA1111_SKPCR); 1085 writel_relaxed(save->skcdr, base + SA1111_SKCDR); 1086 writel_relaxed(save->skaud, base + SA1111_SKAUD); 1087 writel_relaxed(save->skpwm0, base + SA1111_SKPWM0); 1088 writel_relaxed(save->skpwm1, base + SA1111_SKPWM1); 1089 1090 base = sachip->base + SA1111_INTC; 1091 writel_relaxed(save->intpol0, base + SA1111_INTPOL0); 1092 writel_relaxed(save->intpol1, base + SA1111_INTPOL1); 1093 writel_relaxed(save->inten0, base + SA1111_INTEN0); 1094 writel_relaxed(save->inten1, base + SA1111_INTEN1); 1095 writel_relaxed(save->wakepol0, base + SA1111_WAKEPOL0); 1096 writel_relaxed(save->wakepol1, base + SA1111_WAKEPOL1); 1097 writel_relaxed(save->wakeen0, base + SA1111_WAKEEN0); 1098 writel_relaxed(save->wakeen1, base + SA1111_WAKEEN1); 1099 1100 spin_unlock_irqrestore(&sachip->lock, flags); 1101 1102 sachip->saved_state = NULL; 1103 kfree(save); 1104 1105 return 0; 1106 } 1107 1108 #else 1109 #define sa1111_suspend_noirq NULL 1110 #define sa1111_resume_noirq NULL 1111 #endif 1112 1113 static int sa1111_probe(struct platform_device *pdev) 1114 { 1115 struct resource *mem; 1116 int irq; 1117 1118 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1119 if (!mem) 1120 return -EINVAL; 1121 irq = platform_get_irq(pdev, 0); 1122 if (irq < 0) 1123 return irq; 1124 1125 return __sa1111_probe(&pdev->dev, mem, irq); 1126 } 1127 1128 static int sa1111_remove(struct platform_device *pdev) 1129 { 1130 struct sa1111 *sachip = platform_get_drvdata(pdev); 1131 1132 if (sachip) { 1133 #ifdef CONFIG_PM 1134 kfree(sachip->saved_state); 1135 sachip->saved_state = NULL; 1136 #endif 1137 __sa1111_remove(sachip); 1138 platform_set_drvdata(pdev, NULL); 1139 } 1140 1141 return 0; 1142 } 1143 1144 static struct dev_pm_ops sa1111_pm_ops = { 1145 .suspend_noirq = sa1111_suspend_noirq, 1146 .resume_noirq = sa1111_resume_noirq, 1147 }; 1148 1149 /* 1150 * Not sure if this should be on the system bus or not yet. 1151 * We really want some way to register a system device at 1152 * the per-machine level, and then have this driver pick 1153 * up the registered devices. 1154 * 1155 * We also need to handle the SDRAM configuration for 1156 * PXA250/SA1110 machine classes. 1157 */ 1158 static struct platform_driver sa1111_device_driver = { 1159 .probe = sa1111_probe, 1160 .remove = sa1111_remove, 1161 .driver = { 1162 .name = "sa1111", 1163 .pm = &sa1111_pm_ops, 1164 }, 1165 }; 1166 1167 /* 1168 * Get the parent device driver (us) structure 1169 * from a child function device 1170 */ 1171 static inline struct sa1111 *sa1111_chip_driver(struct sa1111_dev *sadev) 1172 { 1173 return (struct sa1111 *)dev_get_drvdata(sadev->dev.parent); 1174 } 1175 1176 /* 1177 * The bits in the opdiv field are non-linear. 1178 */ 1179 static unsigned char opdiv_table[] = { 1, 4, 2, 8 }; 1180 1181 static unsigned int __sa1111_pll_clock(struct sa1111 *sachip) 1182 { 1183 unsigned int skcdr, fbdiv, ipdiv, opdiv; 1184 1185 skcdr = readl_relaxed(sachip->base + SA1111_SKCDR); 1186 1187 fbdiv = (skcdr & 0x007f) + 2; 1188 ipdiv = ((skcdr & 0x0f80) >> 7) + 2; 1189 opdiv = opdiv_table[(skcdr & 0x3000) >> 12]; 1190 1191 return 3686400 * fbdiv / (ipdiv * opdiv); 1192 } 1193 1194 /** 1195 * sa1111_pll_clock - return the current PLL clock frequency. 1196 * @sadev: SA1111 function block 1197 * 1198 * BUG: we should look at SKCR. We also blindly believe that 1199 * the chip is being fed with the 3.6864MHz clock. 1200 * 1201 * Returns the PLL clock in Hz. 1202 */ 1203 unsigned int sa1111_pll_clock(struct sa1111_dev *sadev) 1204 { 1205 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1206 1207 return __sa1111_pll_clock(sachip); 1208 } 1209 EXPORT_SYMBOL(sa1111_pll_clock); 1210 1211 /** 1212 * sa1111_select_audio_mode - select I2S or AC link mode 1213 * @sadev: SA1111 function block 1214 * @mode: One of %SA1111_AUDIO_ACLINK or %SA1111_AUDIO_I2S 1215 * 1216 * Frob the SKCR to select AC Link mode or I2S mode for 1217 * the audio block. 1218 */ 1219 void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode) 1220 { 1221 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1222 unsigned long flags; 1223 unsigned int val; 1224 1225 spin_lock_irqsave(&sachip->lock, flags); 1226 1227 val = readl_relaxed(sachip->base + SA1111_SKCR); 1228 if (mode == SA1111_AUDIO_I2S) { 1229 val &= ~SKCR_SELAC; 1230 } else { 1231 val |= SKCR_SELAC; 1232 } 1233 writel_relaxed(val, sachip->base + SA1111_SKCR); 1234 1235 spin_unlock_irqrestore(&sachip->lock, flags); 1236 } 1237 EXPORT_SYMBOL(sa1111_select_audio_mode); 1238 1239 /** 1240 * sa1111_set_audio_rate - set the audio sample rate 1241 * @sadev: SA1111 SAC function block 1242 * @rate: sample rate to select 1243 */ 1244 int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate) 1245 { 1246 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1247 unsigned int div; 1248 1249 if (sadev->devid != SA1111_DEVID_SAC) 1250 return -EINVAL; 1251 1252 div = (__sa1111_pll_clock(sachip) / 256 + rate / 2) / rate; 1253 if (div == 0) 1254 div = 1; 1255 if (div > 128) 1256 div = 128; 1257 1258 writel_relaxed(div - 1, sachip->base + SA1111_SKAUD); 1259 1260 return 0; 1261 } 1262 EXPORT_SYMBOL(sa1111_set_audio_rate); 1263 1264 /** 1265 * sa1111_get_audio_rate - get the audio sample rate 1266 * @sadev: SA1111 SAC function block device 1267 */ 1268 int sa1111_get_audio_rate(struct sa1111_dev *sadev) 1269 { 1270 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1271 unsigned long div; 1272 1273 if (sadev->devid != SA1111_DEVID_SAC) 1274 return -EINVAL; 1275 1276 div = readl_relaxed(sachip->base + SA1111_SKAUD) + 1; 1277 1278 return __sa1111_pll_clock(sachip) / (256 * div); 1279 } 1280 EXPORT_SYMBOL(sa1111_get_audio_rate); 1281 1282 /* 1283 * Individual device operations. 1284 */ 1285 1286 /** 1287 * sa1111_enable_device - enable an on-chip SA1111 function block 1288 * @sadev: SA1111 function block device to enable 1289 */ 1290 int sa1111_enable_device(struct sa1111_dev *sadev) 1291 { 1292 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1293 unsigned long flags; 1294 unsigned int val; 1295 int ret = 0; 1296 1297 if (sachip->pdata && sachip->pdata->enable) 1298 ret = sachip->pdata->enable(sachip->pdata->data, sadev->devid); 1299 1300 if (ret == 0) { 1301 spin_lock_irqsave(&sachip->lock, flags); 1302 val = readl_relaxed(sachip->base + SA1111_SKPCR); 1303 writel_relaxed(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR); 1304 spin_unlock_irqrestore(&sachip->lock, flags); 1305 } 1306 return ret; 1307 } 1308 EXPORT_SYMBOL(sa1111_enable_device); 1309 1310 /** 1311 * sa1111_disable_device - disable an on-chip SA1111 function block 1312 * @sadev: SA1111 function block device to disable 1313 */ 1314 void sa1111_disable_device(struct sa1111_dev *sadev) 1315 { 1316 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1317 unsigned long flags; 1318 unsigned int val; 1319 1320 spin_lock_irqsave(&sachip->lock, flags); 1321 val = readl_relaxed(sachip->base + SA1111_SKPCR); 1322 writel_relaxed(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR); 1323 spin_unlock_irqrestore(&sachip->lock, flags); 1324 1325 if (sachip->pdata && sachip->pdata->disable) 1326 sachip->pdata->disable(sachip->pdata->data, sadev->devid); 1327 } 1328 EXPORT_SYMBOL(sa1111_disable_device); 1329 1330 int sa1111_get_irq(struct sa1111_dev *sadev, unsigned num) 1331 { 1332 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1333 if (num >= ARRAY_SIZE(sadev->hwirq)) 1334 return -EINVAL; 1335 return sa1111_map_irq(sachip, sadev->hwirq[num]); 1336 } 1337 EXPORT_SYMBOL_GPL(sa1111_get_irq); 1338 1339 /* 1340 * SA1111 "Register Access Bus." 1341 * 1342 * We model this as a regular bus type, and hang devices directly 1343 * off this. 1344 */ 1345 static int sa1111_match(struct device *_dev, struct device_driver *_drv) 1346 { 1347 struct sa1111_dev *dev = to_sa1111_device(_dev); 1348 struct sa1111_driver *drv = SA1111_DRV(_drv); 1349 1350 return !!(dev->devid & drv->devid); 1351 } 1352 1353 static int sa1111_bus_probe(struct device *dev) 1354 { 1355 struct sa1111_dev *sadev = to_sa1111_device(dev); 1356 struct sa1111_driver *drv = SA1111_DRV(dev->driver); 1357 int ret = -ENODEV; 1358 1359 if (drv->probe) 1360 ret = drv->probe(sadev); 1361 return ret; 1362 } 1363 1364 static int sa1111_bus_remove(struct device *dev) 1365 { 1366 struct sa1111_dev *sadev = to_sa1111_device(dev); 1367 struct sa1111_driver *drv = SA1111_DRV(dev->driver); 1368 int ret = 0; 1369 1370 if (drv->remove) 1371 ret = drv->remove(sadev); 1372 return ret; 1373 } 1374 1375 struct bus_type sa1111_bus_type = { 1376 .name = "sa1111-rab", 1377 .match = sa1111_match, 1378 .probe = sa1111_bus_probe, 1379 .remove = sa1111_bus_remove, 1380 }; 1381 EXPORT_SYMBOL(sa1111_bus_type); 1382 1383 int sa1111_driver_register(struct sa1111_driver *driver) 1384 { 1385 driver->drv.bus = &sa1111_bus_type; 1386 return driver_register(&driver->drv); 1387 } 1388 EXPORT_SYMBOL(sa1111_driver_register); 1389 1390 void sa1111_driver_unregister(struct sa1111_driver *driver) 1391 { 1392 driver_unregister(&driver->drv); 1393 } 1394 EXPORT_SYMBOL(sa1111_driver_unregister); 1395 1396 #ifdef CONFIG_DMABOUNCE 1397 /* 1398 * According to the "Intel StrongARM SA-1111 Microprocessor Companion 1399 * Chip Specification Update" (June 2000), erratum #7, there is a 1400 * significant bug in the SA1111 SDRAM shared memory controller. If 1401 * an access to a region of memory above 1MB relative to the bank base, 1402 * it is important that address bit 10 _NOT_ be asserted. Depending 1403 * on the configuration of the RAM, bit 10 may correspond to one 1404 * of several different (processor-relative) address bits. 1405 * 1406 * This routine only identifies whether or not a given DMA address 1407 * is susceptible to the bug. 1408 * 1409 * This should only get called for sa1111_device types due to the 1410 * way we configure our device dma_masks. 1411 */ 1412 static int sa1111_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) 1413 { 1414 /* 1415 * Section 4.6 of the "Intel StrongARM SA-1111 Development Module 1416 * User's Guide" mentions that jumpers R51 and R52 control the 1417 * target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or 1418 * SDRAM bank 1 on Neponset). The default configuration selects 1419 * Assabet, so any address in bank 1 is necessarily invalid. 1420 */ 1421 return (machine_is_assabet() || machine_is_pfs168()) && 1422 (addr >= 0xc8000000 || (addr + size) >= 0xc8000000); 1423 } 1424 1425 static int sa1111_notifier_call(struct notifier_block *n, unsigned long action, 1426 void *data) 1427 { 1428 struct sa1111_dev *dev = to_sa1111_device(data); 1429 1430 switch (action) { 1431 case BUS_NOTIFY_ADD_DEVICE: 1432 if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL) { 1433 int ret = dmabounce_register_dev(&dev->dev, 1024, 4096, 1434 sa1111_needs_bounce); 1435 if (ret) 1436 dev_err(&dev->dev, "failed to register with dmabounce: %d\n", ret); 1437 } 1438 break; 1439 1440 case BUS_NOTIFY_DEL_DEVICE: 1441 if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL) 1442 dmabounce_unregister_dev(&dev->dev); 1443 break; 1444 } 1445 return NOTIFY_OK; 1446 } 1447 1448 static struct notifier_block sa1111_bus_notifier = { 1449 .notifier_call = sa1111_notifier_call, 1450 }; 1451 #endif 1452 1453 static int __init sa1111_init(void) 1454 { 1455 int ret = bus_register(&sa1111_bus_type); 1456 #ifdef CONFIG_DMABOUNCE 1457 if (ret == 0) 1458 bus_register_notifier(&sa1111_bus_type, &sa1111_bus_notifier); 1459 #endif 1460 if (ret == 0) 1461 platform_driver_register(&sa1111_device_driver); 1462 return ret; 1463 } 1464 1465 static void __exit sa1111_exit(void) 1466 { 1467 platform_driver_unregister(&sa1111_device_driver); 1468 #ifdef CONFIG_DMABOUNCE 1469 bus_unregister_notifier(&sa1111_bus_type, &sa1111_bus_notifier); 1470 #endif 1471 bus_unregister(&sa1111_bus_type); 1472 } 1473 1474 subsys_initcall(sa1111_init); 1475 module_exit(sa1111_exit); 1476 1477 MODULE_DESCRIPTION("Intel Corporation SA1111 core driver"); 1478 MODULE_LICENSE("GPL"); 1479