1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC 4 * 5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> 6 */ 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 compatible = "wm,wm8750"; 12 13 cpus { 14 #address-cells = <0>; 15 #size-cells = <0>; 16 17 cpu { 18 device_type = "cpu"; 19 compatible = "arm,arm1176jzf"; 20 }; 21 }; 22 23 memory { 24 device_type = "memory"; 25 reg = <0x0 0x0>; 26 }; 27 28 aliases { 29 serial0 = &uart0; 30 serial1 = &uart1; 31 serial2 = &uart2; 32 serial3 = &uart3; 33 serial4 = &uart4; 34 serial5 = &uart5; 35 i2c0 = &i2c_0; 36 i2c1 = &i2c_1; 37 }; 38 39 soc { 40 #address-cells = <1>; 41 #size-cells = <1>; 42 compatible = "simple-bus"; 43 ranges; 44 interrupt-parent = <&intc0>; 45 46 intc0: interrupt-controller@d8140000 { 47 compatible = "via,vt8500-intc"; 48 interrupt-controller; 49 reg = <0xd8140000 0x10000>; 50 #interrupt-cells = <1>; 51 }; 52 53 /* Secondary IC cascaded to intc0 */ 54 intc1: interrupt-controller@d8150000 { 55 compatible = "via,vt8500-intc"; 56 interrupt-controller; 57 #interrupt-cells = <1>; 58 reg = <0xD8150000 0x10000>; 59 interrupts = <56 57 58 59 60 61 62 63>; 60 }; 61 62 pinctrl: pinctrl@d8110000 { 63 compatible = "wm,wm8750-pinctrl"; 64 reg = <0xd8110000 0x10000>; 65 interrupt-controller; 66 #interrupt-cells = <2>; 67 gpio-controller; 68 #gpio-cells = <2>; 69 }; 70 71 pmc@d8130000 { 72 compatible = "via,vt8500-pmc"; 73 reg = <0xd8130000 0x1000>; 74 75 clocks { 76 #address-cells = <1>; 77 #size-cells = <0>; 78 79 ref24: ref24M { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <24000000>; 83 }; 84 85 ref25: ref25M { 86 #clock-cells = <0>; 87 compatible = "fixed-clock"; 88 clock-frequency = <25000000>; 89 }; 90 91 plla: plla { 92 #clock-cells = <0>; 93 compatible = "wm,wm8750-pll-clock"; 94 clocks = <&ref25>; 95 reg = <0x200>; 96 }; 97 98 pllb: pllb { 99 #clock-cells = <0>; 100 compatible = "wm,wm8750-pll-clock"; 101 clocks = <&ref25>; 102 reg = <0x204>; 103 }; 104 105 pllc: pllc { 106 #clock-cells = <0>; 107 compatible = "wm,wm8750-pll-clock"; 108 clocks = <&ref25>; 109 reg = <0x208>; 110 }; 111 112 plld: plld { 113 #clock-cells = <0>; 114 compatible = "wm,wm8750-pll-clock"; 115 clocks = <&ref25>; 116 reg = <0x20C>; 117 }; 118 119 plle: plle { 120 #clock-cells = <0>; 121 compatible = "wm,wm8750-pll-clock"; 122 clocks = <&ref25>; 123 reg = <0x210>; 124 }; 125 126 clkarm: arm { 127 #clock-cells = <0>; 128 compatible = "via,vt8500-device-clock"; 129 clocks = <&plla>; 130 divisor-reg = <0x300>; 131 }; 132 133 clkahb: ahb { 134 #clock-cells = <0>; 135 compatible = "via,vt8500-device-clock"; 136 clocks = <&pllb>; 137 divisor-reg = <0x304>; 138 }; 139 140 clkapb: apb { 141 #clock-cells = <0>; 142 compatible = "via,vt8500-device-clock"; 143 clocks = <&pllb>; 144 divisor-reg = <0x320>; 145 }; 146 147 clkddr: ddr { 148 #clock-cells = <0>; 149 compatible = "via,vt8500-device-clock"; 150 clocks = <&plld>; 151 divisor-reg = <0x310>; 152 }; 153 154 clkuart0: uart0 { 155 #clock-cells = <0>; 156 compatible = "via,vt8500-device-clock"; 157 clocks = <&ref24>; 158 enable-reg = <0x254>; 159 enable-bit = <24>; 160 }; 161 162 clkuart1: uart1 { 163 #clock-cells = <0>; 164 compatible = "via,vt8500-device-clock"; 165 clocks = <&ref24>; 166 enable-reg = <0x254>; 167 enable-bit = <25>; 168 }; 169 170 clkuart2: uart2 { 171 #clock-cells = <0>; 172 compatible = "via,vt8500-device-clock"; 173 clocks = <&ref24>; 174 enable-reg = <0x254>; 175 enable-bit = <26>; 176 }; 177 178 clkuart3: uart3 { 179 #clock-cells = <0>; 180 compatible = "via,vt8500-device-clock"; 181 clocks = <&ref24>; 182 enable-reg = <0x254>; 183 enable-bit = <27>; 184 }; 185 186 clkuart4: uart4 { 187 #clock-cells = <0>; 188 compatible = "via,vt8500-device-clock"; 189 clocks = <&ref24>; 190 enable-reg = <0x254>; 191 enable-bit = <28>; 192 }; 193 194 clkuart5: uart5 { 195 #clock-cells = <0>; 196 compatible = "via,vt8500-device-clock"; 197 clocks = <&ref24>; 198 enable-reg = <0x254>; 199 enable-bit = <29>; 200 }; 201 202 clkpwm: pwm { 203 #clock-cells = <0>; 204 compatible = "via,vt8500-device-clock"; 205 clocks = <&pllb>; 206 divisor-reg = <0x350>; 207 enable-reg = <0x250>; 208 enable-bit = <17>; 209 }; 210 211 clksdhc: sdhc { 212 #clock-cells = <0>; 213 compatible = "via,vt8500-device-clock"; 214 clocks = <&pllb>; 215 divisor-reg = <0x330>; 216 divisor-mask = <0x3f>; 217 enable-reg = <0x250>; 218 enable-bit = <0>; 219 }; 220 221 clki2c0: i2c0clk { 222 #clock-cells = <0>; 223 compatible = "via,vt8500-device-clock"; 224 clocks = <&pllb>; 225 divisor-reg = <0x3A0>; 226 enable-reg = <0x250>; 227 enable-bit = <8>; 228 }; 229 230 clki2c1: i2c1clk { 231 #clock-cells = <0>; 232 compatible = "via,vt8500-device-clock"; 233 clocks = <&pllb>; 234 divisor-reg = <0x3A4>; 235 enable-reg = <0x250>; 236 enable-bit = <9>; 237 }; 238 }; 239 }; 240 241 pwm: pwm@d8220000 { 242 #pwm-cells = <3>; 243 compatible = "via,vt8500-pwm"; 244 reg = <0xd8220000 0x100>; 245 clocks = <&clkpwm>; 246 }; 247 248 timer@d8130100 { 249 compatible = "via,vt8500-timer"; 250 reg = <0xd8130100 0x28>; 251 interrupts = <36>; 252 }; 253 254 ehci@d8007900 { 255 compatible = "via,vt8500-ehci"; 256 reg = <0xd8007900 0x200>; 257 interrupts = <26>; 258 }; 259 260 uhci@d8007b00 { 261 compatible = "platform-uhci"; 262 reg = <0xd8007b00 0x200>; 263 interrupts = <26>; 264 }; 265 266 uhci@d8008d00 { 267 compatible = "platform-uhci"; 268 reg = <0xd8008d00 0x200>; 269 interrupts = <26>; 270 }; 271 272 uart0: serial@d8200000 { 273 compatible = "via,vt8500-uart"; 274 reg = <0xd8200000 0x1040>; 275 interrupts = <32>; 276 clocks = <&clkuart0>; 277 status = "disabled"; 278 }; 279 280 uart1: serial@d82b0000 { 281 compatible = "via,vt8500-uart"; 282 reg = <0xd82b0000 0x1040>; 283 interrupts = <33>; 284 clocks = <&clkuart1>; 285 status = "disabled"; 286 }; 287 288 uart2: serial@d8210000 { 289 compatible = "via,vt8500-uart"; 290 reg = <0xd8210000 0x1040>; 291 interrupts = <47>; 292 clocks = <&clkuart2>; 293 status = "disabled"; 294 }; 295 296 uart3: serial@d82c0000 { 297 compatible = "via,vt8500-uart"; 298 reg = <0xd82c0000 0x1040>; 299 interrupts = <50>; 300 clocks = <&clkuart3>; 301 status = "disabled"; 302 }; 303 304 uart4: serial@d8370000 { 305 compatible = "via,vt8500-uart"; 306 reg = <0xd8370000 0x1040>; 307 interrupts = <30>; 308 clocks = <&clkuart4>; 309 status = "disabled"; 310 }; 311 312 uart5: serial@d8380000 { 313 compatible = "via,vt8500-uart"; 314 reg = <0xd8380000 0x1040>; 315 interrupts = <43>; 316 clocks = <&clkuart5>; 317 status = "disabled"; 318 }; 319 320 rtc@d8100000 { 321 compatible = "via,vt8500-rtc"; 322 reg = <0xd8100000 0x10000>; 323 interrupts = <48>; 324 }; 325 326 sdhc@d800a000 { 327 compatible = "wm,wm8505-sdhc"; 328 reg = <0xd800a000 0x1000>; 329 interrupts = <20 21>; 330 clocks = <&clksdhc>; 331 bus-width = <4>; 332 sdon-inverted; 333 }; 334 335 i2c_0: i2c@d8280000 { 336 compatible = "wm,wm8505-i2c"; 337 reg = <0xd8280000 0x1000>; 338 interrupts = <19>; 339 clocks = <&clki2c0>; 340 clock-frequency = <400000>; 341 }; 342 343 i2c_1: i2c@d8320000 { 344 compatible = "wm,wm8505-i2c"; 345 reg = <0xd8320000 0x1000>; 346 interrupts = <18>; 347 clocks = <&clki2c1>; 348 clock-frequency = <400000>; 349 }; 350 }; 351}; 352