1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com> 4 */ 5/dts-v1/; 6 7#include "omap3-lilly-a83x.dtsi" 8 9/ { 10 model = "INCOstartec LILLY-DBB056 (DM3730)"; 11 compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap3"; 12}; 13 14&twl { 15 vaux2: regulator-vaux2 { 16 compatible = "ti,twl4030-vaux2"; 17 regulator-min-microvolt = <2800000>; 18 regulator-max-microvolt = <2800000>; 19 regulator-always-on; 20 }; 21}; 22 23&omap3_pmx_core { 24 pinctrl-names = "default"; 25 pinctrl-0 = <&lcd_pins>; 26 27 lan9117_pins: lan9117-pins { 28 pinctrl-single,pins = < 29 OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */ 30 >; 31 }; 32 33 gpio4_pins: gpio4-pins { 34 pinctrl-single,pins = < 35 OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */ 36 >; 37 }; 38 39 gpio5_pins: gpio5-pins { 40 pinctrl-single,pins = < 41 OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -> enable DSS */ 42 >; 43 }; 44 45 lcd_pins: lcd-pins { 46 pinctrl-single,pins = < 47 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 48 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 49 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 50 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 51 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ 52 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ 53 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ 54 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ 55 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ 56 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ 57 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ 58 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ 59 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ 60 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ 61 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ 62 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ 63 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ 64 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ 65 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ 66 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ 67 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ 68 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ 69 >; 70 }; 71 72 mmc2_pins: mmc2-pins { 73 pinctrl-single,pins = < 74 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ 75 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ 76 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ 77 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ 78 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ 79 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ 80 OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ 81 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ 82 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ 83 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ 84 OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 -> wp */ 85 OMAP3_CORE1_IOPAD(0x219c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_rts_sd.gpio_164 -> cd */ 86 >; 87 }; 88 89 spi1_pins: spi1-pins { 90 pinctrl-single,pins = < 91 OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ 92 OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ 93 OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ 94 OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ 95 >; 96 }; 97}; 98 99&gpio4 { 100 pinctrl-names = "default"; 101 pinctrl-0 = <&gpio4_pins>; 102}; 103 104&gpio5 { 105 pinctrl-names = "default"; 106 pinctrl-0 = <&gpio5_pins>; 107}; 108 109&mmc2 { 110 status = "okay"; 111 bus-width = <4>; 112 vmmc-supply = <&vmmc1>; 113 cd-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164 */ 114 wp-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* gpio_163 */ 115 pinctrl-names = "default"; 116 pinctrl-0 = <&mmc2_pins>; 117 ti,dual-volt; 118}; 119 120&mcspi1 { 121 status = "okay"; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&spi1_pins>; 124}; 125 126&gpmc { 127 ranges = <0 0 0x30000000 0x1000000>, /* nand assigned by COM a83x */ 128 <4 0 0x20000000 0x01000000>, 129 <7 0 0x15000000 0x01000000>; /* eth assigend by COM a83x */ 130 131 ethernet@4,0 { 132 compatible = "smsc,lan9117", "smsc,lan9115"; 133 bank-width = <2>; 134 gpmc,mux-add-data = <2>; 135 gpmc,cs-on-ns = <10>; 136 gpmc,cs-rd-off-ns = <65>; 137 gpmc,cs-wr-off-ns = <65>; 138 gpmc,adv-on-ns = <0>; 139 gpmc,adv-rd-off-ns = <10>; 140 gpmc,adv-wr-off-ns = <10>; 141 gpmc,oe-on-ns = <10>; 142 gpmc,oe-off-ns = <65>; 143 gpmc,we-on-ns = <10>; 144 gpmc,we-off-ns = <65>; 145 gpmc,rd-cycle-ns = <100>; 146 gpmc,wr-cycle-ns = <100>; 147 gpmc,access-ns = <60>; 148 gpmc,page-burst-access-ns = <5>; 149 gpmc,bus-turnaround-ns = <0>; 150 gpmc,cycle2cycle-delay-ns = <75>; 151 gpmc,wr-data-mux-bus-ns = <15>; 152 gpmc,wr-access-ns = <75>; 153 gpmc,cycle2cycle-samecsen; 154 gpmc,cycle2cycle-diffcsen; 155 vddvario-supply = <®_vcc3>; 156 vdd33a-supply = <®_vcc3>; 157 reg-io-width = <4>; 158 interrupt-parent = <&gpio4>; 159 interrupts = <2 0x2>; 160 reg = <4 0 0xff>; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&lan9117_pins>; 163 phy-mode = "mii"; 164 smsc,force-internal-phy; 165 }; 166}; 167