1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6#include "dra74x.dtsi" 7 8/ { 9 compatible = "ti,dra762", "ti,dra7"; 10 11 ocp { 12 target-module@42c01900 { 13 compatible = "ti,sysc-dra7-mcan", "ti,sysc"; 14 ranges = <0x0 0x42c00000 0x2000>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 reg = <0x42c01900 0x4>, 18 <0x42c01904 0x4>, 19 <0x42c01908 0x4>; 20 reg-names = "rev", "sysc", "syss"; 21 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET | 22 SYSC_DRA7_MCAN_ENAWAKEUP)>; 23 ti,syss-mask = <1>; 24 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>; 25 clock-names = "fck"; 26 27 m_can0: mcan@1a00 { 28 compatible = "bosch,m_can"; 29 reg = <0x1a00 0x4000>, <0x0 0x18FC>; 30 reg-names = "m_can", "message_ram"; 31 interrupt-parent = <&gic>; 32 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 34 interrupt-names = "int0", "int1"; 35 clocks = <&l3_iclk_div>, <&mcan_clk>; 36 clock-names = "hclk", "cclk"; 37 bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>; 38 }; 39 }; 40 }; 41 42}; 43 44&l4_per3 { 45 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ 46 compatible = "ti,sysc-omap4", "ti,sysc"; 47 reg = <0x1b0000 0x4>, 48 <0x1b0010 0x4>; 49 reg-names = "rev", "sysc"; 50 ti,sysc-midle = <SYSC_IDLE_FORCE>, 51 <SYSC_IDLE_NO>; 52 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 53 <SYSC_IDLE_NO>; 54 clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; 55 clock-names = "fck"; 56 #address-cells = <1>; 57 #size-cells = <1>; 58 ranges = <0x0 0x1b0000 0x10000>; 59 60 cal: cal@0 { 61 compatible = "ti,dra76-cal"; 62 reg = <0x0000 0x400>, 63 <0x0800 0x40>, 64 <0x0900 0x40>; 65 reg-names = "cal_top", 66 "cal_rx_core0", 67 "cal_rx_core1"; 68 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 69 ti,camerrx-control = <&scm_conf 0x6dc>; 70 71 ports { 72 #address-cells = <1>; 73 #size-cells = <0>; 74 75 csi2_0: port@0 { 76 reg = <0>; 77 }; 78 csi2_1: port@1 { 79 reg = <1>; 80 }; 81 }; 82 }; 83 }; 84}; 85 86&scm_conf_clocks { 87 dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc { 88 #clock-cells = <0>; 89 compatible = "ti,divider-clock"; 90 clocks = <&dpll_gmac_x2_ck>; 91 ti,max-div = <63>; 92 reg = <0x03fc>; 93 ti,bit-shift = <20>; 94 ti,latch-bit = <26>; 95 assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; 96 assigned-clock-rates = <80000000>; 97 }; 98 99 dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc { 100 #clock-cells = <0>; 101 compatible = "ti,mux-clock"; 102 clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; 103 reg = <0x3fc>; 104 ti,bit-shift = <29>; 105 ti,latch-bit = <26>; 106 assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; 107 assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; 108 }; 109 110 mcan_clk: mcan_clk@3fc { 111 #clock-cells = <0>; 112 compatible = "ti,gate-clock"; 113 clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; 114 ti,bit-shift = <27>; 115 reg = <0x3fc>; 116 }; 117}; 118 119&rtctarget { 120 status = "disabled"; 121}; 122 123&usb4_tm { 124 status = "disabled"; 125}; 126 127&mmc3 { 128 /* dra76x is not affected by i887 */ 129 max-frequency = <96000000>; 130}; 131 132&cpu0_opp_table { 133 opp-1800000000 { 134 /* OPP Plus */ 135 opp-hz = /bits/ 64 <1800000000>; 136 opp-microvolt = <1250000 950000 1250000>, 137 <1250000 950000 1250000>; 138 opp-supported-hw = <0xFF 0x08>; 139 }; 140}; 141 142&opp_supply_mpu { 143 ti,efuse-settings = < 144 /* uV offset */ 145 1060000 0x0 146 1160000 0x4 147 1210000 0x8 148 1250000 0xC 149 >; 150}; 151 152&abb_mpu { 153 ti,abb_info = < 154 /*uV ABB efuse rbb_m fbb_m vset_m*/ 155 1060000 0 0x0 0 0x02000000 0x01F00000 156 1160000 0 0x4 0 0x02000000 0x01F00000 157 1210000 0 0x8 0 0x02000000 0x01F00000 158 1250000 0 0xC 0 0x02000000 0x01F00000 159 >; 160}; 161