1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring 3*724ba675SRob Herring#include "dm814x-clocks.dtsi" 4*724ba675SRob Herring 5*724ba675SRob Herring/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */ 6*724ba675SRob Herring&adpll_hdvic_ck { 7*724ba675SRob Herring status = "disabled"; 8*724ba675SRob Herring}; 9*724ba675SRob Herring 10*724ba675SRob Herring&adpll_l3_ck { 11*724ba675SRob Herring status = "disabled"; 12*724ba675SRob Herring}; 13*724ba675SRob Herring 14*724ba675SRob Herring&adpll_dss_ck { 15*724ba675SRob Herring status = "disabled"; 16*724ba675SRob Herring}; 17*724ba675SRob Herring 18*724ba675SRob Herring/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */ 19*724ba675SRob Herring&sysclk4_ck { 20*724ba675SRob Herring clocks = <&adpll_isp_ck 1>; 21*724ba675SRob Herring}; 22*724ba675SRob Herring 23*724ba675SRob Herring&sysclk5_ck { 24*724ba675SRob Herring clocks = <&adpll_isp_ck 1>; 25*724ba675SRob Herring}; 26*724ba675SRob Herring 27*724ba675SRob Herring&sysclk6_ck { 28*724ba675SRob Herring clocks = <&adpll_isp_ck 1>; 29*724ba675SRob Herring}; 30*724ba675SRob Herring 31*724ba675SRob Herring/* 32*724ba675SRob Herring * Compared to dm814x, dra62x has different shifts and more mux options. 33*724ba675SRob Herring * Please add the extra options for ysclk_14 and 16 if really needed. 34*724ba675SRob Herring */ 35*724ba675SRob Herring&timer1_fck { 36*724ba675SRob Herring clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck 37*724ba675SRob Herring &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; 38*724ba675SRob Herring ti,bit-shift = <4>; 39*724ba675SRob Herring}; 40*724ba675SRob Herring 41*724ba675SRob Herring&timer2_fck { 42*724ba675SRob Herring clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck 43*724ba675SRob Herring &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; 44*724ba675SRob Herring ti,bit-shift = <8>; 45*724ba675SRob Herring}; 46