1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Device Tree Source for am3517 SoC 4 * 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include "omap3.dtsi" 9 10/* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */ 11/delete-node/ &aes1_target; 12/delete-node/ &aes2_target; 13 14/ { 15 aliases { 16 serial3 = &uart4; 17 can = &hecc; 18 }; 19 20 cpus { 21 cpu: cpu@0 { 22 /* Based on OMAP3630 variants OPP50 and OPP100 */ 23 operating-points-v2 = <&cpu0_opp_table>; 24 25 clock-latency = <300000>; /* From legacy driver */ 26 }; 27 }; 28 29 cpu0_opp_table: opp-table { 30 compatible = "operating-points-v2-ti-cpu"; 31 syscon = <&scm_conf>; 32 /* 33 * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx 34 * appear to operate at 300MHz as well. Since AM3517 only 35 * lists one operating voltage, it will remain fixed at 1.2V 36 */ 37 opp50-300000000 { 38 opp-hz = /bits/ 64 <300000000>; 39 opp-microvolt = <1200000>; 40 opp-supported-hw = <0xffffffff 0xffffffff>; 41 opp-suspend; 42 }; 43 44 opp100-600000000 { 45 opp-hz = /bits/ 64 <600000000>; 46 opp-microvolt = <1200000>; 47 opp-supported-hw = <0xffffffff 0xffffffff>; 48 }; 49 }; 50 51 ocp@68000000 { 52 target-module@5c040000 { 53 compatible = "ti,sysc-omap2", "ti,sysc"; 54 reg = <0x5c040400 0x4>, 55 <0x5c040404 0x4>, 56 <0x5c040408 0x4>; 57 reg-names = "rev", "sysc", "syss"; 58 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 59 SYSC_OMAP2_SOFTRESET | 60 SYSC_OMAP2_AUTOIDLE)>; 61 ti,sysc-midle = <SYSC_IDLE_FORCE>, 62 <SYSC_IDLE_NO>, 63 <SYSC_IDLE_SMART>; 64 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 65 <SYSC_IDLE_NO>, 66 <SYSC_IDLE_SMART>; 67 ti,syss-mask = <1>; 68 clocks = <&hsotgusb_ick_am35xx>; 69 clock-names = "fck"; 70 #address-cells = <1>; 71 #size-cells = <1>; 72 ranges = <0x0 0x5c040000 0x1000>; 73 74 am35x_otg_hs: am35x_otg_hs@0 { 75 compatible = "ti,omap3-musb"; 76 status = "disabled"; 77 reg = <0 0x1000>; 78 interrupts = <71>; 79 interrupt-names = "mc"; 80 }; 81 }; 82 83 davinci_emac: ethernet@5c000000 { 84 compatible = "ti,am3517-emac"; 85 ti,hwmods = "davinci_emac"; 86 status = "disabled"; 87 reg = <0x5c000000 0x30000>; 88 interrupts = <67 68 69 70>; 89 syscon = <&scm_conf>; 90 ti,davinci-ctrl-reg-offset = <0x10000>; 91 ti,davinci-ctrl-mod-reg-offset = <0>; 92 ti,davinci-ctrl-ram-offset = <0x20000>; 93 ti,davinci-ctrl-ram-size = <0x2000>; 94 ti,davinci-rmii-en = /bits/ 8 <1>; 95 local-mac-address = [ 00 00 00 00 00 00 ]; 96 clocks = <&emac_ick>; 97 clock-names = "ick"; 98 }; 99 100 davinci_mdio: mdio@5c030000 { 101 compatible = "ti,davinci_mdio"; 102 ti,hwmods = "davinci_mdio"; 103 status = "disabled"; 104 reg = <0x5c030000 0x1000>; 105 bus_freq = <1000000>; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 clocks = <&emac_fck>; 109 clock-names = "fck"; 110 }; 111 112 uart4: serial@4809e000 { 113 compatible = "ti,omap3-uart"; 114 ti,hwmods = "uart4"; 115 status = "disabled"; 116 reg = <0x4809e000 0x400>; 117 interrupts = <84>; 118 dmas = <&sdma 55 &sdma 54>; 119 dma-names = "tx", "rx"; 120 clock-frequency = <48000000>; 121 }; 122 123 omap3_pmx_core2: pinmux@480025d8 { 124 compatible = "ti,omap3-padconf", "pinctrl-single"; 125 reg = <0x480025d8 0x24>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 #pinctrl-cells = <1>; 129 #interrupt-cells = <1>; 130 interrupt-controller; 131 pinctrl-single,register-width = <16>; 132 pinctrl-single,function-mask = <0xff1f>; 133 }; 134 135 hecc: can@5c050000 { 136 compatible = "ti,am3517-hecc"; 137 status = "disabled"; 138 reg = <0x5c050000 0x80>, 139 <0x5c053000 0x180>, 140 <0x5c052000 0x200>; 141 reg-names = "hecc", "hecc-ram", "mbx"; 142 interrupts = <24>; 143 clocks = <&hecc_ck>; 144 }; 145 146 /* 147 * On am3517 the OCP registers do not seem to be accessible 148 * similar to the omap34xx. Maybe SGX is permanently set to 149 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is 150 * write-only at 0x50000e10. We detect SGX based on the SGX 151 * revision register instead of the unreadable OCP revision 152 * register. 153 */ 154 sgx_module: target-module@50000000 { 155 compatible = "ti,sysc-omap2", "ti,sysc"; 156 reg = <0x50000014 0x4>; 157 reg-names = "rev"; 158 clocks = <&sgx_fck>, <&sgx_ick>; 159 clock-names = "fck", "ick"; 160 #address-cells = <1>; 161 #size-cells = <1>; 162 ranges = <0 0x50000000 0x4000>; 163 164 /* 165 * Closed source PowerVR driver, no child device 166 * binding or driver in mainline 167 */ 168 }; 169 }; 170}; 171 172/* Not currently working, probably needs at least different clocks */ 173&rng_target { 174 status = "disabled"; 175 /delete-property/ clocks; 176}; 177 178/* Table Table 5-79 of the TRM shows 480ab000 is reserved */ 179&usb_otg_target { 180 status = "disabled"; 181}; 182 183&iva { 184 status = "disabled"; 185}; 186 187&mailbox { 188 status = "disabled"; 189}; 190 191&mmu_isp { 192 status = "disabled"; 193}; 194 195#include "am35xx-clocks.dtsi" 196#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" 197 198/* Preferred always-on timer for clocksource */ 199&timer1_target { 200 ti,no-reset-on-init; 201 ti,no-idle; 202 timer@0 { 203 assigned-clocks = <&gpt1_fck>; 204 assigned-clock-parents = <&sys_ck>; 205 }; 206}; 207 208/* Preferred timer for clockevent */ 209&timer2_target { 210 ti,no-reset-on-init; 211 ti,no-idle; 212 timer@0 { 213 assigned-clocks = <&gpt2_fck>; 214 assigned-clock-parents = <&sys_ck>; 215 }; 216}; 217