1724ba675SRob Herring&l4_wkup { /* 0x44c00000 */ 2724ba675SRob Herring compatible = "ti,am33xx-l4-wkup", "simple-pm-bus"; 3724ba675SRob Herring power-domains = <&prm_wkup>; 4724ba675SRob Herring clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; 5724ba675SRob Herring clock-names = "fck"; 6724ba675SRob Herring reg = <0x44c00000 0x800>, 7724ba675SRob Herring <0x44c00800 0x800>, 8724ba675SRob Herring <0x44c01000 0x400>, 9724ba675SRob Herring <0x44c01400 0x400>; 10724ba675SRob Herring reg-names = "ap", "la", "ia0", "ia1"; 11724ba675SRob Herring #address-cells = <1>; 12724ba675SRob Herring #size-cells = <1>; 13724ba675SRob Herring ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ 14724ba675SRob Herring <0x00100000 0x44d00000 0x100000>, /* segment 1 */ 15724ba675SRob Herring <0x00200000 0x44e00000 0x100000>; /* segment 2 */ 16724ba675SRob Herring 17724ba675SRob Herring segment@0 { /* 0x44c00000 */ 18724ba675SRob Herring compatible = "simple-pm-bus"; 19724ba675SRob Herring #address-cells = <1>; 20724ba675SRob Herring #size-cells = <1>; 21724ba675SRob Herring ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 22724ba675SRob Herring <0x00000800 0x00000800 0x000800>, /* ap 1 */ 23724ba675SRob Herring <0x00001000 0x00001000 0x000400>, /* ap 2 */ 24724ba675SRob Herring <0x00001400 0x00001400 0x000400>; /* ap 3 */ 25724ba675SRob Herring }; 26724ba675SRob Herring 27724ba675SRob Herring segment@100000 { /* 0x44d00000 */ 28724ba675SRob Herring compatible = "simple-pm-bus"; 29724ba675SRob Herring #address-cells = <1>; 30724ba675SRob Herring #size-cells = <1>; 31724ba675SRob Herring ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ 32724ba675SRob Herring <0x00004000 0x00104000 0x001000>, /* ap 5 */ 33724ba675SRob Herring <0x00080000 0x00180000 0x002000>, /* ap 6 */ 34724ba675SRob Herring <0x00082000 0x00182000 0x001000>; /* ap 7 */ 35724ba675SRob Herring 36724ba675SRob Herring target-module@0 { /* 0x44d00000, ap 4 28.0 */ 37724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 38724ba675SRob Herring reg = <0x0 0x4>; 39724ba675SRob Herring reg-names = "rev"; 40724ba675SRob Herring clocks = <&l4_wkup_aon_clkctrl AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; 41724ba675SRob Herring clock-names = "fck"; 42724ba675SRob Herring #address-cells = <1>; 43724ba675SRob Herring #size-cells = <1>; 44724ba675SRob Herring ranges = <0x00000000 0x00000000 0x4000>, 45724ba675SRob Herring <0x00080000 0x00080000 0x2000>; 46724ba675SRob Herring 47724ba675SRob Herring wkup_m3: cpu@0 { 48724ba675SRob Herring compatible = "ti,am3352-wkup-m3"; 49724ba675SRob Herring reg = <0x00000000 0x4000>, 50724ba675SRob Herring <0x00080000 0x2000>; 51724ba675SRob Herring reg-names = "umem", "dmem"; 52724ba675SRob Herring resets = <&prm_wkup 3>; 53724ba675SRob Herring reset-names = "rstctrl"; 54724ba675SRob Herring ti,pm-firmware = "am335x-pm-firmware.elf"; 55724ba675SRob Herring }; 56724ba675SRob Herring }; 57724ba675SRob Herring }; 58724ba675SRob Herring 59724ba675SRob Herring segment@200000 { /* 0x44e00000 */ 60724ba675SRob Herring compatible = "simple-pm-bus"; 61724ba675SRob Herring #address-cells = <1>; 62724ba675SRob Herring #size-cells = <1>; 63724ba675SRob Herring ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */ 64724ba675SRob Herring <0x00002000 0x00202000 0x001000>, /* ap 9 */ 65724ba675SRob Herring <0x00003000 0x00203000 0x001000>, /* ap 10 */ 66724ba675SRob Herring <0x00004000 0x00204000 0x001000>, /* ap 11 */ 67724ba675SRob Herring <0x00005000 0x00205000 0x001000>, /* ap 12 */ 68724ba675SRob Herring <0x00006000 0x00206000 0x001000>, /* ap 13 */ 69724ba675SRob Herring <0x00007000 0x00207000 0x001000>, /* ap 14 */ 70724ba675SRob Herring <0x00008000 0x00208000 0x001000>, /* ap 15 */ 71724ba675SRob Herring <0x00009000 0x00209000 0x001000>, /* ap 16 */ 72724ba675SRob Herring <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ 73724ba675SRob Herring <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ 74724ba675SRob Herring <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ 75724ba675SRob Herring <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ 76724ba675SRob Herring <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ 77724ba675SRob Herring <0x00010000 0x00210000 0x010000>, /* ap 22 */ 78724ba675SRob Herring <0x00020000 0x00220000 0x010000>, /* ap 23 */ 79724ba675SRob Herring <0x00030000 0x00230000 0x001000>, /* ap 24 */ 80724ba675SRob Herring <0x00031000 0x00231000 0x001000>, /* ap 25 */ 81724ba675SRob Herring <0x00032000 0x00232000 0x001000>, /* ap 26 */ 82724ba675SRob Herring <0x00033000 0x00233000 0x001000>, /* ap 27 */ 83724ba675SRob Herring <0x00034000 0x00234000 0x001000>, /* ap 28 */ 84724ba675SRob Herring <0x00035000 0x00235000 0x001000>, /* ap 29 */ 85724ba675SRob Herring <0x00036000 0x00236000 0x001000>, /* ap 30 */ 86724ba675SRob Herring <0x00037000 0x00237000 0x001000>, /* ap 31 */ 87724ba675SRob Herring <0x00038000 0x00238000 0x001000>, /* ap 32 */ 88724ba675SRob Herring <0x00039000 0x00239000 0x001000>, /* ap 33 */ 89724ba675SRob Herring <0x0003a000 0x0023a000 0x001000>, /* ap 34 */ 90724ba675SRob Herring <0x0003e000 0x0023e000 0x001000>, /* ap 35 */ 91724ba675SRob Herring <0x0003f000 0x0023f000 0x001000>, /* ap 36 */ 92724ba675SRob Herring <0x0000e000 0x0020e000 0x001000>, /* ap 37 */ 93724ba675SRob Herring <0x00040000 0x00240000 0x040000>, /* ap 38 */ 94724ba675SRob Herring <0x00080000 0x00280000 0x001000>; /* ap 39 */ 95724ba675SRob Herring 96724ba675SRob Herring target-module@0 { /* 0x44e00000, ap 8 58.0 */ 97724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 98724ba675SRob Herring reg = <0 0x4>; 99724ba675SRob Herring reg-names = "rev"; 100724ba675SRob Herring #address-cells = <1>; 101724ba675SRob Herring #size-cells = <1>; 102724ba675SRob Herring ranges = <0x0 0x0 0x2000>; 103724ba675SRob Herring 104724ba675SRob Herring prcm: prcm@0 { 105724ba675SRob Herring compatible = "ti,am3-prcm", "simple-bus"; 106724ba675SRob Herring reg = <0 0x2000>; 107724ba675SRob Herring #address-cells = <1>; 108724ba675SRob Herring #size-cells = <1>; 109724ba675SRob Herring ranges = <0 0 0x2000>; 110724ba675SRob Herring 111724ba675SRob Herring prcm_clocks: clocks { 112724ba675SRob Herring #address-cells = <1>; 113724ba675SRob Herring #size-cells = <0>; 114724ba675SRob Herring }; 115724ba675SRob Herring 116724ba675SRob Herring prcm_clockdomains: clockdomains { 117724ba675SRob Herring }; 118724ba675SRob Herring }; 119724ba675SRob Herring }; 120724ba675SRob Herring 121724ba675SRob Herring target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ 122724ba675SRob Herring compatible = "ti,sysc"; 123724ba675SRob Herring status = "disabled"; 124724ba675SRob Herring #address-cells = <1>; 125724ba675SRob Herring #size-cells = <1>; 126724ba675SRob Herring ranges = <0x0 0x3000 0x1000>; 127724ba675SRob Herring }; 128724ba675SRob Herring 129724ba675SRob Herring target-module@5000 { /* 0x44e05000, ap 12 30.0 */ 130724ba675SRob Herring compatible = "ti,sysc"; 131724ba675SRob Herring status = "disabled"; 132724ba675SRob Herring #address-cells = <1>; 133724ba675SRob Herring #size-cells = <1>; 134724ba675SRob Herring ranges = <0x0 0x5000 0x1000>; 135724ba675SRob Herring }; 136724ba675SRob Herring 137724ba675SRob Herring gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ 138724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 139724ba675SRob Herring reg = <0x7000 0x4>, 140724ba675SRob Herring <0x7010 0x4>, 141724ba675SRob Herring <0x7114 0x4>; 142724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 143724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 144724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 145724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 146724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 147724ba675SRob Herring <SYSC_IDLE_NO>, 148724ba675SRob Herring <SYSC_IDLE_SMART>, 149724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 150724ba675SRob Herring ti,syss-mask = <1>; 151724ba675SRob Herring /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 152724ba675SRob Herring clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>, 153724ba675SRob Herring <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>; 154724ba675SRob Herring clock-names = "fck", "dbclk"; 155724ba675SRob Herring #address-cells = <1>; 156724ba675SRob Herring #size-cells = <1>; 157724ba675SRob Herring ranges = <0x0 0x7000 0x1000>; 158724ba675SRob Herring 159724ba675SRob Herring gpio0: gpio@0 { 160724ba675SRob Herring compatible = "ti,omap4-gpio"; 161724ba675SRob Herring gpio-ranges = <&am33xx_pinmux 0 82 8>, 162724ba675SRob Herring <&am33xx_pinmux 8 52 4>, 163724ba675SRob Herring <&am33xx_pinmux 12 94 4>, 164724ba675SRob Herring <&am33xx_pinmux 16 71 2>, 165724ba675SRob Herring <&am33xx_pinmux 18 135 1>, 166724ba675SRob Herring <&am33xx_pinmux 19 108 2>, 167724ba675SRob Herring <&am33xx_pinmux 21 73 1>, 168724ba675SRob Herring <&am33xx_pinmux 22 8 2>, 169724ba675SRob Herring <&am33xx_pinmux 26 10 2>, 170724ba675SRob Herring <&am33xx_pinmux 28 74 1>, 171724ba675SRob Herring <&am33xx_pinmux 29 81 1>, 172724ba675SRob Herring <&am33xx_pinmux 30 28 2>; 173724ba675SRob Herring gpio-controller; 174724ba675SRob Herring #gpio-cells = <2>; 175724ba675SRob Herring interrupt-controller; 176724ba675SRob Herring #interrupt-cells = <2>; 177724ba675SRob Herring reg = <0x0 0x1000>; 178724ba675SRob Herring interrupts = <96>; 179724ba675SRob Herring }; 180724ba675SRob Herring }; 181724ba675SRob Herring 182724ba675SRob Herring target-module@9000 { /* 0x44e09000, ap 16 04.0 */ 183724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 184724ba675SRob Herring reg = <0x9050 0x4>, 185724ba675SRob Herring <0x9054 0x4>, 186724ba675SRob Herring <0x9058 0x4>; 187724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 188724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 189724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 190724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 191724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 192724ba675SRob Herring <SYSC_IDLE_NO>, 193724ba675SRob Herring <SYSC_IDLE_SMART>, 194724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 195724ba675SRob Herring /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 196724ba675SRob Herring clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>; 197724ba675SRob Herring clock-names = "fck"; 198724ba675SRob Herring #address-cells = <1>; 199724ba675SRob Herring #size-cells = <1>; 200724ba675SRob Herring ranges = <0x0 0x9000 0x1000>; 201724ba675SRob Herring 202724ba675SRob Herring uart0: serial@0 { 203724ba675SRob Herring compatible = "ti,am3352-uart", "ti,omap3-uart"; 204724ba675SRob Herring clock-frequency = <48000000>; 205724ba675SRob Herring reg = <0x0 0x1000>; 206724ba675SRob Herring interrupts = <72>; 207724ba675SRob Herring status = "disabled"; 208724ba675SRob Herring dmas = <&edma 26 0>, <&edma 27 0>; 209724ba675SRob Herring dma-names = "tx", "rx"; 210724ba675SRob Herring }; 211724ba675SRob Herring }; 212724ba675SRob Herring 213724ba675SRob Herring target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ 214724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 215724ba675SRob Herring reg = <0xb000 0x8>, 216724ba675SRob Herring <0xb010 0x8>, 217724ba675SRob Herring <0xb090 0x8>; 218724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 219724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 220724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 221724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 222724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 223724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 224724ba675SRob Herring <SYSC_IDLE_NO>, 225724ba675SRob Herring <SYSC_IDLE_SMART>, 226724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 227724ba675SRob Herring ti,syss-mask = <1>; 228724ba675SRob Herring /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 229724ba675SRob Herring clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>; 230724ba675SRob Herring clock-names = "fck"; 231724ba675SRob Herring #address-cells = <1>; 232724ba675SRob Herring #size-cells = <1>; 233724ba675SRob Herring ranges = <0x0 0xb000 0x1000>; 234724ba675SRob Herring 235724ba675SRob Herring i2c0: i2c@0 { 236724ba675SRob Herring compatible = "ti,omap4-i2c"; 237724ba675SRob Herring #address-cells = <1>; 238724ba675SRob Herring #size-cells = <0>; 239724ba675SRob Herring reg = <0x0 0x1000>; 240724ba675SRob Herring interrupts = <70>; 241724ba675SRob Herring status = "disabled"; 242724ba675SRob Herring }; 243724ba675SRob Herring }; 244724ba675SRob Herring 245724ba675SRob Herring target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ 246724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 247724ba675SRob Herring reg = <0xd000 0x4>, 248724ba675SRob Herring <0xd010 0x4>; 249724ba675SRob Herring reg-names = "rev", "sysc"; 250724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 251724ba675SRob Herring <SYSC_IDLE_NO>, 252724ba675SRob Herring <SYSC_IDLE_SMART>, 253724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 254724ba675SRob Herring /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 255724ba675SRob Herring clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>; 256724ba675SRob Herring clock-names = "fck"; 257724ba675SRob Herring #address-cells = <1>; 258724ba675SRob Herring #size-cells = <1>; 259724ba675SRob Herring ranges = <0x00000000 0x0000d000 0x00001000>, 260724ba675SRob Herring <0x00001000 0x0000e000 0x00001000>; 261724ba675SRob Herring 262724ba675SRob Herring tscadc: tscadc@0 { 263724ba675SRob Herring compatible = "ti,am3359-tscadc"; 264724ba675SRob Herring reg = <0x0 0x1000>; 265724ba675SRob Herring interrupts = <16>; 266724ba675SRob Herring clocks = <&adc_tsc_fck>; 267724ba675SRob Herring clock-names = "fck"; 268724ba675SRob Herring status = "disabled"; 269724ba675SRob Herring dmas = <&edma 53 0>, <&edma 57 0>; 270724ba675SRob Herring dma-names = "fifo0", "fifo1"; 271724ba675SRob Herring 272724ba675SRob Herring tsc { 273724ba675SRob Herring compatible = "ti,am3359-tsc"; 274724ba675SRob Herring }; 275724ba675SRob Herring am335x_adc: adc { 276724ba675SRob Herring #io-channel-cells = <1>; 277724ba675SRob Herring compatible = "ti,am3359-adc"; 278724ba675SRob Herring }; 279724ba675SRob Herring }; 280724ba675SRob Herring }; 281724ba675SRob Herring 282724ba675SRob Herring target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ 283724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 284724ba675SRob Herring reg = <0x10000 0x4>; 285724ba675SRob Herring reg-names = "rev"; 286724ba675SRob Herring clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_CONTROL_CLKCTRL 0>; 287724ba675SRob Herring clock-names = "fck"; 288724ba675SRob Herring ti,no-idle; 289724ba675SRob Herring #address-cells = <1>; 290724ba675SRob Herring #size-cells = <1>; 291724ba675SRob Herring ranges = <0x00000000 0x00010000 0x00010000>, 292724ba675SRob Herring <0x00010000 0x00020000 0x00010000>; 293724ba675SRob Herring 294724ba675SRob Herring scm: scm@0 { 295724ba675SRob Herring compatible = "ti,am3-scm", "simple-bus"; 296724ba675SRob Herring reg = <0x0 0x2000>; 297724ba675SRob Herring #address-cells = <1>; 298724ba675SRob Herring #size-cells = <1>; 299724ba675SRob Herring #pinctrl-cells = <1>; 300724ba675SRob Herring ranges = <0 0 0x2000>; 301724ba675SRob Herring 302724ba675SRob Herring am33xx_pinmux: pinmux@800 { 303724ba675SRob Herring compatible = "pinctrl-single"; 304724ba675SRob Herring reg = <0x800 0x238>; 305724ba675SRob Herring #pinctrl-cells = <2>; 306724ba675SRob Herring pinctrl-single,register-width = <32>; 307724ba675SRob Herring pinctrl-single,function-mask = <0x7f>; 308724ba675SRob Herring }; 309724ba675SRob Herring 310724ba675SRob Herring scm_conf: scm_conf@0 { 311724ba675SRob Herring compatible = "syscon", "simple-bus"; 312724ba675SRob Herring reg = <0x0 0x800>; 313724ba675SRob Herring #address-cells = <1>; 314724ba675SRob Herring #size-cells = <1>; 315724ba675SRob Herring ranges = <0 0 0x800>; 316724ba675SRob Herring 317724ba675SRob Herring phy_gmii_sel: phy-gmii-sel { 318724ba675SRob Herring compatible = "ti,am3352-phy-gmii-sel"; 319724ba675SRob Herring reg = <0x650 0x4>; 320724ba675SRob Herring #phy-cells = <2>; 321724ba675SRob Herring }; 322724ba675SRob Herring 323724ba675SRob Herring scm_clocks: clocks { 324724ba675SRob Herring #address-cells = <1>; 325724ba675SRob Herring #size-cells = <0>; 326724ba675SRob Herring }; 327724ba675SRob Herring }; 328724ba675SRob Herring 329724ba675SRob Herring usb_ctrl_mod: control@620 { 330724ba675SRob Herring compatible = "ti,am335x-usb-ctrl-module"; 331724ba675SRob Herring reg = <0x620 0x10>, 332724ba675SRob Herring <0x648 0x4>; 333724ba675SRob Herring reg-names = "phy_ctrl", "wakeup"; 334724ba675SRob Herring }; 335724ba675SRob Herring 336724ba675SRob Herring wkup_m3_ipc: wkup_m3_ipc@1324 { 337724ba675SRob Herring compatible = "ti,am3352-wkup-m3-ipc"; 338724ba675SRob Herring reg = <0x1324 0x24>; 339724ba675SRob Herring interrupts = <78>; 340724ba675SRob Herring ti,rproc = <&wkup_m3>; 341724ba675SRob Herring mboxes = <&mailbox &mbox_wkupm3>; 342724ba675SRob Herring }; 343724ba675SRob Herring 344724ba675SRob Herring edma_xbar: dma-router@f90 { 345724ba675SRob Herring compatible = "ti,am335x-edma-crossbar"; 346724ba675SRob Herring reg = <0xf90 0x40>; 347724ba675SRob Herring #dma-cells = <3>; 348724ba675SRob Herring dma-requests = <32>; 349724ba675SRob Herring dma-masters = <&edma>; 350724ba675SRob Herring }; 351724ba675SRob Herring 352724ba675SRob Herring scm_clockdomains: clockdomains { 353724ba675SRob Herring }; 354724ba675SRob Herring }; 355724ba675SRob Herring }; 356724ba675SRob Herring 357724ba675SRob Herring timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */ 358724ba675SRob Herring compatible = "ti,sysc-omap2-timer", "ti,sysc"; 359724ba675SRob Herring reg = <0x31000 0x4>, 360724ba675SRob Herring <0x31010 0x4>, 361724ba675SRob Herring <0x31014 0x4>; 362724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 363724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 364724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 365724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 366724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 367724ba675SRob Herring <SYSC_IDLE_NO>, 368724ba675SRob Herring <SYSC_IDLE_SMART>; 369724ba675SRob Herring ti,syss-mask = <1>; 370724ba675SRob Herring /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 371724ba675SRob Herring clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>; 372724ba675SRob Herring clock-names = "fck"; 373724ba675SRob Herring #address-cells = <1>; 374724ba675SRob Herring #size-cells = <1>; 375724ba675SRob Herring ranges = <0x0 0x31000 0x1000>; 376724ba675SRob Herring 377724ba675SRob Herring timer1: timer@0 { 378724ba675SRob Herring compatible = "ti,am335x-timer-1ms"; 379724ba675SRob Herring reg = <0x0 0x400>; 380724ba675SRob Herring interrupts = <67>; 381724ba675SRob Herring ti,timer-alwon; 382724ba675SRob Herring clocks = <&timer1_fck>; 383724ba675SRob Herring clock-names = "fck"; 384724ba675SRob Herring }; 385724ba675SRob Herring }; 386724ba675SRob Herring 387724ba675SRob Herring target-module@33000 { /* 0x44e33000, ap 27 18.0 */ 388724ba675SRob Herring compatible = "ti,sysc"; 389724ba675SRob Herring status = "disabled"; 390724ba675SRob Herring #address-cells = <1>; 391724ba675SRob Herring #size-cells = <1>; 392724ba675SRob Herring ranges = <0x0 0x33000 0x1000>; 393724ba675SRob Herring }; 394724ba675SRob Herring 395724ba675SRob Herring target-module@35000 { /* 0x44e35000, ap 29 50.0 */ 396724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 397724ba675SRob Herring reg = <0x35000 0x4>, 398724ba675SRob Herring <0x35010 0x4>, 399724ba675SRob Herring <0x35014 0x4>; 400724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 401724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 402724ba675SRob Herring SYSC_OMAP2_SOFTRESET)>; 403724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 404724ba675SRob Herring <SYSC_IDLE_NO>, 405724ba675SRob Herring <SYSC_IDLE_SMART>, 406724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 407724ba675SRob Herring ti,syss-mask = <1>; 408724ba675SRob Herring /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 409724ba675SRob Herring clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>; 410724ba675SRob Herring clock-names = "fck"; 411724ba675SRob Herring #address-cells = <1>; 412724ba675SRob Herring #size-cells = <1>; 413724ba675SRob Herring ranges = <0x0 0x35000 0x1000>; 414724ba675SRob Herring 415724ba675SRob Herring wdt2: wdt@0 { 416724ba675SRob Herring compatible = "ti,omap3-wdt"; 417724ba675SRob Herring reg = <0x0 0x1000>; 418724ba675SRob Herring interrupts = <91>; 419724ba675SRob Herring }; 420724ba675SRob Herring }; 421724ba675SRob Herring 422724ba675SRob Herring target-module@37000 { /* 0x44e37000, ap 31 08.0 */ 423724ba675SRob Herring compatible = "ti,sysc"; 424724ba675SRob Herring status = "disabled"; 425724ba675SRob Herring #address-cells = <1>; 426724ba675SRob Herring #size-cells = <1>; 427724ba675SRob Herring ranges = <0x0 0x37000 0x1000>; 428724ba675SRob Herring }; 429724ba675SRob Herring 430724ba675SRob Herring target-module@39000 { /* 0x44e39000, ap 33 02.0 */ 431724ba675SRob Herring compatible = "ti,sysc"; 432724ba675SRob Herring status = "disabled"; 433724ba675SRob Herring #address-cells = <1>; 434724ba675SRob Herring #size-cells = <1>; 435724ba675SRob Herring ranges = <0x0 0x39000 0x1000>; 436724ba675SRob Herring }; 437724ba675SRob Herring 438724ba675SRob Herring target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */ 439724ba675SRob Herring compatible = "ti,sysc-omap4-simple", "ti,sysc"; 440724ba675SRob Herring reg = <0x3e074 0x4>, 441724ba675SRob Herring <0x3e078 0x4>; 442724ba675SRob Herring reg-names = "rev", "sysc"; 443724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 444724ba675SRob Herring <SYSC_IDLE_NO>, 445724ba675SRob Herring <SYSC_IDLE_SMART>, 446724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 447724ba675SRob Herring /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ 448724ba675SRob Herring power-domains = <&prm_rtc>; 449724ba675SRob Herring clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>; 450724ba675SRob Herring clock-names = "fck"; 451724ba675SRob Herring #address-cells = <1>; 452724ba675SRob Herring #size-cells = <1>; 453724ba675SRob Herring ranges = <0x0 0x3e000 0x1000>; 454724ba675SRob Herring 455724ba675SRob Herring rtc: rtc@0 { 456724ba675SRob Herring compatible = "ti,am3352-rtc", "ti,da830-rtc"; 457724ba675SRob Herring reg = <0x0 0x1000>; 458*f274a854SKrzysztof Kozlowski interrupts = <75>, 459*f274a854SKrzysztof Kozlowski <76>; 460724ba675SRob Herring }; 461724ba675SRob Herring }; 462724ba675SRob Herring 463724ba675SRob Herring target-module@40000 { /* 0x44e40000, ap 38 68.0 */ 464724ba675SRob Herring compatible = "ti,sysc"; 465724ba675SRob Herring status = "disabled"; 466724ba675SRob Herring #address-cells = <1>; 467724ba675SRob Herring #size-cells = <1>; 468724ba675SRob Herring ranges = <0x0 0x40000 0x40000>; 469724ba675SRob Herring }; 470724ba675SRob Herring }; 471724ba675SRob Herring}; 472724ba675SRob Herring 473724ba675SRob Herring&l4_fw { /* 0x47c00000 */ 474724ba675SRob Herring compatible = "ti,am33xx-l4-fw", "simple-bus"; 475724ba675SRob Herring reg = <0x47c00000 0x800>, 476724ba675SRob Herring <0x47c00800 0x800>, 477724ba675SRob Herring <0x47c01000 0x400>; 478724ba675SRob Herring reg-names = "ap", "la", "ia0"; 479724ba675SRob Herring #address-cells = <1>; 480724ba675SRob Herring #size-cells = <1>; 481724ba675SRob Herring ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */ 482724ba675SRob Herring 483724ba675SRob Herring segment@0 { /* 0x47c00000 */ 484724ba675SRob Herring compatible = "simple-bus"; 485724ba675SRob Herring #address-cells = <1>; 486724ba675SRob Herring #size-cells = <1>; 487724ba675SRob Herring ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 488724ba675SRob Herring <0x00000800 0x00000800 0x000800>, /* ap 1 */ 489724ba675SRob Herring <0x00001000 0x00001000 0x000400>, /* ap 2 */ 490724ba675SRob Herring <0x0000c000 0x0000c000 0x001000>, /* ap 3 */ 491724ba675SRob Herring <0x0000d000 0x0000d000 0x001000>, /* ap 4 */ 492724ba675SRob Herring <0x0000e000 0x0000e000 0x001000>, /* ap 5 */ 493724ba675SRob Herring <0x0000f000 0x0000f000 0x001000>, /* ap 6 */ 494724ba675SRob Herring <0x00010000 0x00010000 0x001000>, /* ap 7 */ 495724ba675SRob Herring <0x00011000 0x00011000 0x001000>, /* ap 8 */ 496724ba675SRob Herring <0x0001a000 0x0001a000 0x001000>, /* ap 9 */ 497724ba675SRob Herring <0x0001b000 0x0001b000 0x001000>, /* ap 10 */ 498724ba675SRob Herring <0x00024000 0x00024000 0x001000>, /* ap 11 */ 499724ba675SRob Herring <0x00025000 0x00025000 0x001000>, /* ap 12 */ 500724ba675SRob Herring <0x00026000 0x00026000 0x001000>, /* ap 13 */ 501724ba675SRob Herring <0x00027000 0x00027000 0x001000>, /* ap 14 */ 502724ba675SRob Herring <0x00030000 0x00030000 0x001000>, /* ap 15 */ 503724ba675SRob Herring <0x00031000 0x00031000 0x001000>, /* ap 16 */ 504724ba675SRob Herring <0x00038000 0x00038000 0x001000>, /* ap 17 */ 505724ba675SRob Herring <0x00039000 0x00039000 0x001000>, /* ap 18 */ 506724ba675SRob Herring <0x0003a000 0x0003a000 0x001000>, /* ap 19 */ 507724ba675SRob Herring <0x0003b000 0x0003b000 0x001000>, /* ap 20 */ 508724ba675SRob Herring <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ 509724ba675SRob Herring <0x0003f000 0x0003f000 0x001000>, /* ap 22 */ 510724ba675SRob Herring <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ 511724ba675SRob Herring <0x00040000 0x00040000 0x001000>, /* ap 24 */ 512724ba675SRob Herring <0x00046000 0x00046000 0x001000>, /* ap 25 */ 513724ba675SRob Herring <0x00047000 0x00047000 0x001000>, /* ap 26 */ 514724ba675SRob Herring <0x00044000 0x00044000 0x001000>, /* ap 27 */ 515724ba675SRob Herring <0x00045000 0x00045000 0x001000>, /* ap 28 */ 516724ba675SRob Herring <0x00028000 0x00028000 0x001000>, /* ap 29 */ 517724ba675SRob Herring <0x00029000 0x00029000 0x001000>, /* ap 30 */ 518724ba675SRob Herring <0x00032000 0x00032000 0x001000>, /* ap 31 */ 519724ba675SRob Herring <0x00033000 0x00033000 0x001000>, /* ap 32 */ 520724ba675SRob Herring <0x0003d000 0x0003d000 0x001000>, /* ap 33 */ 521724ba675SRob Herring <0x00041000 0x00041000 0x001000>, /* ap 34 */ 522724ba675SRob Herring <0x00042000 0x00042000 0x001000>, /* ap 35 */ 523724ba675SRob Herring <0x00043000 0x00043000 0x001000>, /* ap 36 */ 524724ba675SRob Herring <0x00014000 0x00014000 0x001000>, /* ap 37 */ 525724ba675SRob Herring <0x00015000 0x00015000 0x001000>; /* ap 38 */ 526724ba675SRob Herring 527724ba675SRob Herring target-module@c000 { /* 0x47c0c000, ap 3 04.0 */ 528724ba675SRob Herring compatible = "ti,sysc"; 529724ba675SRob Herring status = "disabled"; 530724ba675SRob Herring #address-cells = <1>; 531724ba675SRob Herring #size-cells = <1>; 532724ba675SRob Herring ranges = <0x0 0xc000 0x1000>; 533724ba675SRob Herring }; 534724ba675SRob Herring 535724ba675SRob Herring target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */ 536724ba675SRob Herring compatible = "ti,sysc"; 537724ba675SRob Herring status = "disabled"; 538724ba675SRob Herring #address-cells = <1>; 539724ba675SRob Herring #size-cells = <1>; 540724ba675SRob Herring ranges = <0x0 0xe000 0x1000>; 541724ba675SRob Herring }; 542724ba675SRob Herring 543724ba675SRob Herring target-module@10000 { /* 0x47c10000, ap 7 20.0 */ 544724ba675SRob Herring compatible = "ti,sysc"; 545724ba675SRob Herring status = "disabled"; 546724ba675SRob Herring #address-cells = <1>; 547724ba675SRob Herring #size-cells = <1>; 548724ba675SRob Herring ranges = <0x0 0x10000 0x1000>; 549724ba675SRob Herring }; 550724ba675SRob Herring 551724ba675SRob Herring target-module@14000 { /* 0x47c14000, ap 37 3c.0 */ 552724ba675SRob Herring compatible = "ti,sysc"; 553724ba675SRob Herring status = "disabled"; 554724ba675SRob Herring #address-cells = <1>; 555724ba675SRob Herring #size-cells = <1>; 556724ba675SRob Herring ranges = <0x0 0x14000 0x1000>; 557724ba675SRob Herring }; 558724ba675SRob Herring 559724ba675SRob Herring target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */ 560724ba675SRob Herring compatible = "ti,sysc"; 561724ba675SRob Herring status = "disabled"; 562724ba675SRob Herring #address-cells = <1>; 563724ba675SRob Herring #size-cells = <1>; 564724ba675SRob Herring ranges = <0x0 0x1a000 0x1000>; 565724ba675SRob Herring }; 566724ba675SRob Herring 567724ba675SRob Herring target-module@24000 { /* 0x47c24000, ap 11 28.0 */ 568724ba675SRob Herring compatible = "ti,sysc"; 569724ba675SRob Herring status = "disabled"; 570724ba675SRob Herring #address-cells = <1>; 571724ba675SRob Herring #size-cells = <1>; 572724ba675SRob Herring ranges = <0x0 0x24000 0x1000>; 573724ba675SRob Herring }; 574724ba675SRob Herring 575724ba675SRob Herring target-module@26000 { /* 0x47c26000, ap 13 30.0 */ 576724ba675SRob Herring compatible = "ti,sysc"; 577724ba675SRob Herring status = "disabled"; 578724ba675SRob Herring #address-cells = <1>; 579724ba675SRob Herring #size-cells = <1>; 580724ba675SRob Herring ranges = <0x0 0x26000 0x1000>; 581724ba675SRob Herring }; 582724ba675SRob Herring 583724ba675SRob Herring target-module@28000 { /* 0x47c28000, ap 29 40.0 */ 584724ba675SRob Herring compatible = "ti,sysc"; 585724ba675SRob Herring status = "disabled"; 586724ba675SRob Herring #address-cells = <1>; 587724ba675SRob Herring #size-cells = <1>; 588724ba675SRob Herring ranges = <0x0 0x28000 0x1000>; 589724ba675SRob Herring }; 590724ba675SRob Herring 591724ba675SRob Herring target-module@30000 { /* 0x47c30000, ap 15 14.0 */ 592724ba675SRob Herring compatible = "ti,sysc"; 593724ba675SRob Herring status = "disabled"; 594724ba675SRob Herring #address-cells = <1>; 595724ba675SRob Herring #size-cells = <1>; 596724ba675SRob Herring ranges = <0x0 0x30000 0x1000>; 597724ba675SRob Herring }; 598724ba675SRob Herring 599724ba675SRob Herring target-module@32000 { /* 0x47c32000, ap 31 06.0 */ 600724ba675SRob Herring compatible = "ti,sysc"; 601724ba675SRob Herring status = "disabled"; 602724ba675SRob Herring #address-cells = <1>; 603724ba675SRob Herring #size-cells = <1>; 604724ba675SRob Herring ranges = <0x0 0x32000 0x1000>; 605724ba675SRob Herring }; 606724ba675SRob Herring 607724ba675SRob Herring target-module@38000 { /* 0x47c38000, ap 17 18.0 */ 608724ba675SRob Herring compatible = "ti,sysc"; 609724ba675SRob Herring status = "disabled"; 610724ba675SRob Herring #address-cells = <1>; 611724ba675SRob Herring #size-cells = <1>; 612724ba675SRob Herring ranges = <0x0 0x38000 0x1000>; 613724ba675SRob Herring }; 614724ba675SRob Herring 615724ba675SRob Herring target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */ 616724ba675SRob Herring compatible = "ti,sysc"; 617724ba675SRob Herring status = "disabled"; 618724ba675SRob Herring #address-cells = <1>; 619724ba675SRob Herring #size-cells = <1>; 620724ba675SRob Herring ranges = <0x0 0x3a000 0x1000>; 621724ba675SRob Herring }; 622724ba675SRob Herring 623724ba675SRob Herring target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */ 624724ba675SRob Herring compatible = "ti,sysc"; 625724ba675SRob Herring status = "disabled"; 626724ba675SRob Herring #address-cells = <1>; 627724ba675SRob Herring #size-cells = <1>; 628724ba675SRob Herring ranges = <0x0 0x3c000 0x1000>; 629724ba675SRob Herring }; 630724ba675SRob Herring 631724ba675SRob Herring target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */ 632724ba675SRob Herring compatible = "ti,sysc"; 633724ba675SRob Herring status = "disabled"; 634724ba675SRob Herring #address-cells = <1>; 635724ba675SRob Herring #size-cells = <1>; 636724ba675SRob Herring ranges = <0x0 0x3e000 0x1000>; 637724ba675SRob Herring }; 638724ba675SRob Herring 639724ba675SRob Herring target-module@40000 { /* 0x47c40000, ap 24 02.0 */ 640724ba675SRob Herring compatible = "ti,sysc"; 641724ba675SRob Herring status = "disabled"; 642724ba675SRob Herring #address-cells = <1>; 643724ba675SRob Herring #size-cells = <1>; 644724ba675SRob Herring ranges = <0x0 0x40000 0x1000>; 645724ba675SRob Herring }; 646724ba675SRob Herring 647724ba675SRob Herring target-module@42000 { /* 0x47c42000, ap 35 34.0 */ 648724ba675SRob Herring compatible = "ti,sysc"; 649724ba675SRob Herring status = "disabled"; 650724ba675SRob Herring #address-cells = <1>; 651724ba675SRob Herring #size-cells = <1>; 652724ba675SRob Herring ranges = <0x0 0x42000 0x1000>; 653724ba675SRob Herring }; 654724ba675SRob Herring 655724ba675SRob Herring target-module@44000 { /* 0x47c44000, ap 27 24.0 */ 656724ba675SRob Herring compatible = "ti,sysc"; 657724ba675SRob Herring status = "disabled"; 658724ba675SRob Herring #address-cells = <1>; 659724ba675SRob Herring #size-cells = <1>; 660724ba675SRob Herring ranges = <0x0 0x44000 0x1000>; 661724ba675SRob Herring }; 662724ba675SRob Herring 663724ba675SRob Herring target-module@46000 { /* 0x47c46000, ap 25 2c.0 */ 664724ba675SRob Herring compatible = "ti,sysc"; 665724ba675SRob Herring status = "disabled"; 666724ba675SRob Herring #address-cells = <1>; 667724ba675SRob Herring #size-cells = <1>; 668724ba675SRob Herring ranges = <0x0 0x46000 0x1000>; 669724ba675SRob Herring }; 670724ba675SRob Herring }; 671724ba675SRob Herring}; 672724ba675SRob Herring 673724ba675SRob Herring&l4_fast { /* 0x4a000000 */ 674724ba675SRob Herring compatible = "ti,am33xx-l4-fast", "simple-pm-bus"; 675724ba675SRob Herring power-domains = <&prm_per>; 676724ba675SRob Herring clocks = <&l4hs_clkctrl AM3_L4HS_L4_HS_CLKCTRL 0>; 677724ba675SRob Herring clock-names = "fck"; 678724ba675SRob Herring reg = <0x4a000000 0x800>, 679724ba675SRob Herring <0x4a000800 0x800>, 680724ba675SRob Herring <0x4a001000 0x400>; 681724ba675SRob Herring reg-names = "ap", "la", "ia0"; 682724ba675SRob Herring #address-cells = <1>; 683724ba675SRob Herring #size-cells = <1>; 684724ba675SRob Herring ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ 685724ba675SRob Herring 686724ba675SRob Herring segment@0 { /* 0x4a000000 */ 687724ba675SRob Herring compatible = "simple-pm-bus"; 688724ba675SRob Herring #address-cells = <1>; 689724ba675SRob Herring #size-cells = <1>; 690724ba675SRob Herring ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 691724ba675SRob Herring <0x00000800 0x00000800 0x000800>, /* ap 1 */ 692724ba675SRob Herring <0x00001000 0x00001000 0x000400>, /* ap 2 */ 693724ba675SRob Herring <0x00100000 0x00100000 0x008000>, /* ap 3 */ 694724ba675SRob Herring <0x00108000 0x00108000 0x001000>, /* ap 4 */ 695724ba675SRob Herring <0x00180000 0x00180000 0x020000>, /* ap 5 */ 696724ba675SRob Herring <0x001a0000 0x001a0000 0x001000>, /* ap 6 */ 697724ba675SRob Herring <0x00200000 0x00200000 0x080000>, /* ap 7 */ 698724ba675SRob Herring <0x00280000 0x00280000 0x001000>, /* ap 8 */ 699724ba675SRob Herring <0x00300000 0x00300000 0x080000>, /* ap 9 */ 700724ba675SRob Herring <0x00380000 0x00380000 0x001000>; /* ap 10 */ 701724ba675SRob Herring 702724ba675SRob Herring target-module@100000 { /* 0x4a100000, ap 3 08.0 */ 703724ba675SRob Herring compatible = "ti,sysc-omap4-simple", "ti,sysc"; 704724ba675SRob Herring reg = <0x101200 0x4>, 705724ba675SRob Herring <0x101208 0x4>, 706724ba675SRob Herring <0x101204 0x4>; 707724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 708724ba675SRob Herring ti,sysc-mask = <0>; 709724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 710724ba675SRob Herring <SYSC_IDLE_NO>; 711724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 712724ba675SRob Herring <SYSC_IDLE_NO>; 713724ba675SRob Herring ti,syss-mask = <1>; 714724ba675SRob Herring clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; 715724ba675SRob Herring clock-names = "fck"; 716724ba675SRob Herring #address-cells = <1>; 717724ba675SRob Herring #size-cells = <1>; 718724ba675SRob Herring ranges = <0x0 0x100000 0x8000>; 719724ba675SRob Herring 720724ba675SRob Herring mac: ethernet@0 { 721724ba675SRob Herring compatible = "ti,am335x-cpsw","ti,cpsw"; 722724ba675SRob Herring clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; 723724ba675SRob Herring clock-names = "fck", "cpts"; 724724ba675SRob Herring cpdma_channels = <8>; 725724ba675SRob Herring ale_entries = <1024>; 726724ba675SRob Herring bd_ram_size = <0x2000>; 727724ba675SRob Herring mac_control = <0x20>; 728724ba675SRob Herring slaves = <2>; 729724ba675SRob Herring active_slave = <0>; 730724ba675SRob Herring cpts_clock_mult = <0x80000000>; 731724ba675SRob Herring cpts_clock_shift = <29>; 732724ba675SRob Herring reg = <0x0 0x800 733724ba675SRob Herring 0x1200 0x100>; 734724ba675SRob Herring #address-cells = <1>; 735724ba675SRob Herring #size-cells = <1>; 736724ba675SRob Herring /* 737724ba675SRob Herring * c0_rx_thresh_pend 738724ba675SRob Herring * c0_rx_pend 739724ba675SRob Herring * c0_tx_pend 740724ba675SRob Herring * c0_misc_pend 741724ba675SRob Herring */ 742*f274a854SKrzysztof Kozlowski interrupts = <40>, <41>, <42>, <43>; 743724ba675SRob Herring ranges = <0 0 0x8000>; 744724ba675SRob Herring syscon = <&scm_conf>; 745724ba675SRob Herring status = "disabled"; 746724ba675SRob Herring 747724ba675SRob Herring davinci_mdio: mdio@1000 { 748724ba675SRob Herring compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 749724ba675SRob Herring clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; 750724ba675SRob Herring clock-names = "fck"; 751724ba675SRob Herring #address-cells = <1>; 752724ba675SRob Herring #size-cells = <0>; 753724ba675SRob Herring bus_freq = <1000000>; 754724ba675SRob Herring reg = <0x1000 0x100>; 755724ba675SRob Herring status = "disabled"; 756724ba675SRob Herring }; 757724ba675SRob Herring 758724ba675SRob Herring cpsw_emac0: slave@200 { 759724ba675SRob Herring /* Filled in by U-Boot */ 760724ba675SRob Herring mac-address = [ 00 00 00 00 00 00 ]; 761724ba675SRob Herring phys = <&phy_gmii_sel 1 1>; 762724ba675SRob Herring }; 763724ba675SRob Herring 764724ba675SRob Herring cpsw_emac1: slave@300 { 765724ba675SRob Herring /* Filled in by U-Boot */ 766724ba675SRob Herring mac-address = [ 00 00 00 00 00 00 ]; 767724ba675SRob Herring phys = <&phy_gmii_sel 2 1>; 768724ba675SRob Herring }; 769724ba675SRob Herring }; 770724ba675SRob Herring 771724ba675SRob Herring mac_sw: switch@0 { 772724ba675SRob Herring compatible = "ti,am335x-cpsw-switch", "ti,cpsw-switch"; 773724ba675SRob Herring reg = <0x0 0x4000>; 774724ba675SRob Herring ranges = <0 0 0x4000>; 775724ba675SRob Herring clocks = <&cpsw_125mhz_gclk>; 776724ba675SRob Herring clock-names = "fck"; 777724ba675SRob Herring #address-cells = <1>; 778724ba675SRob Herring #size-cells = <1>; 779724ba675SRob Herring syscon = <&scm_conf>; 780724ba675SRob Herring status = "disabled"; 781724ba675SRob Herring 782*f274a854SKrzysztof Kozlowski interrupts = <40>, <41>, <42>, <43>; 783724ba675SRob Herring interrupt-names = "rx_thresh", "rx", "tx", "misc"; 784724ba675SRob Herring 785724ba675SRob Herring ethernet-ports { 786724ba675SRob Herring #address-cells = <1>; 787724ba675SRob Herring #size-cells = <0>; 788724ba675SRob Herring 789724ba675SRob Herring cpsw_port1: port@1 { 790724ba675SRob Herring reg = <1>; 791724ba675SRob Herring label = "port1"; 792724ba675SRob Herring mac-address = [ 00 00 00 00 00 00 ]; 793724ba675SRob Herring phys = <&phy_gmii_sel 1 1>; 794724ba675SRob Herring }; 795724ba675SRob Herring 796724ba675SRob Herring cpsw_port2: port@2 { 797724ba675SRob Herring reg = <2>; 798724ba675SRob Herring label = "port2"; 799724ba675SRob Herring mac-address = [ 00 00 00 00 00 00 ]; 800724ba675SRob Herring phys = <&phy_gmii_sel 2 1>; 801724ba675SRob Herring }; 802724ba675SRob Herring }; 803724ba675SRob Herring 804724ba675SRob Herring davinci_mdio_sw: mdio@1000 { 805724ba675SRob Herring compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 806724ba675SRob Herring clocks = <&cpsw_125mhz_gclk>; 807724ba675SRob Herring clock-names = "fck"; 808724ba675SRob Herring #address-cells = <1>; 809724ba675SRob Herring #size-cells = <0>; 810724ba675SRob Herring bus_freq = <1000000>; 811724ba675SRob Herring reg = <0x1000 0x100>; 812724ba675SRob Herring }; 813724ba675SRob Herring 814724ba675SRob Herring cpts { 815724ba675SRob Herring clocks = <&cpsw_cpts_rft_clk>; 816724ba675SRob Herring clock-names = "cpts"; 817724ba675SRob Herring }; 818724ba675SRob Herring }; 819724ba675SRob Herring }; 820724ba675SRob Herring 821724ba675SRob Herring target-module@180000 { /* 0x4a180000, ap 5 10.0 */ 822724ba675SRob Herring compatible = "ti,sysc"; 823724ba675SRob Herring status = "disabled"; 824724ba675SRob Herring #address-cells = <1>; 825724ba675SRob Herring #size-cells = <1>; 826724ba675SRob Herring ranges = <0x0 0x180000 0x20000>; 827724ba675SRob Herring }; 828724ba675SRob Herring 829724ba675SRob Herring target-module@200000 { /* 0x4a200000, ap 7 02.0 */ 830724ba675SRob Herring compatible = "ti,sysc"; 831724ba675SRob Herring status = "disabled"; 832724ba675SRob Herring #address-cells = <1>; 833724ba675SRob Herring #size-cells = <1>; 834724ba675SRob Herring ranges = <0x0 0x200000 0x80000>; 835724ba675SRob Herring }; 836724ba675SRob Herring 837724ba675SRob Herring pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ 838724ba675SRob Herring compatible = "ti,sysc-pruss", "ti,sysc"; 839724ba675SRob Herring reg = <0x326000 0x4>, 840724ba675SRob Herring <0x326004 0x4>; 841724ba675SRob Herring reg-names = "rev", "sysc"; 842724ba675SRob Herring ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | 843724ba675SRob Herring SYSC_PRUSS_SUB_MWAIT)>; 844724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 845724ba675SRob Herring <SYSC_IDLE_NO>, 846724ba675SRob Herring <SYSC_IDLE_SMART>; 847724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 848724ba675SRob Herring <SYSC_IDLE_NO>, 849724ba675SRob Herring <SYSC_IDLE_SMART>; 850724ba675SRob Herring clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>; 851724ba675SRob Herring clock-names = "fck"; 852724ba675SRob Herring resets = <&prm_per 1>; 853724ba675SRob Herring reset-names = "rstctrl"; 854724ba675SRob Herring #address-cells = <1>; 855724ba675SRob Herring #size-cells = <1>; 856724ba675SRob Herring ranges = <0x0 0x300000 0x80000>; 857724ba675SRob Herring status = "disabled"; 858724ba675SRob Herring 859724ba675SRob Herring pruss: pruss@0 { 860724ba675SRob Herring compatible = "ti,am3356-pruss"; 861724ba675SRob Herring reg = <0x0 0x80000>; 862724ba675SRob Herring #address-cells = <1>; 863724ba675SRob Herring #size-cells = <1>; 864724ba675SRob Herring ranges; 865724ba675SRob Herring 866724ba675SRob Herring pruss_mem: memories@0 { 867724ba675SRob Herring reg = <0x0 0x2000>, 868724ba675SRob Herring <0x2000 0x2000>, 869724ba675SRob Herring <0x10000 0x3000>; 870724ba675SRob Herring reg-names = "dram0", "dram1", 871724ba675SRob Herring "shrdram2"; 872724ba675SRob Herring }; 873724ba675SRob Herring 874724ba675SRob Herring pruss_cfg: cfg@26000 { 875724ba675SRob Herring compatible = "ti,pruss-cfg", "syscon"; 876724ba675SRob Herring reg = <0x26000 0x2000>; 877724ba675SRob Herring #address-cells = <1>; 878724ba675SRob Herring #size-cells = <1>; 879724ba675SRob Herring ranges = <0x0 0x26000 0x2000>; 880724ba675SRob Herring 881724ba675SRob Herring clocks { 882724ba675SRob Herring #address-cells = <1>; 883724ba675SRob Herring #size-cells = <0>; 884724ba675SRob Herring 885724ba675SRob Herring pruss_iepclk_mux: iepclk-mux@30 { 886724ba675SRob Herring reg = <0x30>; 887724ba675SRob Herring #clock-cells = <0>; 888724ba675SRob Herring clocks = <&l3_gclk>, /* icss_iep_gclk */ 889724ba675SRob Herring <&pruss_ocp_gclk>; /* icss_ocp_gclk */ 890724ba675SRob Herring }; 891724ba675SRob Herring }; 892724ba675SRob Herring }; 893724ba675SRob Herring 894724ba675SRob Herring pruss_mii_rt: mii-rt@32000 { 895724ba675SRob Herring compatible = "ti,pruss-mii", "syscon"; 896724ba675SRob Herring reg = <0x32000 0x58>; 897724ba675SRob Herring }; 898724ba675SRob Herring 899724ba675SRob Herring pruss_intc: interrupt-controller@20000 { 900724ba675SRob Herring compatible = "ti,pruss-intc"; 901724ba675SRob Herring reg = <0x20000 0x2000>; 902*f274a854SKrzysztof Kozlowski interrupts = <20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>; 903724ba675SRob Herring interrupt-names = "host_intr0", "host_intr1", 904724ba675SRob Herring "host_intr2", "host_intr3", 905724ba675SRob Herring "host_intr4", "host_intr5", 906724ba675SRob Herring "host_intr6", "host_intr7"; 907724ba675SRob Herring interrupt-controller; 908724ba675SRob Herring #interrupt-cells = <3>; 909724ba675SRob Herring }; 910724ba675SRob Herring 911724ba675SRob Herring pru0: pru@34000 { 912724ba675SRob Herring compatible = "ti,am3356-pru"; 913724ba675SRob Herring reg = <0x34000 0x2000>, 914724ba675SRob Herring <0x22000 0x400>, 915724ba675SRob Herring <0x22400 0x100>; 916724ba675SRob Herring reg-names = "iram", "control", "debug"; 917724ba675SRob Herring firmware-name = "am335x-pru0-fw"; 918724ba675SRob Herring }; 919724ba675SRob Herring 920724ba675SRob Herring pru1: pru@38000 { 921724ba675SRob Herring compatible = "ti,am3356-pru"; 922724ba675SRob Herring reg = <0x38000 0x2000>, 923724ba675SRob Herring <0x24000 0x400>, 924724ba675SRob Herring <0x24400 0x100>; 925724ba675SRob Herring reg-names = "iram", "control", "debug"; 926724ba675SRob Herring firmware-name = "am335x-pru1-fw"; 927724ba675SRob Herring }; 928724ba675SRob Herring 929724ba675SRob Herring pruss_mdio: mdio@32400 { 930724ba675SRob Herring compatible = "ti,davinci_mdio"; 931724ba675SRob Herring reg = <0x32400 0x90>; 932724ba675SRob Herring clocks = <&dpll_core_m4_ck>; 933724ba675SRob Herring clock-names = "fck"; 934724ba675SRob Herring bus_freq = <1000000>; 935724ba675SRob Herring #address-cells = <1>; 936724ba675SRob Herring #size-cells = <0>; 937724ba675SRob Herring status = "disabled"; 938724ba675SRob Herring }; 939724ba675SRob Herring }; 940724ba675SRob Herring }; 941724ba675SRob Herring }; 942724ba675SRob Herring}; 943724ba675SRob Herring 944724ba675SRob Herring&l4_mpuss { /* 0x4b140000 */ 945724ba675SRob Herring compatible = "ti,am33xx-l4-mpuss", "simple-bus"; 946724ba675SRob Herring reg = <0x4b144400 0x100>, 947724ba675SRob Herring <0x4b144800 0x400>; 948724ba675SRob Herring reg-names = "la", "ap"; 949724ba675SRob Herring #address-cells = <1>; 950724ba675SRob Herring #size-cells = <1>; 951724ba675SRob Herring ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */ 952724ba675SRob Herring 953724ba675SRob Herring segment@0 { /* 0x4b140000 */ 954724ba675SRob Herring compatible = "simple-bus"; 955724ba675SRob Herring #address-cells = <1>; 956724ba675SRob Herring #size-cells = <1>; 957724ba675SRob Herring ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */ 958724ba675SRob Herring <0x00001000 0x00001000 0x001000>, /* ap 1 */ 959724ba675SRob Herring <0x00002000 0x00002000 0x001000>, /* ap 2 */ 960724ba675SRob Herring <0x00004000 0x00004000 0x000400>, /* ap 3 */ 961724ba675SRob Herring <0x00005000 0x00005000 0x000400>, /* ap 4 */ 962724ba675SRob Herring <0x00000000 0x00000000 0x001000>, /* ap 5 */ 963724ba675SRob Herring <0x00003000 0x00003000 0x001000>, /* ap 6 */ 964724ba675SRob Herring <0x00000800 0x00000800 0x000800>; /* ap 7 */ 965724ba675SRob Herring 966724ba675SRob Herring target-module@0 { /* 0x4b140000, ap 5 02.2 */ 967724ba675SRob Herring compatible = "ti,sysc"; 968724ba675SRob Herring status = "disabled"; 969724ba675SRob Herring #address-cells = <1>; 970724ba675SRob Herring #size-cells = <1>; 971724ba675SRob Herring ranges = <0x00000000 0x00000000 0x00001000>, 972724ba675SRob Herring <0x00001000 0x00001000 0x00001000>, 973724ba675SRob Herring <0x00002000 0x00002000 0x00001000>; 974724ba675SRob Herring }; 975724ba675SRob Herring 976724ba675SRob Herring target-module@3000 { /* 0x4b143000, ap 6 04.0 */ 977724ba675SRob Herring compatible = "ti,sysc"; 978724ba675SRob Herring status = "disabled"; 979724ba675SRob Herring #address-cells = <1>; 980724ba675SRob Herring #size-cells = <1>; 981724ba675SRob Herring ranges = <0x0 0x3000 0x1000>; 982724ba675SRob Herring }; 983724ba675SRob Herring }; 984724ba675SRob Herring}; 985724ba675SRob Herring 986724ba675SRob Herring&l4_per { /* 0x48000000 */ 987724ba675SRob Herring compatible = "ti,am33xx-l4-per", "simple-pm-bus"; 988724ba675SRob Herring power-domains = <&prm_per>; 989724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>; 990724ba675SRob Herring clock-names = "fck"; 991724ba675SRob Herring reg = <0x48000000 0x800>, 992724ba675SRob Herring <0x48000800 0x800>, 993724ba675SRob Herring <0x48001000 0x400>, 994724ba675SRob Herring <0x48001400 0x400>, 995724ba675SRob Herring <0x48001800 0x400>, 996724ba675SRob Herring <0x48001c00 0x400>; 997724ba675SRob Herring reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; 998724ba675SRob Herring #address-cells = <1>; 999724ba675SRob Herring #size-cells = <1>; 1000724ba675SRob Herring ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ 1001724ba675SRob Herring <0x00100000 0x48100000 0x100000>, /* segment 1 */ 1002724ba675SRob Herring <0x00200000 0x48200000 0x100000>, /* segment 2 */ 1003724ba675SRob Herring <0x00300000 0x48300000 0x100000>, /* segment 3 */ 1004724ba675SRob Herring <0x46000000 0x46000000 0x400000>, /* l3 data port */ 1005724ba675SRob Herring <0x46400000 0x46400000 0x400000>; /* l3 data port */ 1006724ba675SRob Herring 1007724ba675SRob Herring segment@0 { /* 0x48000000 */ 1008724ba675SRob Herring compatible = "simple-pm-bus"; 1009724ba675SRob Herring #address-cells = <1>; 1010724ba675SRob Herring #size-cells = <1>; 1011724ba675SRob Herring ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 1012724ba675SRob Herring <0x00000800 0x00000800 0x000800>, /* ap 1 */ 1013724ba675SRob Herring <0x00001000 0x00001000 0x000400>, /* ap 2 */ 1014724ba675SRob Herring <0x00001400 0x00001400 0x000400>, /* ap 3 */ 1015724ba675SRob Herring <0x00001800 0x00001800 0x000400>, /* ap 4 */ 1016724ba675SRob Herring <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ 1017724ba675SRob Herring <0x00008000 0x00008000 0x001000>, /* ap 6 */ 1018724ba675SRob Herring <0x00009000 0x00009000 0x001000>, /* ap 7 */ 1019724ba675SRob Herring <0x00016000 0x00016000 0x001000>, /* ap 8 */ 1020724ba675SRob Herring <0x00017000 0x00017000 0x001000>, /* ap 9 */ 1021724ba675SRob Herring <0x00022000 0x00022000 0x001000>, /* ap 10 */ 1022724ba675SRob Herring <0x00023000 0x00023000 0x001000>, /* ap 11 */ 1023724ba675SRob Herring <0x00024000 0x00024000 0x001000>, /* ap 12 */ 1024724ba675SRob Herring <0x00025000 0x00025000 0x001000>, /* ap 13 */ 1025724ba675SRob Herring <0x0002a000 0x0002a000 0x001000>, /* ap 14 */ 1026724ba675SRob Herring <0x0002b000 0x0002b000 0x001000>, /* ap 15 */ 1027724ba675SRob Herring <0x00038000 0x00038000 0x002000>, /* ap 16 */ 1028724ba675SRob Herring <0x0003a000 0x0003a000 0x001000>, /* ap 17 */ 1029724ba675SRob Herring <0x00014000 0x00014000 0x001000>, /* ap 18 */ 1030724ba675SRob Herring <0x00015000 0x00015000 0x001000>, /* ap 19 */ 1031724ba675SRob Herring <0x0003c000 0x0003c000 0x002000>, /* ap 20 */ 1032724ba675SRob Herring <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ 1033724ba675SRob Herring <0x00040000 0x00040000 0x001000>, /* ap 22 */ 1034724ba675SRob Herring <0x00041000 0x00041000 0x001000>, /* ap 23 */ 1035724ba675SRob Herring <0x00042000 0x00042000 0x001000>, /* ap 24 */ 1036724ba675SRob Herring <0x00043000 0x00043000 0x001000>, /* ap 25 */ 1037724ba675SRob Herring <0x00044000 0x00044000 0x001000>, /* ap 26 */ 1038724ba675SRob Herring <0x00045000 0x00045000 0x001000>, /* ap 27 */ 1039724ba675SRob Herring <0x00046000 0x00046000 0x001000>, /* ap 28 */ 1040724ba675SRob Herring <0x00047000 0x00047000 0x001000>, /* ap 29 */ 1041724ba675SRob Herring <0x00048000 0x00048000 0x001000>, /* ap 30 */ 1042724ba675SRob Herring <0x00049000 0x00049000 0x001000>, /* ap 31 */ 1043724ba675SRob Herring <0x0004c000 0x0004c000 0x001000>, /* ap 32 */ 1044724ba675SRob Herring <0x0004d000 0x0004d000 0x001000>, /* ap 33 */ 1045724ba675SRob Herring <0x00050000 0x00050000 0x002000>, /* ap 34 */ 1046724ba675SRob Herring <0x00052000 0x00052000 0x001000>, /* ap 35 */ 1047724ba675SRob Herring <0x00060000 0x00060000 0x001000>, /* ap 36 */ 1048724ba675SRob Herring <0x00061000 0x00061000 0x001000>, /* ap 37 */ 1049724ba675SRob Herring <0x00080000 0x00080000 0x010000>, /* ap 38 */ 1050724ba675SRob Herring <0x00090000 0x00090000 0x001000>, /* ap 39 */ 1051724ba675SRob Herring <0x000a0000 0x000a0000 0x010000>, /* ap 40 */ 1052724ba675SRob Herring <0x000b0000 0x000b0000 0x001000>, /* ap 41 */ 1053724ba675SRob Herring <0x00030000 0x00030000 0x001000>, /* ap 77 */ 1054724ba675SRob Herring <0x00031000 0x00031000 0x001000>, /* ap 78 */ 1055724ba675SRob Herring <0x0004a000 0x0004a000 0x001000>, /* ap 85 */ 1056724ba675SRob Herring <0x0004b000 0x0004b000 0x001000>, /* ap 86 */ 1057724ba675SRob Herring <0x000c8000 0x000c8000 0x001000>, /* ap 87 */ 1058724ba675SRob Herring <0x000c9000 0x000c9000 0x001000>, /* ap 88 */ 1059724ba675SRob Herring <0x000cc000 0x000cc000 0x001000>, /* ap 89 */ 1060724ba675SRob Herring <0x000cd000 0x000cd000 0x001000>, /* ap 90 */ 1061724ba675SRob Herring <0x000ca000 0x000ca000 0x001000>, /* ap 91 */ 1062724ba675SRob Herring <0x000cb000 0x000cb000 0x001000>, /* ap 92 */ 1063724ba675SRob Herring <0x46000000 0x46000000 0x400000>, /* l3 data port */ 1064724ba675SRob Herring <0x46400000 0x46400000 0x400000>; /* l3 data port */ 1065724ba675SRob Herring 1066724ba675SRob Herring target-module@8000 { /* 0x48008000, ap 6 10.0 */ 1067724ba675SRob Herring compatible = "ti,sysc"; 1068724ba675SRob Herring status = "disabled"; 1069724ba675SRob Herring #address-cells = <1>; 1070724ba675SRob Herring #size-cells = <1>; 1071724ba675SRob Herring ranges = <0x0 0x8000 0x1000>; 1072724ba675SRob Herring }; 1073724ba675SRob Herring 1074724ba675SRob Herring target-module@14000 { /* 0x48014000, ap 18 58.0 */ 1075724ba675SRob Herring compatible = "ti,sysc"; 1076724ba675SRob Herring status = "disabled"; 1077724ba675SRob Herring #address-cells = <1>; 1078724ba675SRob Herring #size-cells = <1>; 1079724ba675SRob Herring ranges = <0x0 0x14000 0x1000>; 1080724ba675SRob Herring }; 1081724ba675SRob Herring 1082724ba675SRob Herring target-module@16000 { /* 0x48016000, ap 8 3c.0 */ 1083724ba675SRob Herring compatible = "ti,sysc"; 1084724ba675SRob Herring status = "disabled"; 1085724ba675SRob Herring #address-cells = <1>; 1086724ba675SRob Herring #size-cells = <1>; 1087724ba675SRob Herring ranges = <0x0 0x16000 0x1000>; 1088724ba675SRob Herring }; 1089724ba675SRob Herring 1090724ba675SRob Herring target-module@22000 { /* 0x48022000, ap 10 12.0 */ 1091724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1092724ba675SRob Herring reg = <0x22050 0x4>, 1093724ba675SRob Herring <0x22054 0x4>, 1094724ba675SRob Herring <0x22058 0x4>; 1095724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1096724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1097724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1098724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1099724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1100724ba675SRob Herring <SYSC_IDLE_NO>, 1101724ba675SRob Herring <SYSC_IDLE_SMART>, 1102724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1103724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1104724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; 1105724ba675SRob Herring clock-names = "fck"; 1106724ba675SRob Herring #address-cells = <1>; 1107724ba675SRob Herring #size-cells = <1>; 1108724ba675SRob Herring ranges = <0x0 0x22000 0x1000>; 1109724ba675SRob Herring 1110724ba675SRob Herring uart1: serial@0 { 1111724ba675SRob Herring compatible = "ti,am3352-uart", "ti,omap3-uart"; 1112724ba675SRob Herring clock-frequency = <48000000>; 1113724ba675SRob Herring reg = <0x0 0x1000>; 1114724ba675SRob Herring interrupts = <73>; 1115724ba675SRob Herring status = "disabled"; 1116724ba675SRob Herring dmas = <&edma 28 0>, <&edma 29 0>; 1117724ba675SRob Herring dma-names = "tx", "rx"; 1118724ba675SRob Herring }; 1119724ba675SRob Herring }; 1120724ba675SRob Herring 1121724ba675SRob Herring target-module@24000 { /* 0x48024000, ap 12 14.0 */ 1122724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1123724ba675SRob Herring reg = <0x24050 0x4>, 1124724ba675SRob Herring <0x24054 0x4>, 1125724ba675SRob Herring <0x24058 0x4>; 1126724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1127724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1128724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1129724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1130724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1131724ba675SRob Herring <SYSC_IDLE_NO>, 1132724ba675SRob Herring <SYSC_IDLE_SMART>, 1133724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1134724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1135724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>; 1136724ba675SRob Herring clock-names = "fck"; 1137724ba675SRob Herring #address-cells = <1>; 1138724ba675SRob Herring #size-cells = <1>; 1139724ba675SRob Herring ranges = <0x0 0x24000 0x1000>; 1140724ba675SRob Herring 1141724ba675SRob Herring uart2: serial@0 { 1142724ba675SRob Herring compatible = "ti,am3352-uart", "ti,omap3-uart"; 1143724ba675SRob Herring clock-frequency = <48000000>; 1144724ba675SRob Herring reg = <0x0 0x1000>; 1145724ba675SRob Herring interrupts = <74>; 1146724ba675SRob Herring status = "disabled"; 1147724ba675SRob Herring dmas = <&edma 30 0>, <&edma 31 0>; 1148724ba675SRob Herring dma-names = "tx", "rx"; 1149724ba675SRob Herring }; 1150724ba675SRob Herring }; 1151724ba675SRob Herring 1152724ba675SRob Herring target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */ 1153724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1154724ba675SRob Herring reg = <0x2a000 0x8>, 1155724ba675SRob Herring <0x2a010 0x8>, 1156724ba675SRob Herring <0x2a090 0x8>; 1157724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1158724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1159724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1160724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1161724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1162724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1163724ba675SRob Herring <SYSC_IDLE_NO>, 1164724ba675SRob Herring <SYSC_IDLE_SMART>, 1165724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1166724ba675SRob Herring ti,syss-mask = <1>; 1167724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1168724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>; 1169724ba675SRob Herring clock-names = "fck"; 1170724ba675SRob Herring #address-cells = <1>; 1171724ba675SRob Herring #size-cells = <1>; 1172724ba675SRob Herring ranges = <0x0 0x2a000 0x1000>; 1173724ba675SRob Herring 1174724ba675SRob Herring i2c1: i2c@0 { 1175724ba675SRob Herring compatible = "ti,omap4-i2c"; 1176724ba675SRob Herring #address-cells = <1>; 1177724ba675SRob Herring #size-cells = <0>; 1178724ba675SRob Herring reg = <0x0 0x1000>; 1179724ba675SRob Herring interrupts = <71>; 1180724ba675SRob Herring status = "disabled"; 1181724ba675SRob Herring }; 1182724ba675SRob Herring }; 1183724ba675SRob Herring 1184724ba675SRob Herring target-module@30000 { /* 0x48030000, ap 77 08.0 */ 1185724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1186724ba675SRob Herring reg = <0x30000 0x4>, 1187724ba675SRob Herring <0x30110 0x4>, 1188724ba675SRob Herring <0x30114 0x4>; 1189724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1190724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1191724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1192724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1193724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1194724ba675SRob Herring <SYSC_IDLE_NO>, 1195724ba675SRob Herring <SYSC_IDLE_SMART>; 1196724ba675SRob Herring ti,syss-mask = <1>; 1197724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1198724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>; 1199724ba675SRob Herring clock-names = "fck"; 1200724ba675SRob Herring #address-cells = <1>; 1201724ba675SRob Herring #size-cells = <1>; 1202724ba675SRob Herring ranges = <0x0 0x30000 0x1000>; 1203724ba675SRob Herring 1204724ba675SRob Herring spi0: spi@0 { 1205724ba675SRob Herring compatible = "ti,omap4-mcspi"; 1206724ba675SRob Herring #address-cells = <1>; 1207724ba675SRob Herring #size-cells = <0>; 1208724ba675SRob Herring reg = <0x0 0x400>; 1209724ba675SRob Herring interrupts = <65>; 1210724ba675SRob Herring ti,spi-num-cs = <2>; 1211724ba675SRob Herring dmas = <&edma 16 0 1212724ba675SRob Herring &edma 17 0 1213724ba675SRob Herring &edma 18 0 1214724ba675SRob Herring &edma 19 0>; 1215724ba675SRob Herring dma-names = "tx0", "rx0", "tx1", "rx1"; 1216724ba675SRob Herring status = "disabled"; 1217724ba675SRob Herring }; 1218724ba675SRob Herring }; 1219724ba675SRob Herring 1220724ba675SRob Herring target-module@38000 { /* 0x48038000, ap 16 02.0 */ 1221724ba675SRob Herring compatible = "ti,sysc-omap4-simple", "ti,sysc"; 1222724ba675SRob Herring reg = <0x38000 0x4>, 1223724ba675SRob Herring <0x38004 0x4>; 1224724ba675SRob Herring reg-names = "rev", "sysc"; 1225724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1226724ba675SRob Herring <SYSC_IDLE_NO>, 1227724ba675SRob Herring <SYSC_IDLE_SMART>; 1228724ba675SRob Herring /* Domains (P, C): per_pwrdm, l3s_clkdm */ 1229724ba675SRob Herring clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>; 1230724ba675SRob Herring clock-names = "fck"; 1231724ba675SRob Herring #address-cells = <1>; 1232724ba675SRob Herring #size-cells = <1>; 1233724ba675SRob Herring ranges = <0x0 0x38000 0x2000>, 1234724ba675SRob Herring <0x46000000 0x46000000 0x400000>; 1235724ba675SRob Herring 1236724ba675SRob Herring mcasp0: mcasp@0 { 1237724ba675SRob Herring compatible = "ti,am33xx-mcasp-audio"; 1238724ba675SRob Herring reg = <0x0 0x2000>, 1239724ba675SRob Herring <0x46000000 0x400000>; 1240724ba675SRob Herring reg-names = "mpu", "dat"; 1241724ba675SRob Herring interrupts = <80>, <81>; 1242724ba675SRob Herring interrupt-names = "tx", "rx"; 1243724ba675SRob Herring status = "disabled"; 1244724ba675SRob Herring dmas = <&edma 8 2>, 1245724ba675SRob Herring <&edma 9 2>; 1246724ba675SRob Herring dma-names = "tx", "rx"; 1247724ba675SRob Herring }; 1248724ba675SRob Herring }; 1249724ba675SRob Herring 1250724ba675SRob Herring target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ 1251724ba675SRob Herring compatible = "ti,sysc-omap4-simple", "ti,sysc"; 1252724ba675SRob Herring reg = <0x3c000 0x4>, 1253724ba675SRob Herring <0x3c004 0x4>; 1254724ba675SRob Herring reg-names = "rev", "sysc"; 1255724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1256724ba675SRob Herring <SYSC_IDLE_NO>, 1257724ba675SRob Herring <SYSC_IDLE_SMART>; 1258724ba675SRob Herring /* Domains (P, C): per_pwrdm, l3s_clkdm */ 1259724ba675SRob Herring clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>; 1260724ba675SRob Herring clock-names = "fck"; 1261724ba675SRob Herring #address-cells = <1>; 1262724ba675SRob Herring #size-cells = <1>; 1263724ba675SRob Herring ranges = <0x0 0x3c000 0x2000>, 1264724ba675SRob Herring <0x46400000 0x46400000 0x400000>; 1265724ba675SRob Herring 1266724ba675SRob Herring mcasp1: mcasp@0 { 1267724ba675SRob Herring compatible = "ti,am33xx-mcasp-audio"; 1268724ba675SRob Herring reg = <0x0 0x2000>, 1269724ba675SRob Herring <0x46400000 0x400000>; 1270724ba675SRob Herring reg-names = "mpu", "dat"; 1271724ba675SRob Herring interrupts = <82>, <83>; 1272724ba675SRob Herring interrupt-names = "tx", "rx"; 1273724ba675SRob Herring status = "disabled"; 1274724ba675SRob Herring dmas = <&edma 10 2>, 1275724ba675SRob Herring <&edma 11 2>; 1276724ba675SRob Herring dma-names = "tx", "rx"; 1277724ba675SRob Herring }; 1278724ba675SRob Herring }; 1279724ba675SRob Herring 1280724ba675SRob Herring timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */ 1281724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1282724ba675SRob Herring reg = <0x40000 0x4>, 1283724ba675SRob Herring <0x40010 0x4>, 1284724ba675SRob Herring <0x40014 0x4>; 1285724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1286724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1287724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1288724ba675SRob Herring <SYSC_IDLE_NO>, 1289724ba675SRob Herring <SYSC_IDLE_SMART>, 1290724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1291724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1292724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>; 1293724ba675SRob Herring clock-names = "fck"; 1294724ba675SRob Herring #address-cells = <1>; 1295724ba675SRob Herring #size-cells = <1>; 1296724ba675SRob Herring ranges = <0x0 0x40000 0x1000>; 1297724ba675SRob Herring 1298724ba675SRob Herring timer2: timer@0 { 1299724ba675SRob Herring compatible = "ti,am335x-timer"; 1300724ba675SRob Herring reg = <0x0 0x400>; 1301724ba675SRob Herring interrupts = <68>; 1302724ba675SRob Herring clocks = <&timer2_fck>; 1303724ba675SRob Herring clock-names = "fck"; 1304724ba675SRob Herring }; 1305724ba675SRob Herring }; 1306724ba675SRob Herring 1307724ba675SRob Herring target-module@42000 { /* 0x48042000, ap 24 1c.0 */ 1308724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1309724ba675SRob Herring reg = <0x42000 0x4>, 1310724ba675SRob Herring <0x42010 0x4>, 1311724ba675SRob Herring <0x42014 0x4>; 1312724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1313724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1314724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1315724ba675SRob Herring <SYSC_IDLE_NO>, 1316724ba675SRob Herring <SYSC_IDLE_SMART>, 1317724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1318724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1319724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>; 1320724ba675SRob Herring clock-names = "fck"; 1321724ba675SRob Herring #address-cells = <1>; 1322724ba675SRob Herring #size-cells = <1>; 1323724ba675SRob Herring ranges = <0x0 0x42000 0x1000>; 1324724ba675SRob Herring 1325724ba675SRob Herring timer3: timer@0 { 1326724ba675SRob Herring compatible = "ti,am335x-timer"; 1327724ba675SRob Herring reg = <0x0 0x400>; 1328724ba675SRob Herring interrupts = <69>; 1329724ba675SRob Herring }; 1330724ba675SRob Herring }; 1331724ba675SRob Herring 1332724ba675SRob Herring target-module@44000 { /* 0x48044000, ap 26 26.0 */ 1333724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1334724ba675SRob Herring reg = <0x44000 0x4>, 1335724ba675SRob Herring <0x44010 0x4>, 1336724ba675SRob Herring <0x44014 0x4>; 1337724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1338724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1339724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1340724ba675SRob Herring <SYSC_IDLE_NO>, 1341724ba675SRob Herring <SYSC_IDLE_SMART>, 1342724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1343724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1344724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>; 1345724ba675SRob Herring clock-names = "fck"; 1346724ba675SRob Herring #address-cells = <1>; 1347724ba675SRob Herring #size-cells = <1>; 1348724ba675SRob Herring ranges = <0x0 0x44000 0x1000>; 1349724ba675SRob Herring 1350724ba675SRob Herring timer4: timer@0 { 1351724ba675SRob Herring compatible = "ti,am335x-timer"; 1352724ba675SRob Herring reg = <0x0 0x400>; 1353724ba675SRob Herring interrupts = <92>; 1354724ba675SRob Herring ti,timer-pwm; 1355724ba675SRob Herring }; 1356724ba675SRob Herring }; 1357724ba675SRob Herring 1358724ba675SRob Herring target-module@46000 { /* 0x48046000, ap 28 28.0 */ 1359724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1360724ba675SRob Herring reg = <0x46000 0x4>, 1361724ba675SRob Herring <0x46010 0x4>, 1362724ba675SRob Herring <0x46014 0x4>; 1363724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1364724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1365724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1366724ba675SRob Herring <SYSC_IDLE_NO>, 1367724ba675SRob Herring <SYSC_IDLE_SMART>, 1368724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1369724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1370724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>; 1371724ba675SRob Herring clock-names = "fck"; 1372724ba675SRob Herring #address-cells = <1>; 1373724ba675SRob Herring #size-cells = <1>; 1374724ba675SRob Herring ranges = <0x0 0x46000 0x1000>; 1375724ba675SRob Herring 1376724ba675SRob Herring timer5: timer@0 { 1377724ba675SRob Herring compatible = "ti,am335x-timer"; 1378724ba675SRob Herring reg = <0x0 0x400>; 1379724ba675SRob Herring interrupts = <93>; 1380724ba675SRob Herring ti,timer-pwm; 1381724ba675SRob Herring }; 1382724ba675SRob Herring }; 1383724ba675SRob Herring 1384724ba675SRob Herring target-module@48000 { /* 0x48048000, ap 30 22.0 */ 1385724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1386724ba675SRob Herring reg = <0x48000 0x4>, 1387724ba675SRob Herring <0x48010 0x4>, 1388724ba675SRob Herring <0x48014 0x4>; 1389724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1390724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1391724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1392724ba675SRob Herring <SYSC_IDLE_NO>, 1393724ba675SRob Herring <SYSC_IDLE_SMART>, 1394724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1395724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1396724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>; 1397724ba675SRob Herring clock-names = "fck"; 1398724ba675SRob Herring #address-cells = <1>; 1399724ba675SRob Herring #size-cells = <1>; 1400724ba675SRob Herring ranges = <0x0 0x48000 0x1000>; 1401724ba675SRob Herring 1402724ba675SRob Herring timer6: timer@0 { 1403724ba675SRob Herring compatible = "ti,am335x-timer"; 1404724ba675SRob Herring reg = <0x0 0x400>; 1405724ba675SRob Herring interrupts = <94>; 1406724ba675SRob Herring ti,timer-pwm; 1407724ba675SRob Herring }; 1408724ba675SRob Herring }; 1409724ba675SRob Herring 1410724ba675SRob Herring target-module@4a000 { /* 0x4804a000, ap 85 60.0 */ 1411724ba675SRob Herring compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1412724ba675SRob Herring reg = <0x4a000 0x4>, 1413724ba675SRob Herring <0x4a010 0x4>, 1414724ba675SRob Herring <0x4a014 0x4>; 1415724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1416724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1417724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1418724ba675SRob Herring <SYSC_IDLE_NO>, 1419724ba675SRob Herring <SYSC_IDLE_SMART>, 1420724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1421724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1422724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>; 1423724ba675SRob Herring clock-names = "fck"; 1424724ba675SRob Herring #address-cells = <1>; 1425724ba675SRob Herring #size-cells = <1>; 1426724ba675SRob Herring ranges = <0x0 0x4a000 0x1000>; 1427724ba675SRob Herring 1428724ba675SRob Herring timer7: timer@0 { 1429724ba675SRob Herring compatible = "ti,am335x-timer"; 1430724ba675SRob Herring reg = <0x0 0x400>; 1431724ba675SRob Herring interrupts = <95>; 1432724ba675SRob Herring ti,timer-pwm; 1433724ba675SRob Herring }; 1434724ba675SRob Herring }; 1435724ba675SRob Herring 1436724ba675SRob Herring target-module@4c000 { /* 0x4804c000, ap 32 36.0 */ 1437724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1438724ba675SRob Herring reg = <0x4c000 0x4>, 1439724ba675SRob Herring <0x4c010 0x4>, 1440724ba675SRob Herring <0x4c114 0x4>; 1441724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1442724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1443724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1444724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1445724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1446724ba675SRob Herring <SYSC_IDLE_NO>, 1447724ba675SRob Herring <SYSC_IDLE_SMART>, 1448724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1449724ba675SRob Herring ti,syss-mask = <1>; 1450724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1451724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>, 1452724ba675SRob Herring <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>; 1453724ba675SRob Herring clock-names = "fck", "dbclk"; 1454724ba675SRob Herring #address-cells = <1>; 1455724ba675SRob Herring #size-cells = <1>; 1456724ba675SRob Herring ranges = <0x0 0x4c000 0x1000>; 1457724ba675SRob Herring 1458724ba675SRob Herring gpio1: gpio@0 { 1459724ba675SRob Herring compatible = "ti,omap4-gpio"; 1460724ba675SRob Herring gpio-ranges = <&am33xx_pinmux 0 0 8>, 1461724ba675SRob Herring <&am33xx_pinmux 8 90 4>, 1462724ba675SRob Herring <&am33xx_pinmux 12 12 16>, 1463724ba675SRob Herring <&am33xx_pinmux 28 30 4>; 1464724ba675SRob Herring gpio-controller; 1465724ba675SRob Herring #gpio-cells = <2>; 1466724ba675SRob Herring interrupt-controller; 1467724ba675SRob Herring #interrupt-cells = <2>; 1468724ba675SRob Herring reg = <0x0 0x1000>; 1469724ba675SRob Herring interrupts = <98>; 1470724ba675SRob Herring }; 1471724ba675SRob Herring }; 1472724ba675SRob Herring 1473724ba675SRob Herring target-module@50000 { /* 0x48050000, ap 34 2c.0 */ 1474724ba675SRob Herring compatible = "ti,sysc"; 1475724ba675SRob Herring status = "disabled"; 1476724ba675SRob Herring #address-cells = <1>; 1477724ba675SRob Herring #size-cells = <1>; 1478724ba675SRob Herring ranges = <0x0 0x50000 0x2000>; 1479724ba675SRob Herring }; 1480724ba675SRob Herring 1481724ba675SRob Herring target-module@60000 { /* 0x48060000, ap 36 0c.0 */ 1482724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1483724ba675SRob Herring reg = <0x602fc 0x4>, 1484724ba675SRob Herring <0x60110 0x4>, 1485724ba675SRob Herring <0x60114 0x4>; 1486724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1487724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1488724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1489724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1490724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1491724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1492724ba675SRob Herring <SYSC_IDLE_NO>, 1493724ba675SRob Herring <SYSC_IDLE_SMART>; 1494724ba675SRob Herring ti,syss-mask = <1>; 1495724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1496724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>; 1497724ba675SRob Herring clock-names = "fck"; 1498724ba675SRob Herring #address-cells = <1>; 1499724ba675SRob Herring #size-cells = <1>; 1500724ba675SRob Herring ranges = <0x0 0x60000 0x1000>; 1501724ba675SRob Herring 1502724ba675SRob Herring mmc1: mmc@0 { 1503724ba675SRob Herring compatible = "ti,am335-sdhci"; 1504724ba675SRob Herring ti,needs-special-reset; 1505724ba675SRob Herring dmas = <&edma 24 0>, <&edma 25 0>; 1506724ba675SRob Herring dma-names = "tx", "rx"; 1507724ba675SRob Herring interrupts = <64>; 1508724ba675SRob Herring reg = <0x0 0x1000>; 1509724ba675SRob Herring status = "disabled"; 1510724ba675SRob Herring }; 1511724ba675SRob Herring }; 1512724ba675SRob Herring 1513724ba675SRob Herring target-module@80000 { /* 0x48080000, ap 38 18.0 */ 1514724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1515724ba675SRob Herring reg = <0x80000 0x4>, 1516724ba675SRob Herring <0x80010 0x4>, 1517724ba675SRob Herring <0x80014 0x4>; 1518724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1519724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1520724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1521724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1522724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1523724ba675SRob Herring <SYSC_IDLE_NO>, 1524724ba675SRob Herring <SYSC_IDLE_SMART>; 1525724ba675SRob Herring ti,syss-mask = <1>; 1526724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1527724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>; 1528724ba675SRob Herring clock-names = "fck"; 1529724ba675SRob Herring #address-cells = <1>; 1530724ba675SRob Herring #size-cells = <1>; 1531724ba675SRob Herring ranges = <0x0 0x80000 0x10000>; 1532724ba675SRob Herring 1533724ba675SRob Herring elm: elm@0 { 1534724ba675SRob Herring compatible = "ti,am3352-elm"; 1535724ba675SRob Herring reg = <0x0 0x2000>; 1536724ba675SRob Herring interrupts = <4>; 1537724ba675SRob Herring status = "disabled"; 1538724ba675SRob Herring }; 1539724ba675SRob Herring }; 1540724ba675SRob Herring 1541724ba675SRob Herring target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */ 1542724ba675SRob Herring compatible = "ti,sysc"; 1543724ba675SRob Herring status = "disabled"; 1544724ba675SRob Herring #address-cells = <1>; 1545724ba675SRob Herring #size-cells = <1>; 1546724ba675SRob Herring ranges = <0x0 0xa0000 0x10000>; 1547724ba675SRob Herring }; 1548724ba675SRob Herring 1549724ba675SRob Herring target-module@c8000 { /* 0x480c8000, ap 87 06.0 */ 1550724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1551724ba675SRob Herring reg = <0xc8000 0x4>, 1552724ba675SRob Herring <0xc8010 0x4>; 1553724ba675SRob Herring reg-names = "rev", "sysc"; 1554724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1555724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1556724ba675SRob Herring <SYSC_IDLE_NO>, 1557724ba675SRob Herring <SYSC_IDLE_SMART>; 1558724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1559724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>; 1560724ba675SRob Herring clock-names = "fck"; 1561724ba675SRob Herring #address-cells = <1>; 1562724ba675SRob Herring #size-cells = <1>; 1563724ba675SRob Herring ranges = <0x0 0xc8000 0x1000>; 1564724ba675SRob Herring 1565724ba675SRob Herring mailbox: mailbox@0 { 1566724ba675SRob Herring compatible = "ti,omap4-mailbox"; 1567724ba675SRob Herring reg = <0x0 0x200>; 1568724ba675SRob Herring interrupts = <77>; 1569724ba675SRob Herring #mbox-cells = <1>; 1570724ba675SRob Herring ti,mbox-num-users = <4>; 1571724ba675SRob Herring ti,mbox-num-fifos = <8>; 1572724ba675SRob Herring mbox_wkupm3: mbox-wkup-m3 { 1573724ba675SRob Herring ti,mbox-send-noirq; 1574724ba675SRob Herring ti,mbox-tx = <0 0 0>; 1575724ba675SRob Herring ti,mbox-rx = <0 0 3>; 1576724ba675SRob Herring }; 1577724ba675SRob Herring }; 1578724ba675SRob Herring }; 1579724ba675SRob Herring 1580724ba675SRob Herring target-module@ca000 { /* 0x480ca000, ap 91 40.0 */ 1581724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1582724ba675SRob Herring reg = <0xca000 0x4>, 1583724ba675SRob Herring <0xca010 0x4>, 1584724ba675SRob Herring <0xca014 0x4>; 1585724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1586724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1587724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1588724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1589724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1590724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1591724ba675SRob Herring <SYSC_IDLE_NO>, 1592724ba675SRob Herring <SYSC_IDLE_SMART>; 1593724ba675SRob Herring ti,syss-mask = <1>; 1594724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1595724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>; 1596724ba675SRob Herring clock-names = "fck"; 1597724ba675SRob Herring #address-cells = <1>; 1598724ba675SRob Herring #size-cells = <1>; 1599724ba675SRob Herring ranges = <0x0 0xca000 0x1000>; 1600724ba675SRob Herring 1601724ba675SRob Herring hwspinlock: spinlock@0 { 1602724ba675SRob Herring compatible = "ti,omap4-hwspinlock"; 1603724ba675SRob Herring reg = <0x0 0x1000>; 1604724ba675SRob Herring #hwlock-cells = <1>; 1605724ba675SRob Herring }; 1606724ba675SRob Herring }; 1607724ba675SRob Herring 1608724ba675SRob Herring target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */ 1609724ba675SRob Herring compatible = "ti,sysc"; 1610724ba675SRob Herring status = "disabled"; 1611724ba675SRob Herring #address-cells = <1>; 1612724ba675SRob Herring #size-cells = <1>; 1613724ba675SRob Herring ranges = <0x0 0xcc000 0x1000>; 1614724ba675SRob Herring }; 1615724ba675SRob Herring }; 1616724ba675SRob Herring 1617724ba675SRob Herring segment@100000 { /* 0x48100000 */ 1618724ba675SRob Herring compatible = "simple-pm-bus"; 1619724ba675SRob Herring #address-cells = <1>; 1620724ba675SRob Herring #size-cells = <1>; 1621724ba675SRob Herring ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */ 1622724ba675SRob Herring <0x0008d000 0x0018d000 0x001000>, /* ap 43 */ 1623724ba675SRob Herring <0x0008e000 0x0018e000 0x001000>, /* ap 44 */ 1624724ba675SRob Herring <0x0008f000 0x0018f000 0x001000>, /* ap 45 */ 1625724ba675SRob Herring <0x0009c000 0x0019c000 0x001000>, /* ap 46 */ 1626724ba675SRob Herring <0x0009d000 0x0019d000 0x001000>, /* ap 47 */ 1627724ba675SRob Herring <0x000a6000 0x001a6000 0x001000>, /* ap 48 */ 1628724ba675SRob Herring <0x000a7000 0x001a7000 0x001000>, /* ap 49 */ 1629724ba675SRob Herring <0x000a8000 0x001a8000 0x001000>, /* ap 50 */ 1630724ba675SRob Herring <0x000a9000 0x001a9000 0x001000>, /* ap 51 */ 1631724ba675SRob Herring <0x000aa000 0x001aa000 0x001000>, /* ap 52 */ 1632724ba675SRob Herring <0x000ab000 0x001ab000 0x001000>, /* ap 53 */ 1633724ba675SRob Herring <0x000ac000 0x001ac000 0x001000>, /* ap 54 */ 1634724ba675SRob Herring <0x000ad000 0x001ad000 0x001000>, /* ap 55 */ 1635724ba675SRob Herring <0x000ae000 0x001ae000 0x001000>, /* ap 56 */ 1636724ba675SRob Herring <0x000af000 0x001af000 0x001000>, /* ap 57 */ 1637724ba675SRob Herring <0x000b0000 0x001b0000 0x010000>, /* ap 58 */ 1638724ba675SRob Herring <0x000c0000 0x001c0000 0x001000>, /* ap 59 */ 1639724ba675SRob Herring <0x000cc000 0x001cc000 0x002000>, /* ap 60 */ 1640724ba675SRob Herring <0x000ce000 0x001ce000 0x002000>, /* ap 61 */ 1641724ba675SRob Herring <0x000d0000 0x001d0000 0x002000>, /* ap 62 */ 1642724ba675SRob Herring <0x000d2000 0x001d2000 0x002000>, /* ap 63 */ 1643724ba675SRob Herring <0x000d8000 0x001d8000 0x001000>, /* ap 64 */ 1644724ba675SRob Herring <0x000d9000 0x001d9000 0x001000>, /* ap 65 */ 1645724ba675SRob Herring <0x000a0000 0x001a0000 0x001000>, /* ap 79 */ 1646724ba675SRob Herring <0x000a1000 0x001a1000 0x001000>, /* ap 80 */ 1647724ba675SRob Herring <0x000a2000 0x001a2000 0x001000>, /* ap 81 */ 1648724ba675SRob Herring <0x000a3000 0x001a3000 0x001000>, /* ap 82 */ 1649724ba675SRob Herring <0x000a4000 0x001a4000 0x001000>, /* ap 83 */ 1650724ba675SRob Herring <0x000a5000 0x001a5000 0x001000>; /* ap 84 */ 1651724ba675SRob Herring 1652724ba675SRob Herring target-module@8c000 { /* 0x4818c000, ap 42 04.0 */ 1653724ba675SRob Herring compatible = "ti,sysc"; 1654724ba675SRob Herring status = "disabled"; 1655724ba675SRob Herring #address-cells = <1>; 1656724ba675SRob Herring #size-cells = <1>; 1657724ba675SRob Herring ranges = <0x0 0x8c000 0x1000>; 1658724ba675SRob Herring }; 1659724ba675SRob Herring 1660724ba675SRob Herring target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */ 1661724ba675SRob Herring compatible = "ti,sysc"; 1662724ba675SRob Herring status = "disabled"; 1663724ba675SRob Herring #address-cells = <1>; 1664724ba675SRob Herring #size-cells = <1>; 1665724ba675SRob Herring ranges = <0x0 0x8e000 0x1000>; 1666724ba675SRob Herring }; 1667724ba675SRob Herring 1668724ba675SRob Herring target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */ 1669724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1670724ba675SRob Herring reg = <0x9c000 0x8>, 1671724ba675SRob Herring <0x9c010 0x8>, 1672724ba675SRob Herring <0x9c090 0x8>; 1673724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1674724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1675724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1676724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1677724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1678724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1679724ba675SRob Herring <SYSC_IDLE_NO>, 1680724ba675SRob Herring <SYSC_IDLE_SMART>, 1681724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1682724ba675SRob Herring ti,syss-mask = <1>; 1683724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1684724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>; 1685724ba675SRob Herring clock-names = "fck"; 1686724ba675SRob Herring #address-cells = <1>; 1687724ba675SRob Herring #size-cells = <1>; 1688724ba675SRob Herring ranges = <0x0 0x9c000 0x1000>; 1689724ba675SRob Herring 1690724ba675SRob Herring i2c2: i2c@0 { 1691724ba675SRob Herring compatible = "ti,omap4-i2c"; 1692724ba675SRob Herring #address-cells = <1>; 1693724ba675SRob Herring #size-cells = <0>; 1694724ba675SRob Herring reg = <0x0 0x1000>; 1695724ba675SRob Herring interrupts = <30>; 1696724ba675SRob Herring status = "disabled"; 1697724ba675SRob Herring }; 1698724ba675SRob Herring }; 1699724ba675SRob Herring 1700724ba675SRob Herring target-module@a0000 { /* 0x481a0000, ap 79 24.0 */ 1701724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1702724ba675SRob Herring reg = <0xa0000 0x4>, 1703724ba675SRob Herring <0xa0110 0x4>, 1704724ba675SRob Herring <0xa0114 0x4>; 1705724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1706724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1707724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1708724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1709724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1710724ba675SRob Herring <SYSC_IDLE_NO>, 1711724ba675SRob Herring <SYSC_IDLE_SMART>; 1712724ba675SRob Herring ti,syss-mask = <1>; 1713724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1714724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>; 1715724ba675SRob Herring clock-names = "fck"; 1716724ba675SRob Herring #address-cells = <1>; 1717724ba675SRob Herring #size-cells = <1>; 1718724ba675SRob Herring ranges = <0x0 0xa0000 0x1000>; 1719724ba675SRob Herring 1720724ba675SRob Herring spi1: spi@0 { 1721724ba675SRob Herring compatible = "ti,omap4-mcspi"; 1722724ba675SRob Herring #address-cells = <1>; 1723724ba675SRob Herring #size-cells = <0>; 1724724ba675SRob Herring reg = <0x0 0x400>; 1725724ba675SRob Herring interrupts = <125>; 1726724ba675SRob Herring ti,spi-num-cs = <2>; 1727724ba675SRob Herring dmas = <&edma 42 0 1728724ba675SRob Herring &edma 43 0 1729724ba675SRob Herring &edma 44 0 1730724ba675SRob Herring &edma 45 0>; 1731724ba675SRob Herring dma-names = "tx0", "rx0", "tx1", "rx1"; 1732724ba675SRob Herring status = "disabled"; 1733724ba675SRob Herring }; 1734724ba675SRob Herring }; 1735724ba675SRob Herring 1736724ba675SRob Herring target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */ 1737724ba675SRob Herring compatible = "ti,sysc"; 1738724ba675SRob Herring status = "disabled"; 1739724ba675SRob Herring #address-cells = <1>; 1740724ba675SRob Herring #size-cells = <1>; 1741724ba675SRob Herring ranges = <0x0 0xa2000 0x1000>; 1742724ba675SRob Herring }; 1743724ba675SRob Herring 1744724ba675SRob Herring target-module@a4000 { /* 0x481a4000, ap 83 30.0 */ 1745724ba675SRob Herring compatible = "ti,sysc"; 1746724ba675SRob Herring status = "disabled"; 1747724ba675SRob Herring #address-cells = <1>; 1748724ba675SRob Herring #size-cells = <1>; 1749724ba675SRob Herring ranges = <0x0 0xa4000 0x1000>; 1750724ba675SRob Herring }; 1751724ba675SRob Herring 1752724ba675SRob Herring target-module@a6000 { /* 0x481a6000, ap 48 16.0 */ 1753724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1754724ba675SRob Herring reg = <0xa6050 0x4>, 1755724ba675SRob Herring <0xa6054 0x4>, 1756724ba675SRob Herring <0xa6058 0x4>; 1757724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1758724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1759724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1760724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1761724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1762724ba675SRob Herring <SYSC_IDLE_NO>, 1763724ba675SRob Herring <SYSC_IDLE_SMART>, 1764724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1765724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1766724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>; 1767724ba675SRob Herring clock-names = "fck"; 1768724ba675SRob Herring #address-cells = <1>; 1769724ba675SRob Herring #size-cells = <1>; 1770724ba675SRob Herring ranges = <0x0 0xa6000 0x1000>; 1771724ba675SRob Herring 1772724ba675SRob Herring uart3: serial@0 { 1773724ba675SRob Herring compatible = "ti,am3352-uart", "ti,omap3-uart"; 1774724ba675SRob Herring clock-frequency = <48000000>; 1775724ba675SRob Herring reg = <0x0 0x1000>; 1776724ba675SRob Herring interrupts = <44>; 1777724ba675SRob Herring status = "disabled"; 1778724ba675SRob Herring }; 1779724ba675SRob Herring }; 1780724ba675SRob Herring 1781724ba675SRob Herring target-module@a8000 { /* 0x481a8000, ap 50 20.0 */ 1782724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1783724ba675SRob Herring reg = <0xa8050 0x4>, 1784724ba675SRob Herring <0xa8054 0x4>, 1785724ba675SRob Herring <0xa8058 0x4>; 1786724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1787724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1788724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1789724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1790724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1791724ba675SRob Herring <SYSC_IDLE_NO>, 1792724ba675SRob Herring <SYSC_IDLE_SMART>, 1793724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1794724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1795724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>; 1796724ba675SRob Herring clock-names = "fck"; 1797724ba675SRob Herring #address-cells = <1>; 1798724ba675SRob Herring #size-cells = <1>; 1799724ba675SRob Herring ranges = <0x0 0xa8000 0x1000>; 1800724ba675SRob Herring 1801724ba675SRob Herring uart4: serial@0 { 1802724ba675SRob Herring compatible = "ti,am3352-uart", "ti,omap3-uart"; 1803724ba675SRob Herring clock-frequency = <48000000>; 1804724ba675SRob Herring reg = <0x0 0x1000>; 1805724ba675SRob Herring interrupts = <45>; 1806724ba675SRob Herring status = "disabled"; 1807724ba675SRob Herring }; 1808724ba675SRob Herring }; 1809724ba675SRob Herring 1810724ba675SRob Herring target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */ 1811724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1812724ba675SRob Herring reg = <0xaa050 0x4>, 1813724ba675SRob Herring <0xaa054 0x4>, 1814724ba675SRob Herring <0xaa058 0x4>; 1815724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1816724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1817724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1818724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1819724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1820724ba675SRob Herring <SYSC_IDLE_NO>, 1821724ba675SRob Herring <SYSC_IDLE_SMART>, 1822724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1823724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1824724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>; 1825724ba675SRob Herring clock-names = "fck"; 1826724ba675SRob Herring #address-cells = <1>; 1827724ba675SRob Herring #size-cells = <1>; 1828724ba675SRob Herring ranges = <0x0 0xaa000 0x1000>; 1829724ba675SRob Herring 1830724ba675SRob Herring uart5: serial@0 { 1831724ba675SRob Herring compatible = "ti,am3352-uart", "ti,omap3-uart"; 1832724ba675SRob Herring clock-frequency = <48000000>; 1833724ba675SRob Herring reg = <0x0 0x1000>; 1834724ba675SRob Herring interrupts = <46>; 1835724ba675SRob Herring status = "disabled"; 1836724ba675SRob Herring }; 1837724ba675SRob Herring }; 1838724ba675SRob Herring 1839724ba675SRob Herring target-module@ac000 { /* 0x481ac000, ap 54 38.0 */ 1840724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1841724ba675SRob Herring reg = <0xac000 0x4>, 1842724ba675SRob Herring <0xac010 0x4>, 1843724ba675SRob Herring <0xac114 0x4>; 1844724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1845724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1846724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1847724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1848724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1849724ba675SRob Herring <SYSC_IDLE_NO>, 1850724ba675SRob Herring <SYSC_IDLE_SMART>, 1851724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1852724ba675SRob Herring ti,syss-mask = <1>; 1853724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1854724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>, 1855724ba675SRob Herring <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>; 1856724ba675SRob Herring clock-names = "fck", "dbclk"; 1857724ba675SRob Herring #address-cells = <1>; 1858724ba675SRob Herring #size-cells = <1>; 1859724ba675SRob Herring ranges = <0x0 0xac000 0x1000>; 1860724ba675SRob Herring 1861724ba675SRob Herring gpio2: gpio@0 { 1862724ba675SRob Herring compatible = "ti,omap4-gpio"; 1863724ba675SRob Herring gpio-ranges = <&am33xx_pinmux 0 34 18>, 1864724ba675SRob Herring <&am33xx_pinmux 18 77 4>, 1865724ba675SRob Herring <&am33xx_pinmux 22 56 10>; 1866724ba675SRob Herring gpio-controller; 1867724ba675SRob Herring #gpio-cells = <2>; 1868724ba675SRob Herring interrupt-controller; 1869724ba675SRob Herring #interrupt-cells = <2>; 1870724ba675SRob Herring reg = <0x0 0x1000>; 1871724ba675SRob Herring interrupts = <32>; 1872724ba675SRob Herring }; 1873724ba675SRob Herring }; 1874724ba675SRob Herring 1875724ba675SRob Herring gpio3_target: target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ 1876724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1877724ba675SRob Herring reg = <0xae000 0x4>, 1878724ba675SRob Herring <0xae010 0x4>, 1879724ba675SRob Herring <0xae114 0x4>; 1880724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1881724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1882724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1883724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1884724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1885724ba675SRob Herring <SYSC_IDLE_NO>, 1886724ba675SRob Herring <SYSC_IDLE_SMART>, 1887724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 1888724ba675SRob Herring ti,syss-mask = <1>; 1889724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1890724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>, 1891724ba675SRob Herring <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>; 1892724ba675SRob Herring clock-names = "fck", "dbclk"; 1893724ba675SRob Herring #address-cells = <1>; 1894724ba675SRob Herring #size-cells = <1>; 1895724ba675SRob Herring ranges = <0x0 0xae000 0x1000>; 1896724ba675SRob Herring 1897724ba675SRob Herring gpio3: gpio@0 { 1898724ba675SRob Herring compatible = "ti,omap4-gpio"; 1899724ba675SRob Herring gpio-ranges = <&am33xx_pinmux 0 66 5>, 1900724ba675SRob Herring <&am33xx_pinmux 5 98 2>, 1901724ba675SRob Herring <&am33xx_pinmux 7 75 2>, 1902724ba675SRob Herring <&am33xx_pinmux 13 141 1>, 1903724ba675SRob Herring <&am33xx_pinmux 14 100 8>; 1904724ba675SRob Herring gpio-controller; 1905724ba675SRob Herring #gpio-cells = <2>; 1906724ba675SRob Herring interrupt-controller; 1907724ba675SRob Herring #interrupt-cells = <2>; 1908724ba675SRob Herring reg = <0x0 0x1000>; 1909724ba675SRob Herring interrupts = <62>; 1910724ba675SRob Herring }; 1911724ba675SRob Herring }; 1912724ba675SRob Herring 1913724ba675SRob Herring target-module@b0000 { /* 0x481b0000, ap 58 50.0 */ 1914724ba675SRob Herring compatible = "ti,sysc"; 1915724ba675SRob Herring status = "disabled"; 1916724ba675SRob Herring #address-cells = <1>; 1917724ba675SRob Herring #size-cells = <1>; 1918724ba675SRob Herring ranges = <0x0 0xb0000 0x10000>; 1919724ba675SRob Herring }; 1920724ba675SRob Herring 1921724ba675SRob Herring target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ 1922724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1923724ba675SRob Herring reg = <0xcc020 0x4>; 1924724ba675SRob Herring reg-names = "rev"; 1925724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1926724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>, 1927724ba675SRob Herring <&dcan0_fck>; 1928724ba675SRob Herring clock-names = "fck", "osc"; 1929724ba675SRob Herring #address-cells = <1>; 1930724ba675SRob Herring #size-cells = <1>; 1931724ba675SRob Herring ranges = <0x0 0xcc000 0x2000>; 1932724ba675SRob Herring 1933724ba675SRob Herring dcan0: can@0 { 1934724ba675SRob Herring compatible = "ti,am3352-d_can"; 1935724ba675SRob Herring reg = <0x0 0x2000>; 1936724ba675SRob Herring clocks = <&dcan0_fck>; 1937724ba675SRob Herring clock-names = "fck"; 1938724ba675SRob Herring syscon-raminit = <&scm_conf 0x644 0>; 1939724ba675SRob Herring interrupts = <52>; 1940724ba675SRob Herring status = "disabled"; 1941724ba675SRob Herring }; 1942724ba675SRob Herring }; 1943724ba675SRob Herring 1944724ba675SRob Herring target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ 1945724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 1946724ba675SRob Herring reg = <0xd0020 0x4>; 1947724ba675SRob Herring reg-names = "rev"; 1948724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1949724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>, 1950724ba675SRob Herring <&dcan1_fck>; 1951724ba675SRob Herring clock-names = "fck", "osc"; 1952724ba675SRob Herring #address-cells = <1>; 1953724ba675SRob Herring #size-cells = <1>; 1954724ba675SRob Herring ranges = <0x0 0xd0000 0x2000>; 1955724ba675SRob Herring 1956724ba675SRob Herring dcan1: can@0 { 1957724ba675SRob Herring compatible = "ti,am3352-d_can"; 1958724ba675SRob Herring reg = <0x0 0x2000>; 1959724ba675SRob Herring clocks = <&dcan1_fck>; 1960724ba675SRob Herring clock-names = "fck"; 1961724ba675SRob Herring syscon-raminit = <&scm_conf 0x644 1>; 1962724ba675SRob Herring interrupts = <55>; 1963724ba675SRob Herring status = "disabled"; 1964724ba675SRob Herring }; 1965724ba675SRob Herring }; 1966724ba675SRob Herring 1967724ba675SRob Herring target-module@d8000 { /* 0x481d8000, ap 64 66.0 */ 1968724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 1969724ba675SRob Herring reg = <0xd82fc 0x4>, 1970724ba675SRob Herring <0xd8110 0x4>, 1971724ba675SRob Herring <0xd8114 0x4>; 1972724ba675SRob Herring reg-names = "rev", "sysc", "syss"; 1973724ba675SRob Herring ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1974724ba675SRob Herring SYSC_OMAP2_ENAWAKEUP | 1975724ba675SRob Herring SYSC_OMAP2_SOFTRESET | 1976724ba675SRob Herring SYSC_OMAP2_AUTOIDLE)>; 1977724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1978724ba675SRob Herring <SYSC_IDLE_NO>, 1979724ba675SRob Herring <SYSC_IDLE_SMART>; 1980724ba675SRob Herring ti,syss-mask = <1>; 1981724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1982724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>; 1983724ba675SRob Herring clock-names = "fck"; 1984724ba675SRob Herring #address-cells = <1>; 1985724ba675SRob Herring #size-cells = <1>; 1986724ba675SRob Herring ranges = <0x0 0xd8000 0x1000>; 1987724ba675SRob Herring 1988724ba675SRob Herring mmc2: mmc@0 { 1989724ba675SRob Herring compatible = "ti,am335-sdhci"; 1990724ba675SRob Herring ti,needs-special-reset; 1991724ba675SRob Herring dmas = <&edma 2 0 1992724ba675SRob Herring &edma 3 0>; 1993724ba675SRob Herring dma-names = "tx", "rx"; 1994724ba675SRob Herring interrupts = <28>; 1995724ba675SRob Herring reg = <0x0 0x1000>; 1996724ba675SRob Herring status = "disabled"; 1997724ba675SRob Herring }; 1998724ba675SRob Herring }; 1999724ba675SRob Herring }; 2000724ba675SRob Herring 2001724ba675SRob Herring segment@200000 { /* 0x48200000 */ 2002724ba675SRob Herring compatible = "simple-pm-bus"; 2003724ba675SRob Herring #address-cells = <1>; 2004724ba675SRob Herring #size-cells = <1>; 2005724ba675SRob Herring ranges = <0x00000000 0x00200000 0x010000>; 2006724ba675SRob Herring 2007724ba675SRob Herring target-module@0 { 2008724ba675SRob Herring compatible = "ti,sysc-omap4-simple", "ti,sysc"; 2009724ba675SRob Herring power-domains = <&prm_mpu>; 2010724ba675SRob Herring clocks = <&mpu_clkctrl AM3_MPU_MPU_CLKCTRL 0>; 2011724ba675SRob Herring clock-names = "fck"; 2012724ba675SRob Herring ti,no-idle; 2013724ba675SRob Herring #address-cells = <1>; 2014724ba675SRob Herring #size-cells = <1>; 2015724ba675SRob Herring ranges = <0 0 0x10000>; 2016724ba675SRob Herring 2017724ba675SRob Herring mpu@0 { 2018724ba675SRob Herring compatible = "ti,omap3-mpu"; 2019724ba675SRob Herring pm-sram = <&pm_sram_code 2020724ba675SRob Herring &pm_sram_data>; 2021724ba675SRob Herring }; 2022724ba675SRob Herring }; 2023724ba675SRob Herring }; 2024724ba675SRob Herring 2025724ba675SRob Herring segment@300000 { /* 0x48300000 */ 2026724ba675SRob Herring compatible = "simple-pm-bus"; 2027724ba675SRob Herring #address-cells = <1>; 2028724ba675SRob Herring #size-cells = <1>; 2029724ba675SRob Herring ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */ 2030724ba675SRob Herring <0x00001000 0x00301000 0x001000>, /* ap 67 */ 2031724ba675SRob Herring <0x00002000 0x00302000 0x001000>, /* ap 68 */ 2032724ba675SRob Herring <0x00003000 0x00303000 0x001000>, /* ap 69 */ 2033724ba675SRob Herring <0x00004000 0x00304000 0x001000>, /* ap 70 */ 2034724ba675SRob Herring <0x00005000 0x00305000 0x001000>, /* ap 71 */ 2035724ba675SRob Herring <0x0000e000 0x0030e000 0x001000>, /* ap 72 */ 2036724ba675SRob Herring <0x0000f000 0x0030f000 0x001000>, /* ap 73 */ 2037724ba675SRob Herring <0x00018000 0x00318000 0x004000>, /* ap 74 */ 2038724ba675SRob Herring <0x0001c000 0x0031c000 0x001000>, /* ap 75 */ 2039724ba675SRob Herring <0x00010000 0x00310000 0x002000>, /* ap 76 */ 2040724ba675SRob Herring <0x00012000 0x00312000 0x001000>, /* ap 93 */ 2041724ba675SRob Herring <0x00015000 0x00315000 0x001000>, /* ap 94 */ 2042724ba675SRob Herring <0x00016000 0x00316000 0x001000>, /* ap 95 */ 2043724ba675SRob Herring <0x00017000 0x00317000 0x001000>, /* ap 96 */ 2044724ba675SRob Herring <0x00013000 0x00313000 0x001000>, /* ap 97 */ 2045724ba675SRob Herring <0x00014000 0x00314000 0x001000>, /* ap 98 */ 2046724ba675SRob Herring <0x00020000 0x00320000 0x001000>, /* ap 99 */ 2047724ba675SRob Herring <0x00021000 0x00321000 0x001000>, /* ap 100 */ 2048724ba675SRob Herring <0x00022000 0x00322000 0x001000>, /* ap 101 */ 2049724ba675SRob Herring <0x00023000 0x00323000 0x001000>, /* ap 102 */ 2050724ba675SRob Herring <0x00024000 0x00324000 0x001000>, /* ap 103 */ 2051724ba675SRob Herring <0x00025000 0x00325000 0x001000>; /* ap 104 */ 2052724ba675SRob Herring 2053724ba675SRob Herring target-module@0 { /* 0x48300000, ap 66 48.0 */ 2054724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2055724ba675SRob Herring reg = <0x0 0x4>, 2056724ba675SRob Herring <0x4 0x4>; 2057724ba675SRob Herring reg-names = "rev", "sysc"; 2058724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 2059724ba675SRob Herring <SYSC_IDLE_NO>, 2060724ba675SRob Herring <SYSC_IDLE_SMART>, 2061724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2062724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2063724ba675SRob Herring <SYSC_IDLE_NO>, 2064724ba675SRob Herring <SYSC_IDLE_SMART>, 2065724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2066724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2067724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>; 2068724ba675SRob Herring clock-names = "fck"; 2069724ba675SRob Herring #address-cells = <1>; 2070724ba675SRob Herring #size-cells = <1>; 2071724ba675SRob Herring ranges = <0x0 0x0 0x1000>; 2072724ba675SRob Herring 2073724ba675SRob Herring epwmss0: epwmss@0 { 2074724ba675SRob Herring compatible = "ti,am33xx-pwmss"; 2075724ba675SRob Herring reg = <0x0 0x10>; 2076724ba675SRob Herring #address-cells = <1>; 2077724ba675SRob Herring #size-cells = <1>; 2078724ba675SRob Herring status = "disabled"; 2079724ba675SRob Herring ranges = <0 0 0x1000>; 2080724ba675SRob Herring 2081724ba675SRob Herring ecap0: pwm@100 { 2082724ba675SRob Herring compatible = "ti,am3352-ecap"; 2083724ba675SRob Herring #pwm-cells = <3>; 2084724ba675SRob Herring reg = <0x100 0x80>; 2085724ba675SRob Herring clocks = <&l4ls_gclk>; 2086724ba675SRob Herring clock-names = "fck"; 2087724ba675SRob Herring status = "disabled"; 2088724ba675SRob Herring }; 2089724ba675SRob Herring 2090724ba675SRob Herring eqep0: counter@180 { 2091724ba675SRob Herring compatible = "ti,am3352-eqep"; 2092724ba675SRob Herring reg = <0x180 0x80>; 2093724ba675SRob Herring clocks = <&l4ls_gclk>; 2094724ba675SRob Herring clock-names = "sysclkout"; 2095724ba675SRob Herring interrupts = <79>; 2096724ba675SRob Herring status = "disabled"; 2097724ba675SRob Herring }; 2098724ba675SRob Herring 2099724ba675SRob Herring ehrpwm0: pwm@200 { 2100724ba675SRob Herring compatible = "ti,am3352-ehrpwm"; 2101724ba675SRob Herring #pwm-cells = <3>; 2102724ba675SRob Herring reg = <0x200 0x80>; 2103724ba675SRob Herring clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; 2104724ba675SRob Herring clock-names = "tbclk", "fck"; 2105724ba675SRob Herring status = "disabled"; 2106724ba675SRob Herring }; 2107724ba675SRob Herring }; 2108724ba675SRob Herring }; 2109724ba675SRob Herring 2110724ba675SRob Herring target-module@2000 { /* 0x48302000, ap 68 52.0 */ 2111724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2112724ba675SRob Herring reg = <0x2000 0x4>, 2113724ba675SRob Herring <0x2004 0x4>; 2114724ba675SRob Herring reg-names = "rev", "sysc"; 2115724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 2116724ba675SRob Herring <SYSC_IDLE_NO>, 2117724ba675SRob Herring <SYSC_IDLE_SMART>, 2118724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2119724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2120724ba675SRob Herring <SYSC_IDLE_NO>, 2121724ba675SRob Herring <SYSC_IDLE_SMART>, 2122724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2123724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2124724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>; 2125724ba675SRob Herring clock-names = "fck"; 2126724ba675SRob Herring #address-cells = <1>; 2127724ba675SRob Herring #size-cells = <1>; 2128724ba675SRob Herring ranges = <0x0 0x2000 0x1000>; 2129724ba675SRob Herring 2130724ba675SRob Herring epwmss1: epwmss@0 { 2131724ba675SRob Herring compatible = "ti,am33xx-pwmss"; 2132724ba675SRob Herring reg = <0x0 0x10>; 2133724ba675SRob Herring #address-cells = <1>; 2134724ba675SRob Herring #size-cells = <1>; 2135724ba675SRob Herring status = "disabled"; 2136724ba675SRob Herring ranges = <0 0 0x1000>; 2137724ba675SRob Herring 2138724ba675SRob Herring ecap1: pwm@100 { 2139724ba675SRob Herring compatible = "ti,am3352-ecap"; 2140724ba675SRob Herring #pwm-cells = <3>; 2141724ba675SRob Herring reg = <0x100 0x80>; 2142724ba675SRob Herring clocks = <&l4ls_gclk>; 2143724ba675SRob Herring clock-names = "fck"; 2144724ba675SRob Herring status = "disabled"; 2145724ba675SRob Herring }; 2146724ba675SRob Herring 2147724ba675SRob Herring eqep1: counter@180 { 2148724ba675SRob Herring compatible = "ti,am3352-eqep"; 2149724ba675SRob Herring reg = <0x180 0x80>; 2150724ba675SRob Herring clocks = <&l4ls_gclk>; 2151724ba675SRob Herring clock-names = "sysclkout"; 2152724ba675SRob Herring interrupts = <88>; 2153724ba675SRob Herring status = "disabled"; 2154724ba675SRob Herring }; 2155724ba675SRob Herring 2156724ba675SRob Herring ehrpwm1: pwm@200 { 2157724ba675SRob Herring compatible = "ti,am3352-ehrpwm"; 2158724ba675SRob Herring #pwm-cells = <3>; 2159724ba675SRob Herring reg = <0x200 0x80>; 2160724ba675SRob Herring clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; 2161724ba675SRob Herring clock-names = "tbclk", "fck"; 2162724ba675SRob Herring status = "disabled"; 2163724ba675SRob Herring }; 2164724ba675SRob Herring }; 2165724ba675SRob Herring }; 2166724ba675SRob Herring 2167724ba675SRob Herring target-module@4000 { /* 0x48304000, ap 70 44.0 */ 2168724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2169724ba675SRob Herring reg = <0x4000 0x4>, 2170724ba675SRob Herring <0x4004 0x4>; 2171724ba675SRob Herring reg-names = "rev", "sysc"; 2172724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 2173724ba675SRob Herring <SYSC_IDLE_NO>, 2174724ba675SRob Herring <SYSC_IDLE_SMART>, 2175724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2176724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2177724ba675SRob Herring <SYSC_IDLE_NO>, 2178724ba675SRob Herring <SYSC_IDLE_SMART>, 2179724ba675SRob Herring <SYSC_IDLE_SMART_WKUP>; 2180724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2181724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>; 2182724ba675SRob Herring clock-names = "fck"; 2183724ba675SRob Herring #address-cells = <1>; 2184724ba675SRob Herring #size-cells = <1>; 2185724ba675SRob Herring ranges = <0x0 0x4000 0x1000>; 2186724ba675SRob Herring 2187724ba675SRob Herring epwmss2: epwmss@0 { 2188724ba675SRob Herring compatible = "ti,am33xx-pwmss"; 2189724ba675SRob Herring reg = <0x0 0x10>; 2190724ba675SRob Herring #address-cells = <1>; 2191724ba675SRob Herring #size-cells = <1>; 2192724ba675SRob Herring status = "disabled"; 2193724ba675SRob Herring ranges = <0 0 0x1000>; 2194724ba675SRob Herring 2195724ba675SRob Herring ecap2: pwm@100 { 2196724ba675SRob Herring compatible = "ti,am3352-ecap"; 2197724ba675SRob Herring #pwm-cells = <3>; 2198724ba675SRob Herring reg = <0x100 0x80>; 2199724ba675SRob Herring clocks = <&l4ls_gclk>; 2200724ba675SRob Herring clock-names = "fck"; 2201724ba675SRob Herring status = "disabled"; 2202724ba675SRob Herring }; 2203724ba675SRob Herring 2204724ba675SRob Herring eqep2: counter@180 { 2205724ba675SRob Herring compatible = "ti,am3352-eqep"; 2206724ba675SRob Herring reg = <0x180 0x80>; 2207724ba675SRob Herring clocks = <&l4ls_gclk>; 2208724ba675SRob Herring clock-names = "sysclkout"; 2209724ba675SRob Herring interrupts = <89>; 2210724ba675SRob Herring status = "disabled"; 2211724ba675SRob Herring }; 2212724ba675SRob Herring 2213724ba675SRob Herring ehrpwm2: pwm@200 { 2214724ba675SRob Herring compatible = "ti,am3352-ehrpwm"; 2215724ba675SRob Herring #pwm-cells = <3>; 2216724ba675SRob Herring reg = <0x200 0x80>; 2217724ba675SRob Herring clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; 2218724ba675SRob Herring clock-names = "tbclk", "fck"; 2219724ba675SRob Herring status = "disabled"; 2220724ba675SRob Herring }; 2221724ba675SRob Herring }; 2222724ba675SRob Herring }; 2223724ba675SRob Herring 2224724ba675SRob Herring target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ 2225724ba675SRob Herring compatible = "ti,sysc-omap4", "ti,sysc"; 2226724ba675SRob Herring reg = <0xe000 0x4>, 2227724ba675SRob Herring <0xe054 0x4>; 2228724ba675SRob Herring reg-names = "rev", "sysc"; 2229724ba675SRob Herring ti,sysc-midle = <SYSC_IDLE_FORCE>, 2230724ba675SRob Herring <SYSC_IDLE_NO>, 2231724ba675SRob Herring <SYSC_IDLE_SMART>; 2232724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2233724ba675SRob Herring <SYSC_IDLE_NO>, 2234724ba675SRob Herring <SYSC_IDLE_SMART>; 2235724ba675SRob Herring /* Domains (P, C): per_pwrdm, lcdc_clkdm */ 2236724ba675SRob Herring clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>; 2237724ba675SRob Herring clock-names = "fck"; 2238724ba675SRob Herring #address-cells = <1>; 2239724ba675SRob Herring #size-cells = <1>; 2240724ba675SRob Herring ranges = <0x0 0xe000 0x1000>; 2241724ba675SRob Herring 2242724ba675SRob Herring lcdc: lcdc@0 { 2243724ba675SRob Herring compatible = "ti,am33xx-tilcdc"; 2244724ba675SRob Herring reg = <0x0 0x1000>; 2245724ba675SRob Herring interrupts = <36>; 2246724ba675SRob Herring status = "disabled"; 2247724ba675SRob Herring }; 2248724ba675SRob Herring }; 2249724ba675SRob Herring 2250724ba675SRob Herring target-module@10000 { /* 0x48310000, ap 76 4e.1 */ 2251724ba675SRob Herring compatible = "ti,sysc-omap2", "ti,sysc"; 2252724ba675SRob Herring reg = <0x11fe0 0x4>, 2253724ba675SRob Herring <0x11fe4 0x4>; 2254724ba675SRob Herring reg-names = "rev", "sysc"; 2255724ba675SRob Herring ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>; 2256724ba675SRob Herring ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2257724ba675SRob Herring <SYSC_IDLE_NO>; 2258724ba675SRob Herring /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2259724ba675SRob Herring clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>; 2260724ba675SRob Herring clock-names = "fck"; 2261724ba675SRob Herring #address-cells = <1>; 2262724ba675SRob Herring #size-cells = <1>; 2263724ba675SRob Herring ranges = <0x0 0x10000 0x2000>; 2264724ba675SRob Herring 2265724ba675SRob Herring rng: rng@0 { 2266724ba675SRob Herring compatible = "ti,omap4-rng"; 2267724ba675SRob Herring reg = <0x0 0x2000>; 2268724ba675SRob Herring interrupts = <111>; 2269724ba675SRob Herring }; 2270724ba675SRob Herring }; 2271724ba675SRob Herring 2272724ba675SRob Herring target-module@13000 { /* 0x48313000, ap 97 62.0 */ 2273724ba675SRob Herring compatible = "ti,sysc"; 2274724ba675SRob Herring status = "disabled"; 2275724ba675SRob Herring #address-cells = <1>; 2276724ba675SRob Herring #size-cells = <1>; 2277724ba675SRob Herring ranges = <0x0 0x13000 0x1000>; 2278724ba675SRob Herring }; 2279724ba675SRob Herring 2280724ba675SRob Herring target-module@15000 { /* 0x48315000, ap 94 56.0 */ 2281724ba675SRob Herring compatible = "ti,sysc"; 2282724ba675SRob Herring status = "disabled"; 2283724ba675SRob Herring #address-cells = <1>; 2284724ba675SRob Herring #size-cells = <1>; 2285724ba675SRob Herring ranges = <0x00000000 0x00015000 0x00001000>, 2286724ba675SRob Herring <0x00001000 0x00016000 0x00001000>; 2287724ba675SRob Herring }; 2288724ba675SRob Herring 2289724ba675SRob Herring target-module@18000 { /* 0x48318000, ap 74 4c.0 */ 2290724ba675SRob Herring compatible = "ti,sysc"; 2291724ba675SRob Herring status = "disabled"; 2292724ba675SRob Herring #address-cells = <1>; 2293724ba675SRob Herring #size-cells = <1>; 2294724ba675SRob Herring ranges = <0x0 0x18000 0x4000>; 2295724ba675SRob Herring }; 2296724ba675SRob Herring 2297724ba675SRob Herring target-module@20000 { /* 0x48320000, ap 99 34.0 */ 2298724ba675SRob Herring compatible = "ti,sysc"; 2299724ba675SRob Herring status = "disabled"; 2300724ba675SRob Herring #address-cells = <1>; 2301724ba675SRob Herring #size-cells = <1>; 2302724ba675SRob Herring ranges = <0x0 0x20000 0x1000>; 2303724ba675SRob Herring }; 2304724ba675SRob Herring 2305724ba675SRob Herring target-module@22000 { /* 0x48322000, ap 101 3e.0 */ 2306724ba675SRob Herring compatible = "ti,sysc"; 2307724ba675SRob Herring status = "disabled"; 2308724ba675SRob Herring #address-cells = <1>; 2309724ba675SRob Herring #size-cells = <1>; 2310724ba675SRob Herring ranges = <0x0 0x22000 0x1000>; 2311724ba675SRob Herring }; 2312724ba675SRob Herring 2313724ba675SRob Herring target-module@24000 { /* 0x48324000, ap 103 68.0 */ 2314724ba675SRob Herring compatible = "ti,sysc"; 2315724ba675SRob Herring status = "disabled"; 2316724ba675SRob Herring #address-cells = <1>; 2317724ba675SRob Herring #size-cells = <1>; 2318724ba675SRob Herring ranges = <0x0 0x24000 0x1000>; 2319724ba675SRob Herring }; 2320724ba675SRob Herring }; 2321724ba675SRob Herring}; 2322724ba675SRob Herring 2323