1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/ 4*724ba675SRob Herring * 5*724ba675SRob Herring * Authors: SZ Lin (林上智) <sz.lin@moxa.com> 6*724ba675SRob Herring * Wes Huang (黃淵河) <wes.huang@moxa.com> 7*724ba675SRob Herring * Fero JD Zhou (周俊達) <FeroJD.Zhou@moxa.com> 8*724ba675SRob Herring */ 9*724ba675SRob Herring 10*724ba675SRob Herring/dts-v1/; 11*724ba675SRob Herring 12*724ba675SRob Herring#include "am335x-moxa-uc-2100-common.dtsi" 13*724ba675SRob Herring 14*724ba675SRob Herring/ { 15*724ba675SRob Herring model = "Moxa UC-2101"; 16*724ba675SRob Herring compatible = "moxa,uc-2101", "ti,am33xx"; 17*724ba675SRob Herring 18*724ba675SRob Herring leds { 19*724ba675SRob Herring compatible = "gpio-leds"; 20*724ba675SRob Herring led1 { 21*724ba675SRob Herring label = "UC2100:GREEN:USER"; 22*724ba675SRob Herring gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; 23*724ba675SRob Herring default-state = "off"; 24*724ba675SRob Herring }; 25*724ba675SRob Herring }; 26*724ba675SRob Herring}; 27*724ba675SRob Herring 28*724ba675SRob Herring&am33xx_pinmux { 29*724ba675SRob Herring pinctrl-names = "default"; 30*724ba675SRob Herring 31*724ba675SRob Herring cpsw_default: cpsw-default-pins { 32*724ba675SRob Herring pinctrl-single,pins = < 33*724ba675SRob Herring /* Slave 1 */ 34*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ 35*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ 36*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ 37*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ 38*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ 39*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ 40*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ 41*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) 42*724ba675SRob Herring >; 43*724ba675SRob Herring }; 44*724ba675SRob Herring 45*724ba675SRob Herring spi1_pins: spi1-pins { 46*724ba675SRob Herring pinctrl-single,pins = < 47*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* ecap0_in_pwm0_out.spi1_sclk */ 48*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart1_ctsn.spi1_cs0 */ 49*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_ctsn.spi1_d0 */ 50*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_rtsn.spi1_d1 */ 51*724ba675SRob Herring >; 52*724ba675SRob Herring }; 53*724ba675SRob Herring}; 54*724ba675SRob Herring 55*724ba675SRob Herring&davinci_mdio_sw { 56*724ba675SRob Herring phy0: ethernet-phy@4 { 57*724ba675SRob Herring reg = <4>; 58*724ba675SRob Herring }; 59*724ba675SRob Herring}; 60*724ba675SRob Herring 61*724ba675SRob Herring&cpsw_port1 { 62*724ba675SRob Herring phy-handle = <&phy0>; 63*724ba675SRob Herring phy-mode = "rmii"; 64*724ba675SRob Herring}; 65*724ba675SRob Herring 66*724ba675SRob Herring&cpsw_port2 { 67*724ba675SRob Herring status = "disabled"; 68*724ba675SRob Herring}; 69