1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring/* 7*724ba675SRob Herring * VScom OnRISC 8*724ba675SRob Herring * http://www.vscom.de 9*724ba675SRob Herring */ 10*724ba675SRob Herring 11*724ba675SRob Herring#include "am33xx.dtsi" 12*724ba675SRob Herring#include <dt-bindings/pwm/pwm.h> 13*724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 14*724ba675SRob Herring 15*724ba675SRob Herring/ { 16*724ba675SRob Herring compatible = "vscom,onrisc", "ti,am33xx"; 17*724ba675SRob Herring 18*724ba675SRob Herring cpus { 19*724ba675SRob Herring cpu@0 { 20*724ba675SRob Herring cpu0-supply = <&vdd1_reg>; 21*724ba675SRob Herring }; 22*724ba675SRob Herring }; 23*724ba675SRob Herring 24*724ba675SRob Herring memory@80000000 { 25*724ba675SRob Herring device_type = "memory"; 26*724ba675SRob Herring reg = <0x80000000 0x10000000>; /* 256 MB */ 27*724ba675SRob Herring }; 28*724ba675SRob Herring 29*724ba675SRob Herring vbat: fixedregulator0 { 30*724ba675SRob Herring compatible = "regulator-fixed"; 31*724ba675SRob Herring regulator-name = "vbat"; 32*724ba675SRob Herring regulator-min-microvolt = <5000000>; 33*724ba675SRob Herring regulator-max-microvolt = <5000000>; 34*724ba675SRob Herring regulator-boot-on; 35*724ba675SRob Herring }; 36*724ba675SRob Herring 37*724ba675SRob Herring wl12xx_vmmc: fixedregulator2 { 38*724ba675SRob Herring pinctrl-names = "default"; 39*724ba675SRob Herring pinctrl-0 = <&wl12xx_gpio>; 40*724ba675SRob Herring compatible = "regulator-fixed"; 41*724ba675SRob Herring regulator-name = "vwl1271"; 42*724ba675SRob Herring regulator-min-microvolt = <3300000>; 43*724ba675SRob Herring regulator-max-microvolt = <3300000>; 44*724ba675SRob Herring gpio = <&gpio3 8 0>; 45*724ba675SRob Herring startup-delay-us = <70000>; 46*724ba675SRob Herring enable-active-high; 47*724ba675SRob Herring }; 48*724ba675SRob Herring}; 49*724ba675SRob Herring 50*724ba675SRob Herring&am33xx_pinmux { 51*724ba675SRob Herring mmc2_pins: mmc2-pins { 52*724ba675SRob Herring pinctrl-single,pins = < 53*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ 54*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ 55*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */ 56*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */ 57*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */ 58*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */ 59*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLUP, MUX_MODE7) /* emu0.gpio3[7] */ 60*724ba675SRob Herring >; 61*724ba675SRob Herring }; 62*724ba675SRob Herring 63*724ba675SRob Herring wl12xx_gpio: wl12xx-gpio-pins { 64*724ba675SRob Herring pinctrl-single,pins = < 65*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ 66*724ba675SRob Herring >; 67*724ba675SRob Herring }; 68*724ba675SRob Herring 69*724ba675SRob Herring tps65910_pins: tps65910-pins { 70*724ba675SRob Herring pinctrl-single,pins = < 71*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ben1.gpio1[28] */ 72*724ba675SRob Herring >; 73*724ba675SRob Herring }; 74*724ba675SRob Herring 75*724ba675SRob Herring i2c1_pins: i2c1-pins { 76*724ba675SRob Herring pinctrl-single,pins = < 77*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */ 78*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */ 79*724ba675SRob Herring >; 80*724ba675SRob Herring }; 81*724ba675SRob Herring 82*724ba675SRob Herring uart0_pins: uart0-pins { 83*724ba675SRob Herring pinctrl-single,pins = < 84*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 85*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 86*724ba675SRob Herring >; 87*724ba675SRob Herring }; 88*724ba675SRob Herring 89*724ba675SRob Herring cpsw_default: cpsw-default-pins { 90*724ba675SRob Herring pinctrl-single,pins = < 91*724ba675SRob Herring /* Slave 1 */ 92*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ 93*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_tx_en.rmii1_txen */ 94*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ 95*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ 96*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ 97*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ 98*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ 99*724ba675SRob Herring 100*724ba675SRob Herring 101*724ba675SRob Herring /* Slave 2 */ 102*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ 103*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ 104*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ 105*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ 106*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ 107*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ 108*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ 109*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ 110*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ 111*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ 112*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ 113*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ 114*724ba675SRob Herring >; 115*724ba675SRob Herring }; 116*724ba675SRob Herring 117*724ba675SRob Herring cpsw_sleep: cpsw-sleep-pins { 118*724ba675SRob Herring pinctrl-single,pins = < 119*724ba675SRob Herring /* Slave 1 reset value */ 120*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) 121*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) 122*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 123*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 124*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 125*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 126*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 127*724ba675SRob Herring 128*724ba675SRob Herring /* Slave 2 reset value*/ 129*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) 130*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) 131*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) 132*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) 133*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) 134*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) 135*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) 136*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) 137*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) 138*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) 139*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) 140*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) 141*724ba675SRob Herring >; 142*724ba675SRob Herring }; 143*724ba675SRob Herring 144*724ba675SRob Herring davinci_mdio_default: davinci-mdio-default-pins { 145*724ba675SRob Herring pinctrl-single,pins = < 146*724ba675SRob Herring /* MDIO */ 147*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data.mdio_data */ 148*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk.mdio_clk */ 149*724ba675SRob Herring >; 150*724ba675SRob Herring }; 151*724ba675SRob Herring 152*724ba675SRob Herring davinci_mdio_sleep: davinci-mdio-sleep-pins { 153*724ba675SRob Herring pinctrl-single,pins = < 154*724ba675SRob Herring /* MDIO reset value */ 155*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) 156*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) 157*724ba675SRob Herring >; 158*724ba675SRob Herring }; 159*724ba675SRob Herring 160*724ba675SRob Herring nandflash_pins_s0: nandflash-s0-pins { 161*724ba675SRob Herring pinctrl-single,pins = < 162*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 163*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 164*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 165*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 166*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 167*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 168*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 169*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 170*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 171*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ 172*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 173*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 174*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 175*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen.gpmc_wen */ 176*724ba675SRob Herring AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 177*724ba675SRob Herring >; 178*724ba675SRob Herring }; 179*724ba675SRob Herring}; 180*724ba675SRob Herring 181*724ba675SRob Herring&elm { 182*724ba675SRob Herring status = "okay"; 183*724ba675SRob Herring}; 184*724ba675SRob Herring 185*724ba675SRob Herring&gpmc { 186*724ba675SRob Herring pinctrl-names = "default"; 187*724ba675SRob Herring pinctrl-0 = <&nandflash_pins_s0>; 188*724ba675SRob Herring ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 189*724ba675SRob Herring status = "okay"; 190*724ba675SRob Herring 191*724ba675SRob Herring nand@0,0 { 192*724ba675SRob Herring compatible = "ti,omap2-nand"; 193*724ba675SRob Herring reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 194*724ba675SRob Herring interrupt-parent = <&gpmc>; 195*724ba675SRob Herring interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 196*724ba675SRob Herring <1 IRQ_TYPE_NONE>; /* termcount */ 197*724ba675SRob Herring rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ 198*724ba675SRob Herring nand-bus-width = <8>; 199*724ba675SRob Herring ti,nand-ecc-opt = "bch8"; 200*724ba675SRob Herring ti,nand-xfer-type = "prefetch-dma"; 201*724ba675SRob Herring 202*724ba675SRob Herring gpmc,device-nand = "true"; 203*724ba675SRob Herring gpmc,device-width = <1>; 204*724ba675SRob Herring gpmc,sync-clk-ps = <0>; 205*724ba675SRob Herring gpmc,cs-on-ns = <0>; 206*724ba675SRob Herring gpmc,cs-rd-off-ns = <44>; 207*724ba675SRob Herring gpmc,cs-wr-off-ns = <44>; 208*724ba675SRob Herring gpmc,adv-on-ns = <6>; 209*724ba675SRob Herring gpmc,adv-rd-off-ns = <34>; 210*724ba675SRob Herring gpmc,adv-wr-off-ns = <44>; 211*724ba675SRob Herring gpmc,we-on-ns = <0>; 212*724ba675SRob Herring gpmc,we-off-ns = <40>; 213*724ba675SRob Herring gpmc,oe-on-ns = <0>; 214*724ba675SRob Herring gpmc,oe-off-ns = <54>; 215*724ba675SRob Herring gpmc,access-ns = <64>; 216*724ba675SRob Herring gpmc,rd-cycle-ns = <82>; 217*724ba675SRob Herring gpmc,wr-cycle-ns = <82>; 218*724ba675SRob Herring gpmc,bus-turnaround-ns = <0>; 219*724ba675SRob Herring gpmc,cycle2cycle-delay-ns = <0>; 220*724ba675SRob Herring gpmc,clk-activation-ns = <0>; 221*724ba675SRob Herring gpmc,wr-access-ns = <40>; 222*724ba675SRob Herring gpmc,wr-data-mux-bus-ns = <0>; 223*724ba675SRob Herring 224*724ba675SRob Herring #address-cells = <1>; 225*724ba675SRob Herring #size-cells = <1>; 226*724ba675SRob Herring ti,elm-id = <&elm>; 227*724ba675SRob Herring }; 228*724ba675SRob Herring}; 229*724ba675SRob Herring 230*724ba675SRob Herring&uart0 { 231*724ba675SRob Herring pinctrl-names = "default"; 232*724ba675SRob Herring pinctrl-0 = <&uart0_pins>; 233*724ba675SRob Herring 234*724ba675SRob Herring status = "okay"; 235*724ba675SRob Herring}; 236*724ba675SRob Herring 237*724ba675SRob Herring&i2c1 { 238*724ba675SRob Herring pinctrl-names = "default"; 239*724ba675SRob Herring pinctrl-0 = <&i2c1_pins>; 240*724ba675SRob Herring 241*724ba675SRob Herring status = "okay"; 242*724ba675SRob Herring clock-frequency = <400000>; 243*724ba675SRob Herring 244*724ba675SRob Herring tps: tps@2d { 245*724ba675SRob Herring reg = <0x2d>; 246*724ba675SRob Herring gpio-controller; 247*724ba675SRob Herring #gpio-cells = <2>; 248*724ba675SRob Herring interrupt-parent = <&gpio1>; 249*724ba675SRob Herring interrupts = <28 IRQ_TYPE_EDGE_RISING>; 250*724ba675SRob Herring pinctrl-names = "default"; 251*724ba675SRob Herring pinctrl-0 = <&tps65910_pins>; 252*724ba675SRob Herring }; 253*724ba675SRob Herring 254*724ba675SRob Herring at24@50 { 255*724ba675SRob Herring compatible = "atmel,24c02"; 256*724ba675SRob Herring pagesize = <8>; 257*724ba675SRob Herring reg = <0x50>; 258*724ba675SRob Herring }; 259*724ba675SRob Herring}; 260*724ba675SRob Herring 261*724ba675SRob Herring#include "../../tps65910.dtsi" 262*724ba675SRob Herring 263*724ba675SRob Herring&tps { 264*724ba675SRob Herring vcc1-supply = <&vbat>; 265*724ba675SRob Herring vcc2-supply = <&vbat>; 266*724ba675SRob Herring vcc3-supply = <&vbat>; 267*724ba675SRob Herring vcc4-supply = <&vbat>; 268*724ba675SRob Herring vcc5-supply = <&vbat>; 269*724ba675SRob Herring vcc6-supply = <&vbat>; 270*724ba675SRob Herring vcc7-supply = <&vbat>; 271*724ba675SRob Herring vccio-supply = <&vbat>; 272*724ba675SRob Herring 273*724ba675SRob Herring ti,en-ck32k-xtal = <1>; 274*724ba675SRob Herring 275*724ba675SRob Herring regulators { 276*724ba675SRob Herring vrtc_reg: regulator@0 { 277*724ba675SRob Herring regulator-always-on; 278*724ba675SRob Herring }; 279*724ba675SRob Herring 280*724ba675SRob Herring vio_reg: regulator@1 { 281*724ba675SRob Herring regulator-always-on; 282*724ba675SRob Herring }; 283*724ba675SRob Herring 284*724ba675SRob Herring vdd1_reg: regulator@2 { 285*724ba675SRob Herring /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 286*724ba675SRob Herring regulator-name = "vdd_mpu"; 287*724ba675SRob Herring regulator-min-microvolt = <912500>; 288*724ba675SRob Herring regulator-max-microvolt = <1351500>; 289*724ba675SRob Herring regulator-boot-on; 290*724ba675SRob Herring regulator-always-on; 291*724ba675SRob Herring }; 292*724ba675SRob Herring 293*724ba675SRob Herring vdd2_reg: regulator@3 { 294*724ba675SRob Herring /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 295*724ba675SRob Herring regulator-name = "vdd_core"; 296*724ba675SRob Herring regulator-min-microvolt = <912500>; 297*724ba675SRob Herring regulator-max-microvolt = <1150000>; 298*724ba675SRob Herring regulator-boot-on; 299*724ba675SRob Herring regulator-always-on; 300*724ba675SRob Herring }; 301*724ba675SRob Herring 302*724ba675SRob Herring vdd3_reg: regulator@4 { 303*724ba675SRob Herring regulator-always-on; 304*724ba675SRob Herring }; 305*724ba675SRob Herring 306*724ba675SRob Herring vdig1_reg: regulator@5 { 307*724ba675SRob Herring regulator-always-on; 308*724ba675SRob Herring }; 309*724ba675SRob Herring 310*724ba675SRob Herring vdig2_reg: regulator@6 { 311*724ba675SRob Herring regulator-always-on; 312*724ba675SRob Herring }; 313*724ba675SRob Herring 314*724ba675SRob Herring vpll_reg: regulator@7 { 315*724ba675SRob Herring regulator-always-on; 316*724ba675SRob Herring }; 317*724ba675SRob Herring 318*724ba675SRob Herring vdac_reg: regulator@8 { 319*724ba675SRob Herring regulator-always-on; 320*724ba675SRob Herring }; 321*724ba675SRob Herring 322*724ba675SRob Herring vaux1_reg: regulator@9 { 323*724ba675SRob Herring regulator-always-on; 324*724ba675SRob Herring }; 325*724ba675SRob Herring 326*724ba675SRob Herring vaux2_reg: regulator@10 { 327*724ba675SRob Herring regulator-always-on; 328*724ba675SRob Herring }; 329*724ba675SRob Herring 330*724ba675SRob Herring vaux33_reg: regulator@11 { 331*724ba675SRob Herring regulator-always-on; 332*724ba675SRob Herring }; 333*724ba675SRob Herring 334*724ba675SRob Herring vmmc_reg: regulator@12 { 335*724ba675SRob Herring regulator-min-microvolt = <1800000>; 336*724ba675SRob Herring regulator-max-microvolt = <3300000>; 337*724ba675SRob Herring regulator-always-on; 338*724ba675SRob Herring }; 339*724ba675SRob Herring }; 340*724ba675SRob Herring}; 341*724ba675SRob Herring 342*724ba675SRob Herring&mac_sw { 343*724ba675SRob Herring pinctrl-names = "default", "sleep"; 344*724ba675SRob Herring pinctrl-0 = <&cpsw_default>; 345*724ba675SRob Herring pinctrl-1 = <&cpsw_sleep>; 346*724ba675SRob Herring 347*724ba675SRob Herring status = "okay"; 348*724ba675SRob Herring}; 349*724ba675SRob Herring 350*724ba675SRob Herring&davinci_mdio_sw { 351*724ba675SRob Herring status = "okay"; 352*724ba675SRob Herring pinctrl-names = "default", "sleep"; 353*724ba675SRob Herring pinctrl-0 = <&davinci_mdio_default>; 354*724ba675SRob Herring pinctrl-1 = <&davinci_mdio_sleep>; 355*724ba675SRob Herring 356*724ba675SRob Herring phy1: ethernet-phy@1 { 357*724ba675SRob Herring reg = <7>; 358*724ba675SRob Herring eee-broken-100tx; 359*724ba675SRob Herring eee-broken-1000t; 360*724ba675SRob Herring }; 361*724ba675SRob Herring}; 362*724ba675SRob Herring 363*724ba675SRob Herring&mmc1 { 364*724ba675SRob Herring vmmc-supply = <&vmmc_reg>; 365*724ba675SRob Herring status = "okay"; 366*724ba675SRob Herring}; 367*724ba675SRob Herring 368*724ba675SRob Herring&mmc2 { 369*724ba675SRob Herring status = "okay"; 370*724ba675SRob Herring vmmc-supply = <&wl12xx_vmmc>; 371*724ba675SRob Herring non-removable; 372*724ba675SRob Herring bus-width = <4>; 373*724ba675SRob Herring cap-power-off-card; 374*724ba675SRob Herring pinctrl-names = "default"; 375*724ba675SRob Herring pinctrl-0 = <&mmc2_pins>; 376*724ba675SRob Herring 377*724ba675SRob Herring #address-cells = <1>; 378*724ba675SRob Herring #size-cells = <0>; 379*724ba675SRob Herring wlcore: wlcore@2 { 380*724ba675SRob Herring compatible = "ti,wl1835"; 381*724ba675SRob Herring reg = <2>; 382*724ba675SRob Herring interrupt-parent = <&gpio3>; 383*724ba675SRob Herring interrupts = <7 IRQ_TYPE_EDGE_RISING>; 384*724ba675SRob Herring }; 385*724ba675SRob Herring}; 386*724ba675SRob Herring 387*724ba675SRob Herring&sham { 388*724ba675SRob Herring status = "okay"; 389*724ba675SRob Herring}; 390*724ba675SRob Herring 391*724ba675SRob Herring&aes { 392*724ba675SRob Herring status = "okay"; 393*724ba675SRob Herring}; 394*724ba675SRob Herring 395*724ba675SRob Herring&gpio0_target { 396*724ba675SRob Herring ti,no-reset-on-init; 397*724ba675SRob Herring}; 398*724ba675SRob Herring 399*724ba675SRob Herring&gpio3_target { 400*724ba675SRob Herring ti,no-reset-on-init; 401*724ba675SRob Herring}; 402