1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/pinctrl/stm32-pinfunc.h> 7 8&pinctrl { 9 adc1_in6_pins_a: adc1-in6-0 { 10 pins { 11 pinmux = <STM32_PINMUX('F', 12, ANALOG)>; 12 }; 13 }; 14 15 adc12_ain_pins_a: adc12-ain-0 { 16 pins { 17 pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */ 18 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ 19 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */ 20 <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */ 21 }; 22 }; 23 24 adc12_ain_pins_b: adc12-ain-1 { 25 pins { 26 pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ 27 <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */ 28 }; 29 }; 30 31 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { 32 pins { 33 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */ 34 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */ 35 }; 36 }; 37 38 cec_pins_a: cec-0 { 39 pins { 40 pinmux = <STM32_PINMUX('A', 15, AF4)>; 41 bias-disable; 42 drive-open-drain; 43 slew-rate = <0>; 44 }; 45 }; 46 47 cec_sleep_pins_a: cec-sleep-0 { 48 pins { 49 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */ 50 }; 51 }; 52 53 cec_pins_b: cec-1 { 54 pins { 55 pinmux = <STM32_PINMUX('B', 6, AF5)>; 56 bias-disable; 57 drive-open-drain; 58 slew-rate = <0>; 59 }; 60 }; 61 62 cec_sleep_pins_b: cec-sleep-1 { 63 pins { 64 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */ 65 }; 66 }; 67 68 dac_ch1_pins_a: dac-ch1-0 { 69 pins { 70 pinmux = <STM32_PINMUX('A', 4, ANALOG)>; 71 }; 72 }; 73 74 dac_ch2_pins_a: dac-ch2-0 { 75 pins { 76 pinmux = <STM32_PINMUX('A', 5, ANALOG)>; 77 }; 78 }; 79 80 dcmi_pins_a: dcmi-0 { 81 pins { 82 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ 83 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ 84 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ 85 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */ 86 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ 87 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ 88 <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */ 89 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ 90 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ 91 <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ 92 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ 93 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ 94 <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */ 95 <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */ 96 <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */ 97 bias-disable; 98 }; 99 }; 100 101 dcmi_sleep_pins_a: dcmi-sleep-0 { 102 pins { 103 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ 104 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ 105 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ 106 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */ 107 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ 108 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ 109 <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */ 110 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ 111 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ 112 <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ 113 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ 114 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ 115 <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */ 116 <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */ 117 <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */ 118 }; 119 }; 120 121 dcmi_pins_b: dcmi-1 { 122 pins { 123 pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ 124 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ 125 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ 126 <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */ 127 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ 128 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ 129 <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ 130 <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */ 131 <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */ 132 <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */ 133 <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */ 134 bias-disable; 135 }; 136 }; 137 138 dcmi_sleep_pins_b: dcmi-sleep-1 { 139 pins { 140 pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ 141 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ 142 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ 143 <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */ 144 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ 145 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ 146 <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ 147 <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */ 148 <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */ 149 <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */ 150 <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */ 151 }; 152 }; 153 154 dcmi_pins_c: dcmi-2 { 155 pins { 156 pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ 157 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ 158 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ 159 <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */ 160 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ 161 <STM32_PINMUX('E', 0, AF13)>,/* DCMI_D2 */ 162 <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ 163 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ 164 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ 165 <STM32_PINMUX('I', 6, AF13)>,/* DCMI_D6 */ 166 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ 167 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ 168 <STM32_PINMUX('H', 7, AF13)>;/* DCMI_D9 */ 169 bias-pull-up; 170 }; 171 }; 172 173 dcmi_sleep_pins_c: dcmi-sleep-2 { 174 pins { 175 pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ 176 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ 177 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ 178 <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */ 179 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ 180 <STM32_PINMUX('E', 0, ANALOG)>,/* DCMI_D2 */ 181 <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ 182 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ 183 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ 184 <STM32_PINMUX('I', 6, ANALOG)>,/* DCMI_D6 */ 185 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ 186 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ 187 <STM32_PINMUX('H', 7, ANALOG)>;/* DCMI_D9 */ 188 }; 189 }; 190 191 ethernet0_rgmii_pins_a: rgmii-0 { 192 pins1 { 193 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 194 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 195 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ 196 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 197 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 198 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 199 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 200 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 201 bias-disable; 202 drive-push-pull; 203 slew-rate = <2>; 204 }; 205 pins2 { 206 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 207 bias-disable; 208 drive-push-pull; 209 slew-rate = <0>; 210 }; 211 pins3 { 212 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 213 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 214 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ 215 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ 216 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 217 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 218 bias-disable; 219 }; 220 }; 221 222 ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { 223 pins1 { 224 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 225 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 226 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ 227 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 228 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 229 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 230 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 231 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 232 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 233 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 234 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 235 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */ 236 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ 237 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 238 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 239 }; 240 }; 241 242 ethernet0_rgmii_pins_b: rgmii-1 { 243 pins1 { 244 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 245 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 246 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ 247 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 248 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 249 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 250 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 251 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 252 bias-disable; 253 drive-push-pull; 254 slew-rate = <2>; 255 }; 256 pins2 { 257 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 258 bias-disable; 259 drive-push-pull; 260 slew-rate = <0>; 261 }; 262 pins3 { 263 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 264 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 265 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ 266 <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */ 267 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 268 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 269 bias-disable; 270 }; 271 }; 272 273 ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { 274 pins1 { 275 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 276 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 277 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ 278 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 279 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 280 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 281 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 282 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 283 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 284 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 285 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 286 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ 287 <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */ 288 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 289 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 290 }; 291 }; 292 293 ethernet0_rgmii_pins_c: rgmii-2 { 294 pins1 { 295 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 296 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 297 <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */ 298 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 299 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 300 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 301 <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 302 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 303 bias-disable; 304 drive-push-pull; 305 slew-rate = <2>; 306 }; 307 pins2 { 308 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 309 bias-disable; 310 drive-push-pull; 311 slew-rate = <0>; 312 }; 313 pins3 { 314 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 315 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 316 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ 317 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ 318 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 319 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 320 bias-disable; 321 }; 322 }; 323 324 ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { 325 pins1 { 326 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 327 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 328 <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */ 329 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 330 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 331 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 332 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 333 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 334 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 335 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 336 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 337 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ 338 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ 339 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 340 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 341 }; 342 }; 343 344 ethernet0_rgmii_pins_d: rgmii-3 { 345 pins1 { 346 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 347 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ 348 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 349 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 350 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 351 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 352 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 353 bias-disable; 354 drive-push-pull; 355 slew-rate = <2>; 356 }; 357 pins2 { 358 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 359 bias-disable; 360 drive-push-pull; 361 slew-rate = <0>; 362 }; 363 pins3 { 364 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 365 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 366 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ 367 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ 368 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 369 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 370 bias-disable; 371 }; 372 }; 373 374 ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 { 375 pins1 { 376 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 377 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 378 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ 379 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 380 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 381 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 382 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 383 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 384 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 385 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 386 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 387 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ 388 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ 389 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 390 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 391 }; 392 }; 393 394 ethernet0_rmii_pins_a: rmii-0 { 395 pins1 { 396 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ 397 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ 398 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ 399 <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ 400 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ 401 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ 402 bias-disable; 403 drive-push-pull; 404 slew-rate = <2>; 405 }; 406 pins2 { 407 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ 408 <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ 409 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ 410 bias-disable; 411 }; 412 }; 413 414 ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { 415 pins1 { 416 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ 417 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ 418 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ 419 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ 420 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ 421 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ 422 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ 423 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ 424 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ 425 }; 426 }; 427 428 ethernet0_rmii_pins_b: rmii-1 { 429 pins1 { 430 pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */ 431 <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */ 432 <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */ 433 <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */ 434 bias-disable; 435 drive-push-pull; 436 slew-rate = <1>; 437 }; 438 pins2 { 439 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */ 440 bias-disable; 441 drive-push-pull; 442 slew-rate = <0>; 443 }; 444 pins3 { 445 pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */ 446 <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */ 447 <STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */ 448 bias-disable; 449 }; 450 pins4 { 451 pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */ 452 }; 453 }; 454 455 ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { 456 pins1 { 457 pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ 458 <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */ 459 <STM32_PINMUX('B', 5, ANALOG)>, /* ETH1_CLK */ 460 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */ 461 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ 462 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */ 463 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */ 464 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */ 465 <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */ 466 }; 467 }; 468 469 ethernet0_rmii_pins_c: rmii-2 { 470 pins1 { 471 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ 472 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ 473 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ 474 <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */ 475 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ 476 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ 477 bias-disable; 478 drive-push-pull; 479 slew-rate = <2>; 480 }; 481 pins2 { 482 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ 483 <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ 484 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ 485 bias-disable; 486 }; 487 }; 488 489 ethernet0_rmii_sleep_pins_c: rmii-sleep-2 { 490 pins1 { 491 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ 492 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ 493 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ 494 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ 495 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ 496 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ 497 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ 498 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ 499 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ 500 }; 501 }; 502 503 fmc_pins_a: fmc-0 { 504 pins1 { 505 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ 506 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ 507 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */ 508 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */ 509 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ 510 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ 511 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ 512 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ 513 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ 514 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ 515 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ 516 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ 517 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */ 518 bias-disable; 519 drive-push-pull; 520 slew-rate = <1>; 521 }; 522 pins2 { 523 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */ 524 bias-pull-up; 525 }; 526 }; 527 528 fmc_sleep_pins_a: fmc-sleep-0 { 529 pins { 530 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ 531 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ 532 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */ 533 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */ 534 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ 535 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ 536 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ 537 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ 538 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ 539 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ 540 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ 541 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ 542 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */ 543 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */ 544 }; 545 }; 546 547 fmc_pins_b: fmc-1 { 548 pins { 549 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ 550 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ 551 <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */ 552 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ 553 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ 554 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ 555 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ 556 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ 557 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ 558 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ 559 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ 560 <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */ 561 <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */ 562 <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */ 563 <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */ 564 <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */ 565 <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */ 566 <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */ 567 <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */ 568 <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */ 569 <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */ 570 bias-disable; 571 drive-push-pull; 572 slew-rate = <3>; 573 }; 574 }; 575 576 fmc_sleep_pins_b: fmc-sleep-1 { 577 pins { 578 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ 579 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ 580 <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */ 581 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ 582 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ 583 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ 584 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ 585 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ 586 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ 587 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ 588 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ 589 <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */ 590 <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */ 591 <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */ 592 <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */ 593 <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */ 594 <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */ 595 <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */ 596 <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */ 597 <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */ 598 <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */ 599 }; 600 }; 601 602 i2c1_pins_a: i2c1-0 { 603 pins { 604 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ 605 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ 606 bias-disable; 607 drive-open-drain; 608 slew-rate = <0>; 609 }; 610 }; 611 612 i2c1_sleep_pins_a: i2c1-sleep-0 { 613 pins { 614 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ 615 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ 616 }; 617 }; 618 619 i2c1_pins_b: i2c1-1 { 620 pins { 621 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ 622 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ 623 bias-disable; 624 drive-open-drain; 625 slew-rate = <0>; 626 }; 627 }; 628 629 i2c1_sleep_pins_b: i2c1-sleep-1 { 630 pins { 631 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ 632 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ 633 }; 634 }; 635 636 i2c2_pins_a: i2c2-0 { 637 pins { 638 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ 639 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 640 bias-disable; 641 drive-open-drain; 642 slew-rate = <0>; 643 }; 644 }; 645 646 i2c2_sleep_pins_a: i2c2-sleep-0 { 647 pins { 648 pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */ 649 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 650 }; 651 }; 652 653 i2c2_pins_b1: i2c2-1 { 654 pins { 655 pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 656 bias-disable; 657 drive-open-drain; 658 slew-rate = <0>; 659 }; 660 }; 661 662 i2c2_sleep_pins_b1: i2c2-sleep-1 { 663 pins { 664 pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 665 }; 666 }; 667 668 i2c2_pins_c: i2c2-2 { 669 pins { 670 pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */ 671 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 672 bias-disable; 673 drive-open-drain; 674 slew-rate = <0>; 675 }; 676 }; 677 678 i2c2_pins_sleep_c: i2c2-sleep-2 { 679 pins { 680 pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */ 681 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 682 }; 683 }; 684 685 i2c5_pins_a: i2c5-0 { 686 pins { 687 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */ 688 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */ 689 bias-disable; 690 drive-open-drain; 691 slew-rate = <0>; 692 }; 693 }; 694 695 i2c5_sleep_pins_a: i2c5-sleep-0 { 696 pins { 697 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */ 698 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */ 699 700 }; 701 }; 702 703 i2c5_pins_b: i2c5-1 { 704 pins { 705 pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */ 706 <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */ 707 bias-disable; 708 drive-open-drain; 709 slew-rate = <0>; 710 }; 711 }; 712 713 i2c5_sleep_pins_b: i2c5-sleep-1 { 714 pins { 715 pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */ 716 <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */ 717 }; 718 }; 719 720 i2s2_pins_a: i2s2-0 { 721 pins { 722 pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ 723 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */ 724 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */ 725 slew-rate = <1>; 726 drive-push-pull; 727 bias-disable; 728 }; 729 }; 730 731 i2s2_sleep_pins_a: i2s2-sleep-0 { 732 pins { 733 pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */ 734 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */ 735 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */ 736 }; 737 }; 738 739 ltdc_pins_a: ltdc-0 { 740 pins { 741 pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ 742 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ 743 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ 744 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */ 745 <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */ 746 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ 747 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ 748 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ 749 <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */ 750 <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */ 751 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ 752 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ 753 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ 754 <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */ 755 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ 756 <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */ 757 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ 758 <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */ 759 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */ 760 <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */ 761 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ 762 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ 763 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ 764 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ 765 <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */ 766 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ 767 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ 768 <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */ 769 bias-disable; 770 drive-push-pull; 771 slew-rate = <1>; 772 }; 773 }; 774 775 ltdc_sleep_pins_a: ltdc-sleep-0 { 776 pins { 777 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ 778 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ 779 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ 780 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */ 781 <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */ 782 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ 783 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ 784 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ 785 <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */ 786 <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */ 787 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ 788 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ 789 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ 790 <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */ 791 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ 792 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */ 793 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ 794 <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */ 795 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */ 796 <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */ 797 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ 798 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ 799 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ 800 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ 801 <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */ 802 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ 803 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ 804 <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */ 805 }; 806 }; 807 808 ltdc_pins_b: ltdc-1 { 809 pins { 810 pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ 811 <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ 812 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ 813 <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */ 814 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ 815 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ 816 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ 817 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ 818 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ 819 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ 820 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */ 821 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ 822 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ 823 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ 824 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ 825 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ 826 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ 827 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ 828 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ 829 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ 830 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ 831 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ 832 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ 833 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */ 834 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ 835 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ 836 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ 837 <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */ 838 bias-disable; 839 drive-push-pull; 840 slew-rate = <1>; 841 }; 842 }; 843 844 ltdc_sleep_pins_b: ltdc-sleep-1 { 845 pins { 846 pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */ 847 <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */ 848 <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */ 849 <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */ 850 <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */ 851 <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */ 852 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */ 853 <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */ 854 <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */ 855 <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */ 856 <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */ 857 <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */ 858 <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */ 859 <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */ 860 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */ 861 <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */ 862 <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */ 863 <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */ 864 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */ 865 <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */ 866 <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */ 867 <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */ 868 <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */ 869 <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */ 870 <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */ 871 <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */ 872 <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */ 873 <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */ 874 }; 875 }; 876 877 ltdc_pins_c: ltdc-2 { 878 pins1 { 879 pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */ 880 <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */ 881 <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */ 882 <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */ 883 <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */ 884 <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */ 885 <STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */ 886 <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */ 887 <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */ 888 <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */ 889 <STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */ 890 <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */ 891 <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */ 892 <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */ 893 <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */ 894 <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */ 895 <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */ 896 <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */ 897 <STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */ 898 <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */ 899 <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */ 900 bias-disable; 901 drive-push-pull; 902 slew-rate = <0>; 903 }; 904 pins2 { 905 pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */ 906 bias-disable; 907 drive-push-pull; 908 slew-rate = <1>; 909 }; 910 }; 911 912 ltdc_sleep_pins_c: ltdc-sleep-2 { 913 pins1 { 914 pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */ 915 <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */ 916 <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */ 917 <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */ 918 <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */ 919 <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */ 920 <STM32_PINMUX('E', 11, ANALOG)>, /* LTDC_G3 */ 921 <STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */ 922 <STM32_PINMUX('E', 13, ANALOG)>, /* LTDC_DE */ 923 <STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */ 924 <STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G5 */ 925 <STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */ 926 <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */ 927 <STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */ 928 <STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */ 929 <STM32_PINMUX('H', 15, ANALOG)>, /* LTDC_G4 */ 930 <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */ 931 <STM32_PINMUX('I', 5, ANALOG)>, /* LTDC_B5 */ 932 <STM32_PINMUX('I', 6, ANALOG)>, /* LTDC_B6 */ 933 <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */ 934 <STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */ 935 <STM32_PINMUX('E', 14, ANALOG)>; /* LTDC_CLK */ 936 }; 937 }; 938 939 ltdc_pins_d: ltdc-3 { 940 pins1 { 941 pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */ 942 bias-disable; 943 drive-push-pull; 944 slew-rate = <3>; 945 }; 946 pins2 { 947 pinmux = <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ 948 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ 949 <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */ 950 <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */ 951 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ 952 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ 953 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ 954 <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */ 955 <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */ 956 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ 957 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ 958 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ 959 <STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */ 960 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ 961 <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */ 962 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ 963 <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */ 964 <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */ 965 <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */ 966 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ 967 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ 968 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ 969 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ 970 <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */ 971 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ 972 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ 973 <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */ 974 bias-disable; 975 drive-push-pull; 976 slew-rate = <2>; 977 }; 978 }; 979 980 ltdc_sleep_pins_d: ltdc-sleep-3 { 981 pins { 982 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ 983 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ 984 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ 985 <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */ 986 <STM32_PINMUX('G', 13, ANALOG)>, /* LCD_R0 */ 987 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ 988 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ 989 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ 990 <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */ 991 <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */ 992 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ 993 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ 994 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ 995 <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */ 996 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ 997 <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */ 998 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ 999 <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */ 1000 <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */ 1001 <STM32_PINMUX('G', 8, ANALOG)>, /* LCD_G7 */ 1002 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ 1003 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ 1004 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ 1005 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ 1006 <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */ 1007 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ 1008 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ 1009 <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */ 1010 }; 1011 }; 1012 1013 mco1_pins_a: mco1-0 { 1014 pins { 1015 pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */ 1016 bias-disable; 1017 drive-push-pull; 1018 slew-rate = <1>; 1019 }; 1020 }; 1021 1022 mco1_sleep_pins_a: mco1-sleep-0 { 1023 pins { 1024 pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */ 1025 }; 1026 }; 1027 1028 mco2_pins_a: mco2-0 { 1029 pins { 1030 pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */ 1031 bias-disable; 1032 drive-push-pull; 1033 slew-rate = <2>; 1034 }; 1035 }; 1036 1037 mco2_sleep_pins_a: mco2-sleep-0 { 1038 pins { 1039 pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */ 1040 }; 1041 }; 1042 1043 m_can1_pins_a: m-can1-0 { 1044 pins1 { 1045 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ 1046 slew-rate = <1>; 1047 drive-push-pull; 1048 bias-disable; 1049 }; 1050 pins2 { 1051 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */ 1052 bias-disable; 1053 }; 1054 }; 1055 1056 m_can1_sleep_pins_a: m_can1-sleep-0 { 1057 pins { 1058 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ 1059 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */ 1060 }; 1061 }; 1062 1063 m_can1_pins_b: m-can1-1 { 1064 pins1 { 1065 pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */ 1066 slew-rate = <1>; 1067 drive-push-pull; 1068 bias-disable; 1069 }; 1070 pins2 { 1071 pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */ 1072 bias-disable; 1073 }; 1074 }; 1075 1076 m_can1_sleep_pins_b: m_can1-sleep-1 { 1077 pins { 1078 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */ 1079 <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */ 1080 }; 1081 }; 1082 1083 m_can1_pins_c: m-can1-2 { 1084 pins1 { 1085 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ 1086 slew-rate = <1>; 1087 drive-push-pull; 1088 bias-disable; 1089 }; 1090 pins2 { 1091 pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */ 1092 bias-disable; 1093 }; 1094 }; 1095 1096 m_can1_sleep_pins_c: m_can1-sleep-2 { 1097 pins { 1098 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ 1099 <STM32_PINMUX('H', 14, ANALOG)>; /* CAN1_RX */ 1100 }; 1101 }; 1102 1103 m_can2_pins_a: m-can2-0 { 1104 pins1 { 1105 pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ 1106 slew-rate = <1>; 1107 drive-push-pull; 1108 bias-disable; 1109 }; 1110 pins2 { 1111 pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */ 1112 bias-disable; 1113 }; 1114 }; 1115 1116 m_can2_sleep_pins_a: m_can2-sleep-0 { 1117 pins { 1118 pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */ 1119 <STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */ 1120 }; 1121 }; 1122 1123 pwm1_pins_a: pwm1-0 { 1124 pins { 1125 pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */ 1126 <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */ 1127 <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */ 1128 bias-pull-down; 1129 drive-push-pull; 1130 slew-rate = <0>; 1131 }; 1132 }; 1133 1134 pwm1_sleep_pins_a: pwm1-sleep-0 { 1135 pins { 1136 pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */ 1137 <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */ 1138 <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */ 1139 }; 1140 }; 1141 1142 pwm1_pins_b: pwm1-1 { 1143 pins { 1144 pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */ 1145 bias-pull-down; 1146 drive-push-pull; 1147 slew-rate = <0>; 1148 }; 1149 }; 1150 1151 pwm1_sleep_pins_b: pwm1-sleep-1 { 1152 pins { 1153 pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */ 1154 }; 1155 }; 1156 1157 pwm2_pins_a: pwm2-0 { 1158 pins { 1159 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ 1160 bias-pull-down; 1161 drive-push-pull; 1162 slew-rate = <0>; 1163 }; 1164 }; 1165 1166 pwm2_sleep_pins_a: pwm2-sleep-0 { 1167 pins { 1168 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */ 1169 }; 1170 }; 1171 1172 pwm3_pins_a: pwm3-0 { 1173 pins { 1174 pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */ 1175 bias-pull-down; 1176 drive-push-pull; 1177 slew-rate = <0>; 1178 }; 1179 }; 1180 1181 pwm3_sleep_pins_a: pwm3-sleep-0 { 1182 pins { 1183 pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */ 1184 }; 1185 }; 1186 1187 pwm3_pins_b: pwm3-1 { 1188 pins { 1189 pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ 1190 bias-disable; 1191 drive-push-pull; 1192 slew-rate = <0>; 1193 }; 1194 }; 1195 1196 pwm3_sleep_pins_b: pwm3-sleep-1 { 1197 pins { 1198 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */ 1199 }; 1200 }; 1201 1202 pwm4_pins_a: pwm4-0 { 1203 pins { 1204 pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */ 1205 <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */ 1206 bias-pull-down; 1207 drive-push-pull; 1208 slew-rate = <0>; 1209 }; 1210 }; 1211 1212 pwm4_sleep_pins_a: pwm4-sleep-0 { 1213 pins { 1214 pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */ 1215 <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */ 1216 }; 1217 }; 1218 1219 pwm4_pins_b: pwm4-1 { 1220 pins { 1221 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ 1222 bias-pull-down; 1223 drive-push-pull; 1224 slew-rate = <0>; 1225 }; 1226 }; 1227 1228 pwm4_sleep_pins_b: pwm4-sleep-1 { 1229 pins { 1230 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ 1231 }; 1232 }; 1233 1234 pwm5_pins_a: pwm5-0 { 1235 pins { 1236 pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */ 1237 bias-pull-down; 1238 drive-push-pull; 1239 slew-rate = <0>; 1240 }; 1241 }; 1242 1243 pwm5_sleep_pins_a: pwm5-sleep-0 { 1244 pins { 1245 pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */ 1246 }; 1247 }; 1248 1249 pwm5_pins_b: pwm5-1 { 1250 pins { 1251 pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */ 1252 <STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */ 1253 <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */ 1254 bias-disable; 1255 drive-push-pull; 1256 slew-rate = <0>; 1257 }; 1258 }; 1259 1260 pwm5_sleep_pins_b: pwm5-sleep-1 { 1261 pins { 1262 pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */ 1263 <STM32_PINMUX('H', 12, ANALOG)>, /* TIM5_CH3 */ 1264 <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */ 1265 }; 1266 }; 1267 1268 pwm8_pins_a: pwm8-0 { 1269 pins { 1270 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */ 1271 bias-pull-down; 1272 drive-push-pull; 1273 slew-rate = <0>; 1274 }; 1275 }; 1276 1277 pwm8_sleep_pins_a: pwm8-sleep-0 { 1278 pins { 1279 pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */ 1280 }; 1281 }; 1282 1283 pwm12_pins_a: pwm12-0 { 1284 pins { 1285 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */ 1286 bias-pull-down; 1287 drive-push-pull; 1288 slew-rate = <0>; 1289 }; 1290 }; 1291 1292 pwm12_sleep_pins_a: pwm12-sleep-0 { 1293 pins { 1294 pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */ 1295 }; 1296 }; 1297 1298 qspi_clk_pins_a: qspi-clk-0 { 1299 pins { 1300 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ 1301 bias-disable; 1302 drive-push-pull; 1303 slew-rate = <3>; 1304 }; 1305 }; 1306 1307 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { 1308 pins { 1309 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ 1310 }; 1311 }; 1312 1313 qspi_bk1_pins_a: qspi-bk1-0 { 1314 pins { 1315 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ 1316 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ 1317 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ 1318 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ 1319 bias-disable; 1320 drive-push-pull; 1321 slew-rate = <1>; 1322 }; 1323 }; 1324 1325 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { 1326 pins { 1327 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ 1328 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ 1329 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ 1330 <STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */ 1331 }; 1332 }; 1333 1334 qspi_bk2_pins_a: qspi-bk2-0 { 1335 pins { 1336 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ 1337 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ 1338 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ 1339 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */ 1340 bias-disable; 1341 drive-push-pull; 1342 slew-rate = <1>; 1343 }; 1344 }; 1345 1346 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { 1347 pins { 1348 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ 1349 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ 1350 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ 1351 <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */ 1352 }; 1353 }; 1354 1355 qspi_cs1_pins_a: qspi-cs1-0 { 1356 pins { 1357 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ 1358 bias-pull-up; 1359 drive-push-pull; 1360 slew-rate = <1>; 1361 }; 1362 }; 1363 1364 qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { 1365 pins { 1366 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ 1367 }; 1368 }; 1369 1370 qspi_cs2_pins_a: qspi-cs2-0 { 1371 pins { 1372 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ 1373 bias-pull-up; 1374 drive-push-pull; 1375 slew-rate = <1>; 1376 }; 1377 }; 1378 1379 qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 { 1380 pins { 1381 pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ 1382 }; 1383 }; 1384 1385 sai2a_pins_a: sai2a-0 { 1386 pins { 1387 pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */ 1388 <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ 1389 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ 1390 <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */ 1391 slew-rate = <0>; 1392 drive-push-pull; 1393 bias-disable; 1394 }; 1395 }; 1396 1397 sai2a_sleep_pins_a: sai2a-sleep-0 { 1398 pins { 1399 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ 1400 <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ 1401 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ 1402 <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */ 1403 }; 1404 }; 1405 1406 sai2a_pins_b: sai2a-1 { 1407 pins1 { 1408 pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ 1409 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ 1410 <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */ 1411 slew-rate = <0>; 1412 drive-push-pull; 1413 bias-disable; 1414 }; 1415 }; 1416 1417 sai2a_sleep_pins_b: sai2a-sleep-1 { 1418 pins { 1419 pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ 1420 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ 1421 <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */ 1422 }; 1423 }; 1424 1425 sai2a_pins_c: sai2a-2 { 1426 pins { 1427 pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */ 1428 <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */ 1429 <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */ 1430 slew-rate = <0>; 1431 drive-push-pull; 1432 bias-disable; 1433 }; 1434 }; 1435 1436 sai2a_sleep_pins_c: sai2a-sleep-2 { 1437 pins { 1438 pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */ 1439 <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */ 1440 <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */ 1441 }; 1442 }; 1443 1444 sai2b_pins_a: sai2b-0 { 1445 pins1 { 1446 pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */ 1447 <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */ 1448 <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */ 1449 slew-rate = <0>; 1450 drive-push-pull; 1451 bias-disable; 1452 }; 1453 pins2 { 1454 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1455 bias-disable; 1456 }; 1457 }; 1458 1459 sai2b_sleep_pins_a: sai2b-sleep-0 { 1460 pins { 1461 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */ 1462 <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */ 1463 <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */ 1464 <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */ 1465 }; 1466 }; 1467 1468 sai2b_pins_b: sai2b-1 { 1469 pins { 1470 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1471 bias-disable; 1472 }; 1473 }; 1474 1475 sai2b_sleep_pins_b: sai2b-sleep-1 { 1476 pins { 1477 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ 1478 }; 1479 }; 1480 1481 sai2b_pins_c: sai2b-2 { 1482 pins1 { 1483 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1484 bias-disable; 1485 }; 1486 }; 1487 1488 sai2b_sleep_pins_c: sai2b-sleep-2 { 1489 pins { 1490 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ 1491 }; 1492 }; 1493 1494 sai2b_pins_d: sai2b-3 { 1495 pins1 { 1496 pinmux = <STM32_PINMUX('H', 2, AF10)>, /* SAI2_SCK_B */ 1497 <STM32_PINMUX('C', 0, AF8)>, /* SAI2_FS_B */ 1498 <STM32_PINMUX('H', 3, AF10)>; /* SAI2_MCLK_B */ 1499 slew-rate = <0>; 1500 drive-push-pull; 1501 bias-disable; 1502 }; 1503 pins2 { 1504 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1505 bias-disable; 1506 }; 1507 }; 1508 1509 sai2b_sleep_pins_d: sai2b-sleep-3 { 1510 pins1 { 1511 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* SAI2_SCK_B */ 1512 <STM32_PINMUX('C', 0, ANALOG)>, /* SAI2_FS_B */ 1513 <STM32_PINMUX('H', 3, ANALOG)>, /* SAI2_MCLK_B */ 1514 <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ 1515 }; 1516 }; 1517 1518 sai4a_pins_a: sai4a-0 { 1519 pins { 1520 pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */ 1521 slew-rate = <0>; 1522 drive-push-pull; 1523 bias-disable; 1524 }; 1525 }; 1526 1527 sai4a_sleep_pins_a: sai4a-sleep-0 { 1528 pins { 1529 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */ 1530 }; 1531 }; 1532 1533 sdmmc1_b4_pins_a: sdmmc1-b4-0 { 1534 pins1 { 1535 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1536 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1537 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 1538 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ 1539 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 1540 slew-rate = <1>; 1541 drive-push-pull; 1542 bias-disable; 1543 }; 1544 pins2 { 1545 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 1546 slew-rate = <2>; 1547 drive-push-pull; 1548 bias-disable; 1549 }; 1550 }; 1551 1552 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { 1553 pins1 { 1554 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1555 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1556 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 1557 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ 1558 slew-rate = <1>; 1559 drive-push-pull; 1560 bias-disable; 1561 }; 1562 pins2 { 1563 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 1564 slew-rate = <2>; 1565 drive-push-pull; 1566 bias-disable; 1567 }; 1568 pins3 { 1569 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 1570 slew-rate = <1>; 1571 drive-open-drain; 1572 bias-disable; 1573 }; 1574 }; 1575 1576 sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 { 1577 pins1 { 1578 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1579 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1580 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 1581 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ 1582 slew-rate = <1>; 1583 drive-push-pull; 1584 bias-disable; 1585 }; 1586 }; 1587 1588 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { 1589 pins { 1590 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ 1591 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ 1592 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ 1593 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ 1594 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ 1595 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ 1596 }; 1597 }; 1598 1599 sdmmc1_b4_pins_b: sdmmc1-b4-1 { 1600 pins1 { 1601 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1602 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1603 <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */ 1604 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ 1605 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 1606 slew-rate = <1>; 1607 drive-push-pull; 1608 bias-disable; 1609 }; 1610 pins2 { 1611 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 1612 slew-rate = <2>; 1613 drive-push-pull; 1614 bias-disable; 1615 }; 1616 }; 1617 1618 sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 { 1619 pins1 { 1620 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1621 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1622 <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */ 1623 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ 1624 slew-rate = <1>; 1625 drive-push-pull; 1626 bias-disable; 1627 }; 1628 pins2 { 1629 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 1630 slew-rate = <2>; 1631 drive-push-pull; 1632 bias-disable; 1633 }; 1634 pins3 { 1635 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 1636 slew-rate = <1>; 1637 drive-open-drain; 1638 bias-disable; 1639 }; 1640 }; 1641 1642 sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 { 1643 pins { 1644 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ 1645 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ 1646 <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC1_D2 */ 1647 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ 1648 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ 1649 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ 1650 }; 1651 }; 1652 1653 sdmmc1_dir_pins_a: sdmmc1-dir-0 { 1654 pins1 { 1655 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 1656 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ 1657 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 1658 slew-rate = <1>; 1659 drive-push-pull; 1660 bias-pull-up; 1661 }; 1662 pins2 { 1663 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ 1664 bias-pull-up; 1665 }; 1666 }; 1667 1668 sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 { 1669 pins1 { 1670 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 1671 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ 1672 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 1673 slew-rate = <1>; 1674 drive-push-pull; 1675 bias-pull-up; 1676 }; 1677 }; 1678 1679 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { 1680 pins { 1681 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ 1682 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ 1683 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ 1684 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ 1685 }; 1686 }; 1687 1688 sdmmc1_dir_pins_b: sdmmc1-dir-1 { 1689 pins1 { 1690 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 1691 <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */ 1692 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 1693 slew-rate = <1>; 1694 drive-push-pull; 1695 bias-pull-up; 1696 }; 1697 pins2 { 1698 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ 1699 bias-pull-up; 1700 }; 1701 }; 1702 1703 sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { 1704 pins { 1705 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ 1706 <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */ 1707 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ 1708 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ 1709 }; 1710 }; 1711 1712 sdmmc2_b4_pins_a: sdmmc2-b4-0 { 1713 pins1 { 1714 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1715 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1716 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1717 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 1718 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1719 slew-rate = <1>; 1720 drive-push-pull; 1721 bias-pull-up; 1722 }; 1723 pins2 { 1724 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1725 slew-rate = <2>; 1726 drive-push-pull; 1727 bias-pull-up; 1728 }; 1729 }; 1730 1731 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { 1732 pins1 { 1733 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1734 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1735 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1736 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ 1737 slew-rate = <1>; 1738 drive-push-pull; 1739 bias-pull-up; 1740 }; 1741 pins2 { 1742 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1743 slew-rate = <2>; 1744 drive-push-pull; 1745 bias-pull-up; 1746 }; 1747 pins3 { 1748 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1749 slew-rate = <1>; 1750 drive-open-drain; 1751 bias-pull-up; 1752 }; 1753 }; 1754 1755 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { 1756 pins { 1757 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ 1758 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ 1759 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ 1760 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ 1761 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ 1762 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ 1763 }; 1764 }; 1765 1766 sdmmc2_b4_pins_b: sdmmc2-b4-1 { 1767 pins1 { 1768 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1769 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1770 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1771 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 1772 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1773 slew-rate = <1>; 1774 drive-push-pull; 1775 bias-disable; 1776 }; 1777 pins2 { 1778 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1779 slew-rate = <2>; 1780 drive-push-pull; 1781 bias-disable; 1782 }; 1783 }; 1784 1785 sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { 1786 pins1 { 1787 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1788 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1789 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1790 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ 1791 slew-rate = <1>; 1792 drive-push-pull; 1793 bias-disable; 1794 }; 1795 pins2 { 1796 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1797 slew-rate = <2>; 1798 drive-push-pull; 1799 bias-disable; 1800 }; 1801 pins3 { 1802 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1803 slew-rate = <1>; 1804 drive-open-drain; 1805 bias-disable; 1806 }; 1807 }; 1808 1809 sdmmc2_d47_pins_a: sdmmc2-d47-0 { 1810 pins { 1811 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1812 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1813 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ 1814 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ 1815 slew-rate = <1>; 1816 drive-push-pull; 1817 bias-pull-up; 1818 }; 1819 }; 1820 1821 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { 1822 pins { 1823 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1824 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1825 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ 1826 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ 1827 }; 1828 }; 1829 1830 sdmmc2_d47_pins_b: sdmmc2-d47-1 { 1831 pins { 1832 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1833 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1834 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 1835 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 1836 slew-rate = <1>; 1837 drive-push-pull; 1838 bias-disable; 1839 }; 1840 }; 1841 1842 sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { 1843 pins { 1844 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1845 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1846 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ 1847 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 1848 }; 1849 }; 1850 1851 sdmmc2_d47_pins_c: sdmmc2-d47-2 { 1852 pins { 1853 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1854 <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */ 1855 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 1856 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 1857 slew-rate = <1>; 1858 drive-push-pull; 1859 bias-pull-up; 1860 }; 1861 }; 1862 1863 sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 { 1864 pins { 1865 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1866 <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */ 1867 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ 1868 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 1869 }; 1870 }; 1871 1872 sdmmc2_d47_pins_d: sdmmc2-d47-3 { 1873 pins { 1874 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1875 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1876 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ 1877 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 1878 }; 1879 }; 1880 1881 sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { 1882 pins { 1883 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1884 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1885 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ 1886 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 1887 }; 1888 }; 1889 1890 sdmmc2_d47_pins_e: sdmmc2-d47-4 { 1891 pins { 1892 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1893 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1894 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 1895 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ 1896 slew-rate = <1>; 1897 drive-push-pull; 1898 bias-pull-up; 1899 }; 1900 }; 1901 1902 sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 { 1903 pins { 1904 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1905 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1906 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ 1907 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ 1908 }; 1909 }; 1910 1911 sdmmc3_b4_pins_a: sdmmc3-b4-0 { 1912 pins1 { 1913 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1914 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1915 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ 1916 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ 1917 <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */ 1918 slew-rate = <1>; 1919 drive-push-pull; 1920 bias-pull-up; 1921 }; 1922 pins2 { 1923 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1924 slew-rate = <2>; 1925 drive-push-pull; 1926 bias-pull-up; 1927 }; 1928 }; 1929 1930 sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { 1931 pins1 { 1932 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1933 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1934 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ 1935 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ 1936 slew-rate = <1>; 1937 drive-push-pull; 1938 bias-pull-up; 1939 }; 1940 pins2 { 1941 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1942 slew-rate = <2>; 1943 drive-push-pull; 1944 bias-pull-up; 1945 }; 1946 pins3 { 1947 pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */ 1948 slew-rate = <1>; 1949 drive-open-drain; 1950 bias-pull-up; 1951 }; 1952 }; 1953 1954 sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { 1955 pins { 1956 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ 1957 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ 1958 <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */ 1959 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ 1960 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ 1961 <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */ 1962 }; 1963 }; 1964 1965 sdmmc3_b4_pins_b: sdmmc3-b4-1 { 1966 pins1 { 1967 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1968 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1969 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ 1970 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ 1971 <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ 1972 slew-rate = <1>; 1973 drive-push-pull; 1974 bias-pull-up; 1975 }; 1976 pins2 { 1977 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1978 slew-rate = <2>; 1979 drive-push-pull; 1980 bias-pull-up; 1981 }; 1982 }; 1983 1984 sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { 1985 pins1 { 1986 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1987 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1988 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ 1989 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ 1990 slew-rate = <1>; 1991 drive-push-pull; 1992 bias-pull-up; 1993 }; 1994 pins2 { 1995 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1996 slew-rate = <2>; 1997 drive-push-pull; 1998 bias-pull-up; 1999 }; 2000 pins3 { 2001 pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */ 2002 slew-rate = <1>; 2003 drive-open-drain; 2004 bias-pull-up; 2005 }; 2006 }; 2007 2008 sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { 2009 pins { 2010 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ 2011 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ 2012 <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */ 2013 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ 2014 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ 2015 <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */ 2016 }; 2017 }; 2018 2019 spdifrx_pins_a: spdifrx-0 { 2020 pins { 2021 pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ 2022 bias-disable; 2023 }; 2024 }; 2025 2026 spdifrx_sleep_pins_a: spdifrx-sleep-0 { 2027 pins { 2028 pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */ 2029 }; 2030 }; 2031 2032 spi1_pins_b: spi1-1 { 2033 pins1 { 2034 pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */ 2035 <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */ 2036 bias-disable; 2037 drive-push-pull; 2038 slew-rate = <1>; 2039 }; 2040 2041 pins2 { 2042 pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */ 2043 bias-disable; 2044 }; 2045 }; 2046 2047 spi2_pins_a: spi2-0 { 2048 pins1 { 2049 pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */ 2050 <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ 2051 bias-disable; 2052 drive-push-pull; 2053 slew-rate = <1>; 2054 }; 2055 2056 pins2 { 2057 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ 2058 bias-disable; 2059 }; 2060 }; 2061 2062 spi2_pins_b: spi2-1 { 2063 pins1 { 2064 pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */ 2065 <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ 2066 bias-disable; 2067 drive-push-pull; 2068 slew-rate = <1>; 2069 }; 2070 2071 pins2 { 2072 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ 2073 bias-disable; 2074 }; 2075 }; 2076 2077 spi4_pins_a: spi4-0 { 2078 pins { 2079 pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ 2080 <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */ 2081 bias-disable; 2082 drive-push-pull; 2083 slew-rate = <1>; 2084 }; 2085 pins2 { 2086 pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */ 2087 bias-disable; 2088 }; 2089 }; 2090 2091 stusb1600_pins_a: stusb1600-0 { 2092 pins { 2093 pinmux = <STM32_PINMUX('I', 11, GPIO)>; 2094 bias-pull-up; 2095 }; 2096 }; 2097 2098 uart4_pins_a: uart4-0 { 2099 pins1 { 2100 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ 2101 bias-disable; 2102 drive-push-pull; 2103 slew-rate = <0>; 2104 }; 2105 pins2 { 2106 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 2107 bias-disable; 2108 }; 2109 }; 2110 2111 uart4_idle_pins_a: uart4-idle-0 { 2112 pins1 { 2113 pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ 2114 }; 2115 pins2 { 2116 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 2117 bias-disable; 2118 }; 2119 }; 2120 2121 uart4_sleep_pins_a: uart4-sleep-0 { 2122 pins { 2123 pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ 2124 <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ 2125 }; 2126 }; 2127 2128 uart4_pins_b: uart4-1 { 2129 pins1 { 2130 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ 2131 bias-disable; 2132 drive-push-pull; 2133 slew-rate = <0>; 2134 }; 2135 pins2 { 2136 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 2137 bias-disable; 2138 }; 2139 }; 2140 2141 uart4_pins_c: uart4-2 { 2142 pins1 { 2143 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ 2144 bias-disable; 2145 drive-push-pull; 2146 slew-rate = <0>; 2147 }; 2148 pins2 { 2149 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 2150 bias-disable; 2151 }; 2152 }; 2153 2154 uart4_pins_d: uart4-3 { 2155 pins1 { 2156 pinmux = <STM32_PINMUX('A', 13, AF8)>; /* UART4_TX */ 2157 bias-disable; 2158 drive-push-pull; 2159 slew-rate = <0>; 2160 }; 2161 pins2 { 2162 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 2163 bias-disable; 2164 }; 2165 }; 2166 2167 uart4_idle_pins_d: uart4-idle-3 { 2168 pins1 { 2169 pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* UART4_TX */ 2170 }; 2171 pins2 { 2172 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 2173 bias-disable; 2174 }; 2175 }; 2176 2177 uart4_sleep_pins_d: uart4-sleep-3 { 2178 pins { 2179 pinmux = <STM32_PINMUX('A', 13, ANALOG)>, /* UART4_TX */ 2180 <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ 2181 }; 2182 }; 2183 2184 uart5_pins_a: uart5-0 { 2185 pins1 { 2186 pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */ 2187 bias-disable; 2188 drive-push-pull; 2189 slew-rate = <0>; 2190 }; 2191 pins2 { 2192 pinmux = <STM32_PINMUX('B', 5, AF12)>; /* UART5_RX */ 2193 bias-disable; 2194 }; 2195 }; 2196 2197 uart7_pins_a: uart7-0 { 2198 pins1 { 2199 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ 2200 bias-disable; 2201 drive-push-pull; 2202 slew-rate = <0>; 2203 }; 2204 pins2 { 2205 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */ 2206 <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */ 2207 <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */ 2208 bias-disable; 2209 }; 2210 }; 2211 2212 uart7_pins_b: uart7-1 { 2213 pins1 { 2214 pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ 2215 bias-disable; 2216 drive-push-pull; 2217 slew-rate = <0>; 2218 }; 2219 pins2 { 2220 pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */ 2221 bias-disable; 2222 }; 2223 }; 2224 2225 uart7_pins_c: uart7-2 { 2226 pins1 { 2227 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ 2228 bias-disable; 2229 drive-push-pull; 2230 slew-rate = <0>; 2231 }; 2232 pins2 { 2233 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ 2234 bias-pull-up; 2235 }; 2236 }; 2237 2238 uart7_idle_pins_c: uart7-idle-2 { 2239 pins1 { 2240 pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */ 2241 }; 2242 pins2 { 2243 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ 2244 bias-pull-up; 2245 }; 2246 }; 2247 2248 uart7_sleep_pins_c: uart7-sleep-2 { 2249 pins { 2250 pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */ 2251 <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */ 2252 }; 2253 }; 2254 2255 uart8_pins_a: uart8-0 { 2256 pins1 { 2257 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ 2258 bias-disable; 2259 drive-push-pull; 2260 slew-rate = <0>; 2261 }; 2262 pins2 { 2263 pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */ 2264 bias-disable; 2265 }; 2266 }; 2267 2268 uart8_rtscts_pins_a: uart8rtscts-0 { 2269 pins { 2270 pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */ 2271 <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */ 2272 bias-disable; 2273 }; 2274 }; 2275 2276 usart1_pins_a: usart1-0 { 2277 pins1 { 2278 pinmux = <STM32_PINMUX('A', 12, AF7)>; /* USART1_RTS */ 2279 bias-disable; 2280 drive-push-pull; 2281 slew-rate = <0>; 2282 }; 2283 pins2 { 2284 pinmux = <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */ 2285 bias-disable; 2286 }; 2287 }; 2288 2289 usart1_idle_pins_a: usart1-idle-0 { 2290 pins1 { 2291 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */ 2292 <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */ 2293 }; 2294 }; 2295 2296 usart1_sleep_pins_a: usart1-sleep-0 { 2297 pins { 2298 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */ 2299 <STM32_PINMUX('A', 11, ANALOG)>; /* USART1_CTS_NSS */ 2300 }; 2301 }; 2302 2303 usart2_pins_a: usart2-0 { 2304 pins1 { 2305 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ 2306 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ 2307 bias-disable; 2308 drive-push-pull; 2309 slew-rate = <0>; 2310 }; 2311 pins2 { 2312 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ 2313 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ 2314 bias-disable; 2315 }; 2316 }; 2317 2318 usart2_sleep_pins_a: usart2-sleep-0 { 2319 pins { 2320 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ 2321 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ 2322 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ 2323 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ 2324 }; 2325 }; 2326 2327 usart2_pins_b: usart2-1 { 2328 pins1 { 2329 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ 2330 <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ 2331 bias-disable; 2332 drive-push-pull; 2333 slew-rate = <0>; 2334 }; 2335 pins2 { 2336 pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */ 2337 <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */ 2338 bias-disable; 2339 }; 2340 }; 2341 2342 usart2_sleep_pins_b: usart2-sleep-1 { 2343 pins { 2344 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ 2345 <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ 2346 <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */ 2347 <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ 2348 }; 2349 }; 2350 2351 usart2_pins_c: usart2-2 { 2352 pins1 { 2353 pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */ 2354 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ 2355 bias-disable; 2356 drive-push-pull; 2357 slew-rate = <0>; 2358 }; 2359 pins2 { 2360 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ 2361 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ 2362 bias-disable; 2363 }; 2364 }; 2365 2366 usart2_idle_pins_c: usart2-idle-2 { 2367 pins1 { 2368 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ 2369 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ 2370 }; 2371 pins2 { 2372 pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ 2373 bias-disable; 2374 drive-push-pull; 2375 slew-rate = <0>; 2376 }; 2377 pins3 { 2378 pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ 2379 bias-disable; 2380 }; 2381 }; 2382 2383 usart2_sleep_pins_c: usart2-sleep-2 { 2384 pins { 2385 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ 2386 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ 2387 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ 2388 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ 2389 }; 2390 }; 2391 2392 usart3_pins_a: usart3-0 { 2393 pins1 { 2394 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ 2395 bias-disable; 2396 drive-push-pull; 2397 slew-rate = <0>; 2398 }; 2399 pins2 { 2400 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 2401 bias-disable; 2402 }; 2403 }; 2404 2405 usart3_idle_pins_a: usart3-idle-0 { 2406 pins1 { 2407 pinmux = <STM32_PINMUX('B', 10, ANALOG)>; /* USART3_TX */ 2408 }; 2409 pins2 { 2410 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 2411 bias-disable; 2412 }; 2413 }; 2414 2415 usart3_sleep_pins_a: usart3-sleep-0 { 2416 pins { 2417 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2418 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ 2419 }; 2420 }; 2421 2422 usart3_pins_b: usart3-1 { 2423 pins1 { 2424 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 2425 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2426 bias-disable; 2427 drive-push-pull; 2428 slew-rate = <0>; 2429 }; 2430 pins2 { 2431 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ 2432 <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */ 2433 bias-pull-up; 2434 }; 2435 }; 2436 2437 usart3_idle_pins_b: usart3-idle-1 { 2438 pins1 { 2439 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2440 <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */ 2441 }; 2442 pins2 { 2443 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2444 bias-disable; 2445 drive-push-pull; 2446 slew-rate = <0>; 2447 }; 2448 pins3 { 2449 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 2450 bias-pull-up; 2451 }; 2452 }; 2453 2454 usart3_sleep_pins_b: usart3-sleep-1 { 2455 pins { 2456 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2457 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2458 <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */ 2459 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ 2460 }; 2461 }; 2462 2463 usart3_pins_c: usart3-2 { 2464 pins1 { 2465 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 2466 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2467 bias-disable; 2468 drive-push-pull; 2469 slew-rate = <0>; 2470 }; 2471 pins2 { 2472 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ 2473 <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */ 2474 bias-pull-up; 2475 }; 2476 }; 2477 2478 usart3_idle_pins_c: usart3-idle-2 { 2479 pins1 { 2480 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2481 <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */ 2482 }; 2483 pins2 { 2484 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2485 bias-disable; 2486 drive-push-pull; 2487 slew-rate = <0>; 2488 }; 2489 pins3 { 2490 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 2491 bias-pull-up; 2492 }; 2493 }; 2494 2495 usart3_sleep_pins_c: usart3-sleep-2 { 2496 pins { 2497 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2498 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2499 <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */ 2500 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ 2501 }; 2502 }; 2503 2504 usart3_pins_d: usart3-3 { 2505 pins1 { 2506 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 2507 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2508 bias-disable; 2509 drive-push-pull; 2510 slew-rate = <0>; 2511 }; 2512 pins2 { 2513 pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */ 2514 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ 2515 bias-disable; 2516 }; 2517 }; 2518 2519 usart3_idle_pins_d: usart3-idle-3 { 2520 pins1 { 2521 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2522 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2523 <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */ 2524 }; 2525 pins2 { 2526 pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */ 2527 bias-disable; 2528 }; 2529 }; 2530 2531 usart3_sleep_pins_d: usart3-sleep-3 { 2532 pins { 2533 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2534 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2535 <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */ 2536 <STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */ 2537 }; 2538 }; 2539 2540 usart3_pins_e: usart3-4 { 2541 pins1 { 2542 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 2543 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2544 bias-disable; 2545 drive-push-pull; 2546 slew-rate = <0>; 2547 }; 2548 pins2 { 2549 pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */ 2550 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ 2551 bias-pull-up; 2552 }; 2553 }; 2554 2555 usart3_idle_pins_e: usart3-idle-4 { 2556 pins1 { 2557 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2558 <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */ 2559 }; 2560 pins2 { 2561 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2562 bias-disable; 2563 drive-push-pull; 2564 slew-rate = <0>; 2565 }; 2566 pins3 { 2567 pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */ 2568 bias-pull-up; 2569 }; 2570 }; 2571 2572 usart3_sleep_pins_e: usart3-sleep-4 { 2573 pins { 2574 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2575 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2576 <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */ 2577 <STM32_PINMUX('B', 11, ANALOG)>; /* USART3_RX */ 2578 }; 2579 }; 2580 2581 usbotg_hs_pins_a: usbotg-hs-0 { 2582 pins { 2583 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ 2584 }; 2585 }; 2586 2587 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { 2588 pins { 2589 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */ 2590 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */ 2591 }; 2592 }; 2593}; 2594 2595&pinctrl_z { 2596 i2c2_pins_b2: i2c2-0 { 2597 pins { 2598 pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */ 2599 bias-disable; 2600 drive-open-drain; 2601 slew-rate = <0>; 2602 }; 2603 }; 2604 2605 i2c2_sleep_pins_b2: i2c2-sleep-0 { 2606 pins { 2607 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */ 2608 }; 2609 }; 2610 2611 i2c4_pins_a: i2c4-0 { 2612 pins { 2613 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ 2614 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ 2615 bias-disable; 2616 drive-open-drain; 2617 slew-rate = <0>; 2618 }; 2619 }; 2620 2621 i2c4_sleep_pins_a: i2c4-sleep-0 { 2622 pins { 2623 pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ 2624 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */ 2625 }; 2626 }; 2627 2628 i2c6_pins_a: i2c6-0 { 2629 pins { 2630 pinmux = <STM32_PINMUX('Z', 6, AF2)>, /* I2C6_SCL */ 2631 <STM32_PINMUX('Z', 7, AF2)>; /* I2C6_SDA */ 2632 bias-disable; 2633 drive-open-drain; 2634 slew-rate = <0>; 2635 }; 2636 }; 2637 2638 i2c6_sleep_pins_a: i2c6-sleep-0 { 2639 pins { 2640 pinmux = <STM32_PINMUX('Z', 6, ANALOG)>, /* I2C6_SCL */ 2641 <STM32_PINMUX('Z', 7, ANALOG)>; /* I2C6_SDA */ 2642 }; 2643 }; 2644 2645 spi1_pins_a: spi1-0 { 2646 pins1 { 2647 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ 2648 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */ 2649 bias-disable; 2650 drive-push-pull; 2651 slew-rate = <1>; 2652 }; 2653 2654 pins2 { 2655 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */ 2656 bias-disable; 2657 }; 2658 }; 2659 2660 spi1_sleep_pins_a: spi1-sleep-0 { 2661 pins { 2662 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */ 2663 <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */ 2664 <STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */ 2665 }; 2666 }; 2667 2668 usart1_pins_b: usart1-1 { 2669 pins1 { 2670 pinmux = <STM32_PINMUX('Z', 7, AF7)>; /* USART1_TX */ 2671 bias-disable; 2672 drive-push-pull; 2673 slew-rate = <0>; 2674 }; 2675 pins2 { 2676 pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */ 2677 bias-disable; 2678 }; 2679 }; 2680 2681 usart1_idle_pins_b: usart1-idle-1 { 2682 pins1 { 2683 pinmux = <STM32_PINMUX('Z', 7, ANALOG)>; /* USART1_TX */ 2684 }; 2685 pins2 { 2686 pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */ 2687 bias-disable; 2688 }; 2689 }; 2690 2691 usart1_sleep_pins_b: usart1-sleep-1 { 2692 pins { 2693 pinmux = <STM32_PINMUX('Z', 7, ANALOG)>, /* USART1_TX */ 2694 <STM32_PINMUX('Z', 6, ANALOG)>; /* USART1_RX */ 2695 }; 2696 }; 2697}; 2698