1/* 2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include "../armv7-m.dtsi" 44#include <dt-bindings/clock/stm32fx-clock.h> 45#include <dt-bindings/mfd/stm32f7-rcc.h> 46 47/ { 48 #address-cells = <1>; 49 #size-cells = <1>; 50 51 clocks { 52 clk_hse: clk-hse { 53 #clock-cells = <0>; 54 compatible = "fixed-clock"; 55 clock-frequency = <0>; 56 }; 57 58 clk-lse { 59 #clock-cells = <0>; 60 compatible = "fixed-clock"; 61 clock-frequency = <32768>; 62 }; 63 64 clk-lsi { 65 #clock-cells = <0>; 66 compatible = "fixed-clock"; 67 clock-frequency = <32000>; 68 }; 69 70 clk_i2s_ckin: clk-i2s-ckin { 71 #clock-cells = <0>; 72 compatible = "fixed-clock"; 73 clock-frequency = <48000000>; 74 }; 75 }; 76 77 soc { 78 timers2: timers@40000000 { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 compatible = "st,stm32-timers"; 82 reg = <0x40000000 0x400>; 83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; 84 clock-names = "int"; 85 status = "disabled"; 86 87 pwm { 88 compatible = "st,stm32-pwm"; 89 #pwm-cells = <3>; 90 status = "disabled"; 91 }; 92 93 timer@1 { 94 compatible = "st,stm32-timer-trigger"; 95 reg = <1>; 96 status = "disabled"; 97 }; 98 }; 99 100 timers3: timers@40000400 { 101 #address-cells = <1>; 102 #size-cells = <0>; 103 compatible = "st,stm32-timers"; 104 reg = <0x40000400 0x400>; 105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; 106 clock-names = "int"; 107 status = "disabled"; 108 109 pwm { 110 compatible = "st,stm32-pwm"; 111 #pwm-cells = <3>; 112 status = "disabled"; 113 }; 114 115 timer@2 { 116 compatible = "st,stm32-timer-trigger"; 117 reg = <2>; 118 status = "disabled"; 119 }; 120 }; 121 122 timers4: timers@40000800 { 123 #address-cells = <1>; 124 #size-cells = <0>; 125 compatible = "st,stm32-timers"; 126 reg = <0x40000800 0x400>; 127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; 128 clock-names = "int"; 129 status = "disabled"; 130 131 pwm { 132 compatible = "st,stm32-pwm"; 133 #pwm-cells = <3>; 134 status = "disabled"; 135 }; 136 137 timer@3 { 138 compatible = "st,stm32-timer-trigger"; 139 reg = <3>; 140 status = "disabled"; 141 }; 142 }; 143 144 timers5: timers@40000c00 { 145 #address-cells = <1>; 146 #size-cells = <0>; 147 compatible = "st,stm32-timers"; 148 reg = <0x40000C00 0x400>; 149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; 150 clock-names = "int"; 151 status = "disabled"; 152 153 pwm { 154 compatible = "st,stm32-pwm"; 155 #pwm-cells = <3>; 156 status = "disabled"; 157 }; 158 159 timer@4 { 160 compatible = "st,stm32-timer-trigger"; 161 reg = <4>; 162 status = "disabled"; 163 }; 164 }; 165 166 timers6: timers@40001000 { 167 #address-cells = <1>; 168 #size-cells = <0>; 169 compatible = "st,stm32-timers"; 170 reg = <0x40001000 0x400>; 171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; 172 clock-names = "int"; 173 status = "disabled"; 174 175 timer@5 { 176 compatible = "st,stm32-timer-trigger"; 177 reg = <5>; 178 status = "disabled"; 179 }; 180 }; 181 182 timers7: timers@40001400 { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 compatible = "st,stm32-timers"; 186 reg = <0x40001400 0x400>; 187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; 188 clock-names = "int"; 189 status = "disabled"; 190 191 timer@6 { 192 compatible = "st,stm32-timer-trigger"; 193 reg = <6>; 194 status = "disabled"; 195 }; 196 }; 197 198 timers12: timers@40001800 { 199 #address-cells = <1>; 200 #size-cells = <0>; 201 compatible = "st,stm32-timers"; 202 reg = <0x40001800 0x400>; 203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; 204 clock-names = "int"; 205 status = "disabled"; 206 207 pwm { 208 compatible = "st,stm32-pwm"; 209 #pwm-cells = <3>; 210 status = "disabled"; 211 }; 212 213 timer@11 { 214 compatible = "st,stm32-timer-trigger"; 215 reg = <11>; 216 status = "disabled"; 217 }; 218 }; 219 220 timers13: timers@40001c00 { 221 compatible = "st,stm32-timers"; 222 reg = <0x40001C00 0x400>; 223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; 224 clock-names = "int"; 225 status = "disabled"; 226 227 pwm { 228 compatible = "st,stm32-pwm"; 229 #pwm-cells = <3>; 230 status = "disabled"; 231 }; 232 }; 233 234 timers14: timers@40002000 { 235 compatible = "st,stm32-timers"; 236 reg = <0x40002000 0x400>; 237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; 238 clock-names = "int"; 239 status = "disabled"; 240 241 pwm { 242 compatible = "st,stm32-pwm"; 243 #pwm-cells = <3>; 244 status = "disabled"; 245 }; 246 }; 247 248 rtc: rtc@40002800 { 249 compatible = "st,stm32-rtc"; 250 reg = <0x40002800 0x400>; 251 clocks = <&rcc 1 CLK_RTC>; 252 assigned-clocks = <&rcc 1 CLK_RTC>; 253 assigned-clock-parents = <&rcc 1 CLK_LSE>; 254 interrupt-parent = <&exti>; 255 interrupts = <17 1>; 256 st,syscfg = <&pwrcfg 0x00 0x100>; 257 status = "disabled"; 258 }; 259 260 can3: can@40003400 { 261 compatible = "st,stm32f4-bxcan"; 262 reg = <0x40003400 0x200>; 263 interrupts = <104>, <105>, <106>, <107>; 264 interrupt-names = "tx", "rx0", "rx1", "sce"; 265 resets = <&rcc STM32F7_APB1_RESET(CAN3)>; 266 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; 267 st,gcan = <&gcan3>; 268 status = "disabled"; 269 }; 270 271 gcan3: gcan@40003600 { 272 compatible = "st,stm32f4-gcan", "syscon"; 273 reg = <0x40003600 0x200>; 274 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; 275 }; 276 277 usart2: serial@40004400 { 278 compatible = "st,stm32f7-uart"; 279 reg = <0x40004400 0x400>; 280 interrupts = <38>; 281 clocks = <&rcc 1 CLK_USART2>; 282 status = "disabled"; 283 }; 284 285 usart3: serial@40004800 { 286 compatible = "st,stm32f7-uart"; 287 reg = <0x40004800 0x400>; 288 interrupts = <39>; 289 clocks = <&rcc 1 CLK_USART3>; 290 status = "disabled"; 291 }; 292 293 usart4: serial@40004c00 { 294 compatible = "st,stm32f7-uart"; 295 reg = <0x40004c00 0x400>; 296 interrupts = <52>; 297 clocks = <&rcc 1 CLK_UART4>; 298 status = "disabled"; 299 }; 300 301 usart5: serial@40005000 { 302 compatible = "st,stm32f7-uart"; 303 reg = <0x40005000 0x400>; 304 interrupts = <53>; 305 clocks = <&rcc 1 CLK_UART5>; 306 status = "disabled"; 307 }; 308 309 i2c1: i2c@40005400 { 310 compatible = "st,stm32f7-i2c"; 311 reg = <0x40005400 0x400>; 312 interrupts = <31>, 313 <32>; 314 resets = <&rcc STM32F7_APB1_RESET(I2C1)>; 315 clocks = <&rcc 1 CLK_I2C1>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 status = "disabled"; 319 }; 320 321 i2c2: i2c@40005800 { 322 compatible = "st,stm32f7-i2c"; 323 reg = <0x40005800 0x400>; 324 interrupts = <33>, 325 <34>; 326 resets = <&rcc STM32F7_APB1_RESET(I2C2)>; 327 clocks = <&rcc 1 CLK_I2C2>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 status = "disabled"; 331 }; 332 333 i2c3: i2c@40005c00 { 334 compatible = "st,stm32f7-i2c"; 335 reg = <0x40005c00 0x400>; 336 interrupts = <72>, 337 <73>; 338 resets = <&rcc STM32F7_APB1_RESET(I2C3)>; 339 clocks = <&rcc 1 CLK_I2C3>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 status = "disabled"; 343 }; 344 345 i2c4: i2c@40006000 { 346 compatible = "st,stm32f7-i2c"; 347 reg = <0x40006000 0x400>; 348 interrupts = <95>, 349 <96>; 350 resets = <&rcc STM32F7_APB1_RESET(I2C4)>; 351 clocks = <&rcc 1 CLK_I2C4>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 status = "disabled"; 355 }; 356 357 can1: can@40006400 { 358 compatible = "st,stm32f4-bxcan"; 359 reg = <0x40006400 0x200>; 360 interrupts = <19>, <20>, <21>, <22>; 361 interrupt-names = "tx", "rx0", "rx1", "sce"; 362 resets = <&rcc STM32F7_APB1_RESET(CAN1)>; 363 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; 364 st,can-primary; 365 st,gcan = <&gcan1>; 366 status = "disabled"; 367 }; 368 369 gcan1: gcan@40006600 { 370 compatible = "st,stm32f4-gcan", "syscon"; 371 reg = <0x40006600 0x200>; 372 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; 373 }; 374 375 can2: can@40006800 { 376 compatible = "st,stm32f4-bxcan"; 377 reg = <0x40006800 0x200>; 378 interrupts = <63>, <64>, <65>, <66>; 379 interrupt-names = "tx", "rx0", "rx1", "sce"; 380 resets = <&rcc STM32F7_APB1_RESET(CAN2)>; 381 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>; 382 st,can-secondary; 383 st,gcan = <&gcan1>; 384 status = "disabled"; 385 }; 386 387 cec: cec@40006c00 { 388 compatible = "st,stm32-cec"; 389 reg = <0x40006C00 0x400>; 390 interrupts = <94>; 391 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; 392 clock-names = "cec", "hdmi-cec"; 393 status = "disabled"; 394 }; 395 396 usart7: serial@40007800 { 397 compatible = "st,stm32f7-uart"; 398 reg = <0x40007800 0x400>; 399 interrupts = <82>; 400 clocks = <&rcc 1 CLK_UART7>; 401 status = "disabled"; 402 }; 403 404 usart8: serial@40007c00 { 405 compatible = "st,stm32f7-uart"; 406 reg = <0x40007c00 0x400>; 407 interrupts = <83>; 408 clocks = <&rcc 1 CLK_UART8>; 409 status = "disabled"; 410 }; 411 412 timers1: timers@40010000 { 413 #address-cells = <1>; 414 #size-cells = <0>; 415 compatible = "st,stm32-timers"; 416 reg = <0x40010000 0x400>; 417 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; 418 clock-names = "int"; 419 status = "disabled"; 420 421 pwm { 422 compatible = "st,stm32-pwm"; 423 #pwm-cells = <3>; 424 status = "disabled"; 425 }; 426 427 timer@0 { 428 compatible = "st,stm32-timer-trigger"; 429 reg = <0>; 430 status = "disabled"; 431 }; 432 }; 433 434 timers8: timers@40010400 { 435 #address-cells = <1>; 436 #size-cells = <0>; 437 compatible = "st,stm32-timers"; 438 reg = <0x40010400 0x400>; 439 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; 440 clock-names = "int"; 441 status = "disabled"; 442 443 pwm { 444 compatible = "st,stm32-pwm"; 445 #pwm-cells = <3>; 446 status = "disabled"; 447 }; 448 449 timer@7 { 450 compatible = "st,stm32-timer-trigger"; 451 reg = <7>; 452 status = "disabled"; 453 }; 454 }; 455 456 usart1: serial@40011000 { 457 compatible = "st,stm32f7-uart"; 458 reg = <0x40011000 0x400>; 459 interrupts = <37>; 460 clocks = <&rcc 1 CLK_USART1>; 461 status = "disabled"; 462 }; 463 464 usart6: serial@40011400 { 465 compatible = "st,stm32f7-uart"; 466 reg = <0x40011400 0x400>; 467 interrupts = <71>; 468 clocks = <&rcc 1 CLK_USART6>; 469 status = "disabled"; 470 }; 471 472 sdio2: mmc@40011c00 { 473 compatible = "arm,pl180", "arm,primecell"; 474 arm,primecell-periphid = <0x00880180>; 475 reg = <0x40011c00 0x400>; 476 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>; 477 clock-names = "apb_pclk"; 478 interrupts = <103>; 479 max-frequency = <48000000>; 480 status = "disabled"; 481 }; 482 483 sdio1: mmc@40012c00 { 484 compatible = "arm,pl180", "arm,primecell"; 485 arm,primecell-periphid = <0x00880180>; 486 reg = <0x40012c00 0x400>; 487 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>; 488 clock-names = "apb_pclk"; 489 interrupts = <49>; 490 max-frequency = <48000000>; 491 status = "disabled"; 492 }; 493 494 syscfg: syscon@40013800 { 495 compatible = "st,stm32-syscfg", "syscon"; 496 reg = <0x40013800 0x400>; 497 }; 498 499 exti: interrupt-controller@40013c00 { 500 compatible = "st,stm32-exti"; 501 interrupt-controller; 502 #interrupt-cells = <2>; 503 reg = <0x40013C00 0x400>; 504 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; 505 }; 506 507 timers9: timers@40014000 { 508 #address-cells = <1>; 509 #size-cells = <0>; 510 compatible = "st,stm32-timers"; 511 reg = <0x40014000 0x400>; 512 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; 513 clock-names = "int"; 514 status = "disabled"; 515 516 pwm { 517 compatible = "st,stm32-pwm"; 518 #pwm-cells = <3>; 519 status = "disabled"; 520 }; 521 522 timer@8 { 523 compatible = "st,stm32-timer-trigger"; 524 reg = <8>; 525 status = "disabled"; 526 }; 527 }; 528 529 timers10: timers@40014400 { 530 compatible = "st,stm32-timers"; 531 reg = <0x40014400 0x400>; 532 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; 533 clock-names = "int"; 534 status = "disabled"; 535 536 pwm { 537 compatible = "st,stm32-pwm"; 538 #pwm-cells = <3>; 539 status = "disabled"; 540 }; 541 }; 542 543 timers11: timers@40014800 { 544 compatible = "st,stm32-timers"; 545 reg = <0x40014800 0x400>; 546 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; 547 clock-names = "int"; 548 status = "disabled"; 549 550 pwm { 551 compatible = "st,stm32-pwm"; 552 #pwm-cells = <3>; 553 status = "disabled"; 554 }; 555 }; 556 557 ltdc: display-controller@40016800 { 558 compatible = "st,stm32-ltdc"; 559 reg = <0x40016800 0x200>; 560 interrupts = <88>, <89>; 561 resets = <&rcc STM32F7_APB2_RESET(LTDC)>; 562 clocks = <&rcc 1 CLK_LCD>; 563 clock-names = "lcd"; 564 status = "disabled"; 565 }; 566 567 pwrcfg: power-config@40007000 { 568 compatible = "st,stm32-power-config", "syscon"; 569 reg = <0x40007000 0x400>; 570 }; 571 572 crc: crc@40023000 { 573 compatible = "st,stm32f7-crc"; 574 reg = <0x40023000 0x400>; 575 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>; 576 status = "disabled"; 577 }; 578 579 rcc: rcc@40023800 { 580 #reset-cells = <1>; 581 #clock-cells = <2>; 582 compatible = "st,stm32f746-rcc", "st,stm32-rcc"; 583 reg = <0x40023800 0x400>; 584 clocks = <&clk_hse>, <&clk_i2s_ckin>; 585 st,syscfg = <&pwrcfg>; 586 assigned-clocks = <&rcc 1 CLK_HSE_RTC>; 587 assigned-clock-rates = <1000000>; 588 }; 589 590 dma1: dma-controller@40026000 { 591 compatible = "st,stm32-dma"; 592 reg = <0x40026000 0x400>; 593 interrupts = <11>, 594 <12>, 595 <13>, 596 <14>, 597 <15>, 598 <16>, 599 <17>, 600 <47>; 601 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>; 602 #dma-cells = <4>; 603 status = "disabled"; 604 }; 605 606 dma2: dma-controller@40026400 { 607 compatible = "st,stm32-dma"; 608 reg = <0x40026400 0x400>; 609 interrupts = <56>, 610 <57>, 611 <58>, 612 <59>, 613 <60>, 614 <68>, 615 <69>, 616 <70>; 617 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>; 618 #dma-cells = <4>; 619 st,mem2mem; 620 status = "disabled"; 621 }; 622 623 usbotg_hs: usb@40040000 { 624 compatible = "st,stm32f7-hsotg"; 625 reg = <0x40040000 0x40000>; 626 interrupts = <77>; 627 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; 628 clock-names = "otg"; 629 g-rx-fifo-size = <256>; 630 g-np-tx-fifo-size = <32>; 631 g-tx-fifo-size = <128 128 64 64 64 64 32 32>; 632 status = "disabled"; 633 }; 634 635 usbotg_fs: usb@50000000 { 636 compatible = "st,stm32f4x9-fsotg"; 637 reg = <0x50000000 0x40000>; 638 interrupts = <67>; 639 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>; 640 clock-names = "otg"; 641 status = "disabled"; 642 }; 643 }; 644}; 645 646&systick { 647 clocks = <&rcc 1 0>; 648 status = "okay"; 649}; 650