1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/pinctrl/rockchip.h>
7#include <arm64/rockchip/rockchip-pinconf.dtsi>
8
9/*
10 * This file is auto generated by pin2dts tool, please keep these code
11 * by adding changes at end of this file.
12 */
13&pinctrl {
14	clk_out_ethernet {
15		/omit-if-no-ref/
16		clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
17			rockchip,pins =
18				/* clk_out_ethernet_m1 */
19				<2 RK_PC5 2 &pcfg_pull_none>;
20		};
21	};
22	emmc {
23		/omit-if-no-ref/
24		emmc_rstnout: emmc-rstnout {
25			rockchip,pins =
26				/* emmc_rstn */
27				<1 RK_PA3 2 &pcfg_pull_none>;
28		};
29		/omit-if-no-ref/
30		emmc_bus8: emmc-bus8 {
31			rockchip,pins =
32				/* emmc_d0 */
33				<0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
34				/* emmc_d1 */
35				<0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
36				/* emmc_d2 */
37				<0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
38				/* emmc_d3 */
39				<0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
40				/* emmc_d4 */
41				<0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
42				/* emmc_d5 */
43				<0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
44				/* emmc_d6 */
45				<0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
46				/* emmc_d7 */
47				<0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
48		};
49		/omit-if-no-ref/
50		emmc_clk: emmc-clk {
51			rockchip,pins =
52				/* emmc_clko */
53				<0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
54		};
55		/omit-if-no-ref/
56		emmc_cmd: emmc-cmd {
57			rockchip,pins =
58				/* emmc_cmd */
59				<0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
60		};
61	};
62	fspi {
63		/omit-if-no-ref/
64		fspi_pins: fspi-pins {
65			rockchip,pins =
66				/* fspi_clk */
67				<1 RK_PA3 3 &pcfg_pull_down>,
68				/* fspi_cs0n */
69				<0 RK_PD4 3 &pcfg_pull_up>,
70				/* fspi_d0 */
71				<1 RK_PA0 3 &pcfg_pull_up>,
72				/* fspi_d1 */
73				<1 RK_PA1 3 &pcfg_pull_up>,
74				/* fspi_d2 */
75				<0 RK_PD6 3 &pcfg_pull_up>,
76				/* fspi_d3 */
77				<1 RK_PA2 3 &pcfg_pull_up>;
78		};
79	};
80	i2c0 {
81		/omit-if-no-ref/
82		i2c0_xfer: i2c0-xfer {
83			rockchip,pins =
84				/* i2c0_scl */
85				<0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
86				/* i2c0_sda */
87				<0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
88		};
89	};
90	rgmii {
91		/omit-if-no-ref/
92		rgmiim1_pins: rgmiim1-pins {
93			rockchip,pins =
94				/* rgmii_mdc_m1 */
95				<2 RK_PC2 2 &pcfg_pull_none>,
96				/* rgmii_mdio_m1 */
97				<2 RK_PC1 2 &pcfg_pull_none>,
98				/* rgmii_rxclk_m1 */
99				<2 RK_PD3 2 &pcfg_pull_none>,
100				/* rgmii_rxd0_m1 */
101				<2 RK_PB5 2 &pcfg_pull_none>,
102				/* rgmii_rxd1_m1 */
103				<2 RK_PB6 2 &pcfg_pull_none>,
104				/* rgmii_rxd2_m1 */
105				<2 RK_PC7 2 &pcfg_pull_none>,
106				/* rgmii_rxd3_m1 */
107				<2 RK_PD0 2 &pcfg_pull_none>,
108				/* rgmii_rxdv_m1 */
109				<2 RK_PB4 2 &pcfg_pull_none>,
110				/* rgmii_txclk_m1 */
111				<2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
112				/* rgmii_txd0_m1 */
113				<2 RK_PC3 2 &pcfg_pull_none_drv_level_3>,
114				/* rgmii_txd1_m1 */
115				<2 RK_PC4 2 &pcfg_pull_none_drv_level_3>,
116				/* rgmii_txd2_m1 */
117				<2 RK_PD1 2 &pcfg_pull_none_drv_level_3>,
118				/* rgmii_txd3_m1 */
119				<2 RK_PA4 2 &pcfg_pull_none_drv_level_3>,
120				/* rgmii_txen_m1 */
121				<2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
122		};
123	};
124	sdmmc0 {
125		/omit-if-no-ref/
126		sdmmc0_bus4: sdmmc0-bus4 {
127			rockchip,pins =
128				/* sdmmc0_d0 */
129				<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
130				/* sdmmc0_d1 */
131				<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
132				/* sdmmc0_d2 */
133				<1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
134				/* sdmmc0_d3 */
135				<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
136		};
137		/omit-if-no-ref/
138		sdmmc0_clk: sdmmc0-clk {
139			rockchip,pins =
140				/* sdmmc0_clk */
141				<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
142		};
143		/omit-if-no-ref/
144		sdmmc0_cmd: sdmmc0-cmd {
145			rockchip,pins =
146				/* sdmmc0_cmd */
147				<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
148		};
149		/omit-if-no-ref/
150		sdmmc0_det: sdmmc0-det {
151			rockchip,pins =
152				<0 RK_PA3 1 &pcfg_pull_none>;
153		};
154		/omit-if-no-ref/
155		sdmmc0_pwr: sdmmc0-pwr {
156			rockchip,pins =
157				<0 RK_PC0 1 &pcfg_pull_none>;
158		};
159	};
160	sdmmc1 {
161		/omit-if-no-ref/
162		sdmmc1_bus4: sdmmc1-bus4 {
163			rockchip,pins =
164				/* sdmmc1_d0 */
165				<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
166				/* sdmmc1_d1 */
167				<1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
168				/* sdmmc1_d2 */
169				<1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
170				/* sdmmc1_d3 */
171				<1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
172		};
173		/omit-if-no-ref/
174		sdmmc1_clk: sdmmc1-clk {
175			rockchip,pins =
176				/* sdmmc1_clk */
177				<1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
178		};
179		/omit-if-no-ref/
180		sdmmc1_cmd: sdmmc1-cmd {
181			rockchip,pins =
182				/* sdmmc1_cmd */
183				<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
184		};
185		/omit-if-no-ref/
186		sdmmc1_det: sdmmc1-det {
187			rockchip,pins =
188				<1 RK_PD0 2 &pcfg_pull_none>;
189		};
190		/omit-if-no-ref/
191		sdmmc1_pwr: sdmmc1-pwr {
192			rockchip,pins =
193				<1 RK_PD1 2 &pcfg_pull_none>;
194		};
195	};
196	uart0 {
197		/omit-if-no-ref/
198		uart0_xfer: uart0-xfer {
199			rockchip,pins =
200				/* uart0_rx */
201				<1 RK_PC2 1 &pcfg_pull_up>,
202				/* uart0_tx */
203				<1 RK_PC3 1 &pcfg_pull_up>;
204		};
205		/omit-if-no-ref/
206		uart0_ctsn: uart0-ctsn {
207			rockchip,pins =
208				<1 RK_PC1 1 &pcfg_pull_none>;
209		};
210		/omit-if-no-ref/
211		uart0_rtsn: uart0-rtsn {
212			rockchip,pins =
213				<1 RK_PC0 1 &pcfg_pull_none>;
214		};
215		/omit-if-no-ref/
216		uart0_rtsn_gpio: uart0-rts-pin {
217			rockchip,pins =
218				<1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
219		};
220	};
221	uart1 {
222		/omit-if-no-ref/
223		uart1m0_xfer: uart1m0-xfer {
224			rockchip,pins =
225				/* uart1_rx_m0 */
226				<0 RK_PB7 2 &pcfg_pull_up>,
227				/* uart1_tx_m0 */
228				<0 RK_PB6 2 &pcfg_pull_up>;
229		};
230	};
231	uart2 {
232		/omit-if-no-ref/
233		uart2m1_xfer: uart2m1-xfer {
234			rockchip,pins =
235				/* uart2_rx_m1 */
236				<3 RK_PA3 1 &pcfg_pull_up>,
237				/* uart2_tx_m1 */
238				<3 RK_PA2 1 &pcfg_pull_up>;
239		};
240	};
241	uart3 {
242		/omit-if-no-ref/
243		uart3m0_xfer: uart3m0-xfer {
244			rockchip,pins =
245				/* uart3_rx_m0 */
246				<3 RK_PC7 4 &pcfg_pull_up>,
247				/* uart3_tx_m0 */
248				<3 RK_PC6 4 &pcfg_pull_up>;
249		};
250	};
251	uart4 {
252		/omit-if-no-ref/
253		uart4m0_xfer: uart4m0-xfer {
254			rockchip,pins =
255				/* uart4_rx_m0 */
256				<3 RK_PA5 4 &pcfg_pull_up>,
257				/* uart4_tx_m0 */
258				<3 RK_PA4 4 &pcfg_pull_up>;
259		};
260	};
261	uart5 {
262		/omit-if-no-ref/
263		uart5m0_xfer: uart5m0-xfer {
264			rockchip,pins =
265				/* uart5_rx_m0 */
266				<3 RK_PA7 4 &pcfg_pull_up>,
267				/* uart5_tx_m0 */
268				<3 RK_PA6 4 &pcfg_pull_up>;
269		};
270		/omit-if-no-ref/
271		uart5m2_xfer: uart5m2-xfer {
272			rockchip,pins =
273				/* uart5_rx_m2 */
274				<2 RK_PA1 3 &pcfg_pull_up>,
275				/* uart5_tx_m2 */
276				<2 RK_PA0 3 &pcfg_pull_up>;
277		};
278	};
279};
280