1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3288-cru.h> 8#include <dt-bindings/power/rk3288-power.h> 9#include <dt-bindings/thermal/thermal.h> 10#include <dt-bindings/soc/rockchip,boot-mode.h> 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 compatible = "rockchip,rk3288"; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 ethernet0 = &gmac; 22 i2c0 = &i2c0; 23 i2c1 = &i2c1; 24 i2c2 = &i2c2; 25 i2c3 = &i2c3; 26 i2c4 = &i2c4; 27 i2c5 = &i2c5; 28 mshc0 = &emmc; 29 mshc1 = &sdmmc; 30 mshc2 = &sdio0; 31 mshc3 = &sdio1; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 spi0 = &spi0; 38 spi1 = &spi1; 39 spi2 = &spi2; 40 }; 41 42 arm-pmu { 43 compatible = "arm,cortex-a12-pmu"; 44 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 48 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 enable-method = "rockchip,rk3066-smp"; 55 rockchip,pmu = <&pmu>; 56 57 cpu0: cpu@500 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a12"; 60 reg = <0x500>; 61 resets = <&cru SRST_CORE0>; 62 operating-points-v2 = <&cpu_opp_table>; 63 #cooling-cells = <2>; /* min followed by max */ 64 clock-latency = <40000>; 65 clocks = <&cru ARMCLK>; 66 dynamic-power-coefficient = <370>; 67 }; 68 cpu1: cpu@501 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a12"; 71 reg = <0x501>; 72 resets = <&cru SRST_CORE1>; 73 operating-points-v2 = <&cpu_opp_table>; 74 #cooling-cells = <2>; /* min followed by max */ 75 clock-latency = <40000>; 76 clocks = <&cru ARMCLK>; 77 dynamic-power-coefficient = <370>; 78 }; 79 cpu2: cpu@502 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a12"; 82 reg = <0x502>; 83 resets = <&cru SRST_CORE2>; 84 operating-points-v2 = <&cpu_opp_table>; 85 #cooling-cells = <2>; /* min followed by max */ 86 clock-latency = <40000>; 87 clocks = <&cru ARMCLK>; 88 dynamic-power-coefficient = <370>; 89 }; 90 cpu3: cpu@503 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a12"; 93 reg = <0x503>; 94 resets = <&cru SRST_CORE3>; 95 operating-points-v2 = <&cpu_opp_table>; 96 #cooling-cells = <2>; /* min followed by max */ 97 clock-latency = <40000>; 98 clocks = <&cru ARMCLK>; 99 dynamic-power-coefficient = <370>; 100 }; 101 }; 102 103 cpu_opp_table: opp-table-0 { 104 compatible = "operating-points-v2"; 105 opp-shared; 106 107 opp-126000000 { 108 opp-hz = /bits/ 64 <126000000>; 109 opp-microvolt = <900000>; 110 }; 111 opp-216000000 { 112 opp-hz = /bits/ 64 <216000000>; 113 opp-microvolt = <900000>; 114 }; 115 opp-312000000 { 116 opp-hz = /bits/ 64 <312000000>; 117 opp-microvolt = <900000>; 118 }; 119 opp-408000000 { 120 opp-hz = /bits/ 64 <408000000>; 121 opp-microvolt = <900000>; 122 }; 123 opp-600000000 { 124 opp-hz = /bits/ 64 <600000000>; 125 opp-microvolt = <900000>; 126 }; 127 opp-696000000 { 128 opp-hz = /bits/ 64 <696000000>; 129 opp-microvolt = <950000>; 130 }; 131 opp-816000000 { 132 opp-hz = /bits/ 64 <816000000>; 133 opp-microvolt = <1000000>; 134 }; 135 opp-1008000000 { 136 opp-hz = /bits/ 64 <1008000000>; 137 opp-microvolt = <1050000>; 138 }; 139 opp-1200000000 { 140 opp-hz = /bits/ 64 <1200000000>; 141 opp-microvolt = <1100000>; 142 }; 143 opp-1416000000 { 144 opp-hz = /bits/ 64 <1416000000>; 145 opp-microvolt = <1200000>; 146 }; 147 opp-1512000000 { 148 opp-hz = /bits/ 64 <1512000000>; 149 opp-microvolt = <1300000>; 150 }; 151 opp-1608000000 { 152 opp-hz = /bits/ 64 <1608000000>; 153 opp-microvolt = <1350000>; 154 }; 155 }; 156 157 reserved-memory { 158 #address-cells = <2>; 159 #size-cells = <2>; 160 ranges; 161 162 /* 163 * The rk3288 cannot use the memory area above 0xfe000000 164 * for dma operations for some reason. While there is 165 * probably a better solution available somewhere, we 166 * haven't found it yet and while devices with 2GB of ram 167 * are not affected, this issue prevents 4GB from booting. 168 * So to make these devices at least bootable, block 169 * this area for the time being until the real solution 170 * is found. 171 */ 172 dma-unusable@fe000000 { 173 reg = <0x0 0xfe000000 0x0 0x1000000>; 174 }; 175 }; 176 177 xin24m: oscillator { 178 compatible = "fixed-clock"; 179 clock-frequency = <24000000>; 180 clock-output-names = "xin24m"; 181 #clock-cells = <0>; 182 }; 183 184 timer { 185 compatible = "arm,armv7-timer"; 186 arm,cpu-registers-not-fw-configured; 187 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 188 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 189 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 190 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 191 clock-frequency = <24000000>; 192 arm,no-tick-in-suspend; 193 }; 194 195 timer: timer@ff810000 { 196 compatible = "rockchip,rk3288-timer"; 197 reg = <0x0 0xff810000 0x0 0x20>; 198 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&cru PCLK_TIMER>, <&xin24m>; 200 clock-names = "pclk", "timer"; 201 }; 202 203 display-subsystem { 204 compatible = "rockchip,display-subsystem"; 205 ports = <&vopl_out>, <&vopb_out>; 206 }; 207 208 sdmmc: mmc@ff0c0000 { 209 compatible = "rockchip,rk3288-dw-mshc"; 210 max-frequency = <150000000>; 211 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 212 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 214 fifo-depth = <0x100>; 215 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 216 reg = <0x0 0xff0c0000 0x0 0x4000>; 217 resets = <&cru SRST_MMC0>; 218 reset-names = "reset"; 219 status = "disabled"; 220 }; 221 222 sdio0: mmc@ff0d0000 { 223 compatible = "rockchip,rk3288-dw-mshc"; 224 max-frequency = <150000000>; 225 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 226 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 227 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 228 fifo-depth = <0x100>; 229 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 230 reg = <0x0 0xff0d0000 0x0 0x4000>; 231 resets = <&cru SRST_SDIO0>; 232 reset-names = "reset"; 233 status = "disabled"; 234 }; 235 236 sdio1: mmc@ff0e0000 { 237 compatible = "rockchip,rk3288-dw-mshc"; 238 max-frequency = <150000000>; 239 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 240 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 241 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 242 fifo-depth = <0x100>; 243 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 244 reg = <0x0 0xff0e0000 0x0 0x4000>; 245 resets = <&cru SRST_SDIO1>; 246 reset-names = "reset"; 247 status = "disabled"; 248 }; 249 250 emmc: mmc@ff0f0000 { 251 compatible = "rockchip,rk3288-dw-mshc"; 252 max-frequency = <150000000>; 253 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 254 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 255 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 256 fifo-depth = <0x100>; 257 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 258 reg = <0x0 0xff0f0000 0x0 0x4000>; 259 resets = <&cru SRST_EMMC>; 260 reset-names = "reset"; 261 status = "disabled"; 262 }; 263 264 saradc: saradc@ff100000 { 265 compatible = "rockchip,saradc"; 266 reg = <0x0 0xff100000 0x0 0x100>; 267 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 268 #io-channel-cells = <1>; 269 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 270 clock-names = "saradc", "apb_pclk"; 271 resets = <&cru SRST_SARADC>; 272 reset-names = "saradc-apb"; 273 status = "disabled"; 274 }; 275 276 spi0: spi@ff110000 { 277 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 278 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 279 clock-names = "spiclk", "apb_pclk"; 280 dmas = <&dmac_peri 11>, <&dmac_peri 12>; 281 dma-names = "tx", "rx"; 282 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 285 reg = <0x0 0xff110000 0x0 0x1000>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 status = "disabled"; 289 }; 290 291 spi1: spi@ff120000 { 292 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 293 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 294 clock-names = "spiclk", "apb_pclk"; 295 dmas = <&dmac_peri 13>, <&dmac_peri 14>; 296 dma-names = "tx", "rx"; 297 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 300 reg = <0x0 0xff120000 0x0 0x1000>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 status = "disabled"; 304 }; 305 306 spi2: spi@ff130000 { 307 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 308 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 309 clock-names = "spiclk", "apb_pclk"; 310 dmas = <&dmac_peri 15>, <&dmac_peri 16>; 311 dma-names = "tx", "rx"; 312 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 315 reg = <0x0 0xff130000 0x0 0x1000>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 status = "disabled"; 319 }; 320 321 i2c1: i2c@ff140000 { 322 compatible = "rockchip,rk3288-i2c"; 323 reg = <0x0 0xff140000 0x0 0x1000>; 324 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 clock-names = "i2c"; 328 clocks = <&cru PCLK_I2C1>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&i2c1_xfer>; 331 status = "disabled"; 332 }; 333 334 i2c3: i2c@ff150000 { 335 compatible = "rockchip,rk3288-i2c"; 336 reg = <0x0 0xff150000 0x0 0x1000>; 337 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 clock-names = "i2c"; 341 clocks = <&cru PCLK_I2C3>; 342 pinctrl-names = "default"; 343 pinctrl-0 = <&i2c3_xfer>; 344 status = "disabled"; 345 }; 346 347 i2c4: i2c@ff160000 { 348 compatible = "rockchip,rk3288-i2c"; 349 reg = <0x0 0xff160000 0x0 0x1000>; 350 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 clock-names = "i2c"; 354 clocks = <&cru PCLK_I2C4>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&i2c4_xfer>; 357 status = "disabled"; 358 }; 359 360 i2c5: i2c@ff170000 { 361 compatible = "rockchip,rk3288-i2c"; 362 reg = <0x0 0xff170000 0x0 0x1000>; 363 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 clock-names = "i2c"; 367 clocks = <&cru PCLK_I2C5>; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&i2c5_xfer>; 370 status = "disabled"; 371 }; 372 373 uart0: serial@ff180000 { 374 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 375 reg = <0x0 0xff180000 0x0 0x100>; 376 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 377 reg-shift = <2>; 378 reg-io-width = <4>; 379 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 380 clock-names = "baudclk", "apb_pclk"; 381 dmas = <&dmac_peri 1>, <&dmac_peri 2>; 382 dma-names = "tx", "rx"; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&uart0_xfer>; 385 status = "disabled"; 386 }; 387 388 uart1: serial@ff190000 { 389 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 390 reg = <0x0 0xff190000 0x0 0x100>; 391 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 392 reg-shift = <2>; 393 reg-io-width = <4>; 394 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 395 clock-names = "baudclk", "apb_pclk"; 396 dmas = <&dmac_peri 3>, <&dmac_peri 4>; 397 dma-names = "tx", "rx"; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&uart1_xfer>; 400 status = "disabled"; 401 }; 402 403 uart2: serial@ff690000 { 404 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 405 reg = <0x0 0xff690000 0x0 0x100>; 406 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 407 reg-shift = <2>; 408 reg-io-width = <4>; 409 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 410 clock-names = "baudclk", "apb_pclk"; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&uart2_xfer>; 413 status = "disabled"; 414 }; 415 416 uart3: serial@ff1b0000 { 417 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 418 reg = <0x0 0xff1b0000 0x0 0x100>; 419 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 420 reg-shift = <2>; 421 reg-io-width = <4>; 422 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 423 clock-names = "baudclk", "apb_pclk"; 424 dmas = <&dmac_peri 7>, <&dmac_peri 8>; 425 dma-names = "tx", "rx"; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&uart3_xfer>; 428 status = "disabled"; 429 }; 430 431 uart4: serial@ff1c0000 { 432 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 433 reg = <0x0 0xff1c0000 0x0 0x100>; 434 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 435 reg-shift = <2>; 436 reg-io-width = <4>; 437 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 438 clock-names = "baudclk", "apb_pclk"; 439 dmas = <&dmac_peri 9>, <&dmac_peri 10>; 440 dma-names = "tx", "rx"; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&uart4_xfer>; 443 status = "disabled"; 444 }; 445 446 dmac_peri: dma-controller@ff250000 { 447 compatible = "arm,pl330", "arm,primecell"; 448 reg = <0x0 0xff250000 0x0 0x4000>; 449 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 451 #dma-cells = <1>; 452 arm,pl330-broken-no-flushp; 453 arm,pl330-periph-burst; 454 clocks = <&cru ACLK_DMAC2>; 455 clock-names = "apb_pclk"; 456 }; 457 458 thermal-zones { 459 reserve_thermal: reserve-thermal { 460 polling-delay-passive = <1000>; /* milliseconds */ 461 polling-delay = <5000>; /* milliseconds */ 462 463 thermal-sensors = <&tsadc 0>; 464 }; 465 466 cpu_thermal: cpu-thermal { 467 polling-delay-passive = <100>; /* milliseconds */ 468 polling-delay = <5000>; /* milliseconds */ 469 470 thermal-sensors = <&tsadc 1>; 471 472 trips { 473 cpu_alert0: cpu_alert0 { 474 temperature = <70000>; /* millicelsius */ 475 hysteresis = <2000>; /* millicelsius */ 476 type = "passive"; 477 }; 478 cpu_alert1: cpu_alert1 { 479 temperature = <75000>; /* millicelsius */ 480 hysteresis = <2000>; /* millicelsius */ 481 type = "passive"; 482 }; 483 cpu_crit: cpu_crit { 484 temperature = <90000>; /* millicelsius */ 485 hysteresis = <2000>; /* millicelsius */ 486 type = "critical"; 487 }; 488 }; 489 490 cooling-maps { 491 map0 { 492 trip = <&cpu_alert0>; 493 cooling-device = 494 <&cpu0 THERMAL_NO_LIMIT 6>, 495 <&cpu1 THERMAL_NO_LIMIT 6>, 496 <&cpu2 THERMAL_NO_LIMIT 6>, 497 <&cpu3 THERMAL_NO_LIMIT 6>; 498 }; 499 map1 { 500 trip = <&cpu_alert1>; 501 cooling-device = 502 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 503 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 504 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 505 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 506 }; 507 }; 508 }; 509 510 gpu_thermal: gpu-thermal { 511 polling-delay-passive = <100>; /* milliseconds */ 512 polling-delay = <5000>; /* milliseconds */ 513 514 thermal-sensors = <&tsadc 2>; 515 516 trips { 517 gpu_alert0: gpu_alert0 { 518 temperature = <70000>; /* millicelsius */ 519 hysteresis = <2000>; /* millicelsius */ 520 type = "passive"; 521 }; 522 gpu_crit: gpu_crit { 523 temperature = <90000>; /* millicelsius */ 524 hysteresis = <2000>; /* millicelsius */ 525 type = "critical"; 526 }; 527 }; 528 529 cooling-maps { 530 map0 { 531 trip = <&gpu_alert0>; 532 cooling-device = 533 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 534 }; 535 }; 536 }; 537 }; 538 539 tsadc: tsadc@ff280000 { 540 compatible = "rockchip,rk3288-tsadc"; 541 reg = <0x0 0xff280000 0x0 0x100>; 542 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 544 clock-names = "tsadc", "apb_pclk"; 545 resets = <&cru SRST_TSADC>; 546 reset-names = "tsadc-apb"; 547 pinctrl-names = "init", "default", "sleep"; 548 pinctrl-0 = <&otp_pin>; 549 pinctrl-1 = <&otp_out>; 550 pinctrl-2 = <&otp_pin>; 551 #thermal-sensor-cells = <1>; 552 rockchip,grf = <&grf>; 553 rockchip,hw-tshut-temp = <95000>; 554 status = "disabled"; 555 }; 556 557 gmac: ethernet@ff290000 { 558 compatible = "rockchip,rk3288-gmac"; 559 reg = <0x0 0xff290000 0x0 0x10000>; 560 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 562 interrupt-names = "macirq", "eth_wake_irq"; 563 rockchip,grf = <&grf>; 564 clocks = <&cru SCLK_MAC>, 565 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 566 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 567 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 568 clock-names = "stmmaceth", 569 "mac_clk_rx", "mac_clk_tx", 570 "clk_mac_ref", "clk_mac_refout", 571 "aclk_mac", "pclk_mac"; 572 resets = <&cru SRST_MAC>; 573 reset-names = "stmmaceth"; 574 status = "disabled"; 575 }; 576 577 usb_host0_ehci: usb@ff500000 { 578 compatible = "generic-ehci"; 579 reg = <0x0 0xff500000 0x0 0x100>; 580 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&cru HCLK_USBHOST0>; 582 phys = <&usbphy1>; 583 phy-names = "usb"; 584 status = "disabled"; 585 }; 586 587 /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */ 588 usb_host0_ohci: usb@ff520000 { 589 compatible = "generic-ohci"; 590 reg = <0x0 0xff520000 0x0 0x100>; 591 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&cru HCLK_USBHOST0>; 593 phys = <&usbphy1>; 594 phy-names = "usb"; 595 status = "disabled"; 596 }; 597 598 usb_host1: usb@ff540000 { 599 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 600 "snps,dwc2"; 601 reg = <0x0 0xff540000 0x0 0x40000>; 602 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&cru HCLK_USBHOST1>; 604 clock-names = "otg"; 605 dr_mode = "host"; 606 phys = <&usbphy2>; 607 phy-names = "usb2-phy"; 608 snps,reset-phy-on-wake; 609 status = "disabled"; 610 }; 611 612 usb_otg: usb@ff580000 { 613 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 614 "snps,dwc2"; 615 reg = <0x0 0xff580000 0x0 0x40000>; 616 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&cru HCLK_OTG0>; 618 clock-names = "otg"; 619 dr_mode = "otg"; 620 g-np-tx-fifo-size = <16>; 621 g-rx-fifo-size = <275>; 622 g-tx-fifo-size = <256 128 128 64 64 32>; 623 phys = <&usbphy0>; 624 phy-names = "usb2-phy"; 625 status = "disabled"; 626 }; 627 628 usb_hsic: usb@ff5c0000 { 629 compatible = "generic-ehci"; 630 reg = <0x0 0xff5c0000 0x0 0x100>; 631 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&cru HCLK_HSIC>; 633 status = "disabled"; 634 }; 635 636 dmac_bus_ns: dma-controller@ff600000 { 637 compatible = "arm,pl330", "arm,primecell"; 638 reg = <0x0 0xff600000 0x0 0x4000>; 639 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 641 #dma-cells = <1>; 642 arm,pl330-broken-no-flushp; 643 arm,pl330-periph-burst; 644 clocks = <&cru ACLK_DMAC1>; 645 clock-names = "apb_pclk"; 646 status = "disabled"; 647 }; 648 649 i2c0: i2c@ff650000 { 650 compatible = "rockchip,rk3288-i2c"; 651 reg = <0x0 0xff650000 0x0 0x1000>; 652 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 clock-names = "i2c"; 656 clocks = <&cru PCLK_I2C0>; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&i2c0_xfer>; 659 status = "disabled"; 660 }; 661 662 i2c2: i2c@ff660000 { 663 compatible = "rockchip,rk3288-i2c"; 664 reg = <0x0 0xff660000 0x0 0x1000>; 665 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 clock-names = "i2c"; 669 clocks = <&cru PCLK_I2C2>; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&i2c2_xfer>; 672 status = "disabled"; 673 }; 674 675 pwm0: pwm@ff680000 { 676 compatible = "rockchip,rk3288-pwm"; 677 reg = <0x0 0xff680000 0x0 0x10>; 678 #pwm-cells = <3>; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&pwm0_pin>; 681 clocks = <&cru PCLK_RKPWM>; 682 status = "disabled"; 683 }; 684 685 pwm1: pwm@ff680010 { 686 compatible = "rockchip,rk3288-pwm"; 687 reg = <0x0 0xff680010 0x0 0x10>; 688 #pwm-cells = <3>; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&pwm1_pin>; 691 clocks = <&cru PCLK_RKPWM>; 692 status = "disabled"; 693 }; 694 695 pwm2: pwm@ff680020 { 696 compatible = "rockchip,rk3288-pwm"; 697 reg = <0x0 0xff680020 0x0 0x10>; 698 #pwm-cells = <3>; 699 pinctrl-names = "default"; 700 pinctrl-0 = <&pwm2_pin>; 701 clocks = <&cru PCLK_RKPWM>; 702 status = "disabled"; 703 }; 704 705 pwm3: pwm@ff680030 { 706 compatible = "rockchip,rk3288-pwm"; 707 reg = <0x0 0xff680030 0x0 0x10>; 708 #pwm-cells = <3>; 709 pinctrl-names = "default"; 710 pinctrl-0 = <&pwm3_pin>; 711 clocks = <&cru PCLK_RKPWM>; 712 status = "disabled"; 713 }; 714 715 bus_intmem: sram@ff700000 { 716 compatible = "mmio-sram"; 717 reg = <0x0 0xff700000 0x0 0x18000>; 718 #address-cells = <1>; 719 #size-cells = <1>; 720 ranges = <0 0x0 0xff700000 0x18000>; 721 smp-sram@0 { 722 compatible = "rockchip,rk3066-smp-sram"; 723 reg = <0x00 0x10>; 724 }; 725 }; 726 727 pmu_sram: sram@ff720000 { 728 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 729 reg = <0x0 0xff720000 0x0 0x1000>; 730 }; 731 732 pmu: power-management@ff730000 { 733 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; 734 reg = <0x0 0xff730000 0x0 0x100>; 735 736 power: power-controller { 737 compatible = "rockchip,rk3288-power-controller"; 738 #power-domain-cells = <1>; 739 #address-cells = <1>; 740 #size-cells = <0>; 741 742 assigned-clocks = <&cru SCLK_EDP_24M>; 743 assigned-clock-parents = <&xin24m>; 744 745 /* 746 * Note: Although SCLK_* are the working clocks 747 * of device without including on the NOC, needed for 748 * synchronous reset. 749 * 750 * The clocks on the which NOC: 751 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. 752 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. 753 * ACLK_RGA is on ACLK_RGA_NIU. 754 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. 755 * 756 * Which clock are device clocks: 757 * clocks devices 758 * *_IEP IEP:Image Enhancement Processor 759 * *_ISP ISP:Image Signal Processing 760 * *_VIP VIP:Video Input Processor 761 * *_VOP* VOP:Visual Output Processor 762 * *_RGA RGA 763 * *_EDP* EDP 764 * *_LVDS_* LVDS 765 * *_HDMI HDMI 766 * *_MIPI_* MIPI 767 */ 768 power-domain@RK3288_PD_VIO { 769 reg = <RK3288_PD_VIO>; 770 clocks = <&cru ACLK_IEP>, 771 <&cru ACLK_ISP>, 772 <&cru ACLK_RGA>, 773 <&cru ACLK_VIP>, 774 <&cru ACLK_VOP0>, 775 <&cru ACLK_VOP1>, 776 <&cru DCLK_VOP0>, 777 <&cru DCLK_VOP1>, 778 <&cru HCLK_IEP>, 779 <&cru HCLK_ISP>, 780 <&cru HCLK_RGA>, 781 <&cru HCLK_VIP>, 782 <&cru HCLK_VOP0>, 783 <&cru HCLK_VOP1>, 784 <&cru PCLK_EDP_CTRL>, 785 <&cru PCLK_HDMI_CTRL>, 786 <&cru PCLK_LVDS_PHY>, 787 <&cru PCLK_MIPI_CSI>, 788 <&cru PCLK_MIPI_DSI0>, 789 <&cru PCLK_MIPI_DSI1>, 790 <&cru SCLK_EDP_24M>, 791 <&cru SCLK_EDP>, 792 <&cru SCLK_ISP_JPE>, 793 <&cru SCLK_ISP>, 794 <&cru SCLK_RGA>; 795 pm_qos = <&qos_vio0_iep>, 796 <&qos_vio1_vop>, 797 <&qos_vio1_isp_w0>, 798 <&qos_vio1_isp_w1>, 799 <&qos_vio0_vop>, 800 <&qos_vio0_vip>, 801 <&qos_vio2_rga_r>, 802 <&qos_vio2_rga_w>, 803 <&qos_vio1_isp_r>; 804 #power-domain-cells = <0>; 805 }; 806 807 /* 808 * Note: The following 3 are HEVC(H.265) clocks, 809 * and on the ACLK_HEVC_NIU (NOC). 810 */ 811 power-domain@RK3288_PD_HEVC { 812 reg = <RK3288_PD_HEVC>; 813 clocks = <&cru ACLK_HEVC>, 814 <&cru SCLK_HEVC_CABAC>, 815 <&cru SCLK_HEVC_CORE>; 816 pm_qos = <&qos_hevc_r>, 817 <&qos_hevc_w>; 818 #power-domain-cells = <0>; 819 }; 820 821 /* 822 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC 823 * (video endecoder & decoder) clocks that on the 824 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). 825 */ 826 power-domain@RK3288_PD_VIDEO { 827 reg = <RK3288_PD_VIDEO>; 828 clocks = <&cru ACLK_VCODEC>, 829 <&cru HCLK_VCODEC>; 830 pm_qos = <&qos_video>; 831 #power-domain-cells = <0>; 832 }; 833 834 /* 835 * Note: ACLK_GPU is the GPU clock, 836 * and on the ACLK_GPU_NIU (NOC). 837 */ 838 power-domain@RK3288_PD_GPU { 839 reg = <RK3288_PD_GPU>; 840 clocks = <&cru ACLK_GPU>; 841 pm_qos = <&qos_gpu_r>, 842 <&qos_gpu_w>; 843 #power-domain-cells = <0>; 844 }; 845 }; 846 847 reboot-mode { 848 compatible = "syscon-reboot-mode"; 849 offset = <0x94>; 850 mode-normal = <BOOT_NORMAL>; 851 mode-recovery = <BOOT_RECOVERY>; 852 mode-bootloader = <BOOT_FASTBOOT>; 853 mode-loader = <BOOT_BL_DOWNLOAD>; 854 }; 855 }; 856 857 sgrf: syscon@ff740000 { 858 compatible = "rockchip,rk3288-sgrf", "syscon"; 859 reg = <0x0 0xff740000 0x0 0x1000>; 860 }; 861 862 cru: clock-controller@ff760000 { 863 compatible = "rockchip,rk3288-cru"; 864 reg = <0x0 0xff760000 0x0 0x1000>; 865 clocks = <&xin24m>; 866 clock-names = "xin24m"; 867 rockchip,grf = <&grf>; 868 #clock-cells = <1>; 869 #reset-cells = <1>; 870 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, 871 <&cru PLL_NPLL>, <&cru ACLK_CPU>, 872 <&cru HCLK_CPU>, <&cru PCLK_CPU>, 873 <&cru ACLK_PERI>, <&cru HCLK_PERI>, 874 <&cru PCLK_PERI>; 875 assigned-clock-rates = <594000000>, <400000000>, 876 <500000000>, <300000000>, 877 <150000000>, <75000000>, 878 <300000000>, <150000000>, 879 <75000000>; 880 }; 881 882 grf: syscon@ff770000 { 883 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; 884 reg = <0x0 0xff770000 0x0 0x1000>; 885 886 edp_phy: edp-phy { 887 compatible = "rockchip,rk3288-dp-phy"; 888 clocks = <&cru SCLK_EDP_24M>; 889 clock-names = "24m"; 890 #phy-cells = <0>; 891 status = "disabled"; 892 }; 893 894 io_domains: io-domains { 895 compatible = "rockchip,rk3288-io-voltage-domain"; 896 status = "disabled"; 897 }; 898 899 usbphy: usbphy { 900 compatible = "rockchip,rk3288-usb-phy"; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 status = "disabled"; 904 905 usbphy0: usb-phy@320 { 906 #phy-cells = <0>; 907 reg = <0x320>; 908 clocks = <&cru SCLK_OTGPHY0>; 909 clock-names = "phyclk"; 910 #clock-cells = <0>; 911 resets = <&cru SRST_USBOTG_PHY>; 912 reset-names = "phy-reset"; 913 }; 914 915 usbphy1: usb-phy@334 { 916 #phy-cells = <0>; 917 reg = <0x334>; 918 clocks = <&cru SCLK_OTGPHY1>; 919 clock-names = "phyclk"; 920 #clock-cells = <0>; 921 resets = <&cru SRST_USBHOST0_PHY>; 922 reset-names = "phy-reset"; 923 }; 924 925 usbphy2: usb-phy@348 { 926 #phy-cells = <0>; 927 reg = <0x348>; 928 clocks = <&cru SCLK_OTGPHY2>; 929 clock-names = "phyclk"; 930 #clock-cells = <0>; 931 resets = <&cru SRST_USBHOST1_PHY>; 932 reset-names = "phy-reset"; 933 }; 934 }; 935 }; 936 937 wdt: watchdog@ff800000 { 938 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 939 reg = <0x0 0xff800000 0x0 0x100>; 940 clocks = <&cru PCLK_WDT>; 941 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 942 status = "disabled"; 943 }; 944 945 spdif: sound@ff8b0000 { 946 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 947 reg = <0x0 0xff8b0000 0x0 0x10000>; 948 #sound-dai-cells = <0>; 949 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; 950 clock-names = "mclk", "hclk"; 951 dmas = <&dmac_bus_s 3>; 952 dma-names = "tx"; 953 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 954 pinctrl-names = "default"; 955 pinctrl-0 = <&spdif_tx>; 956 rockchip,grf = <&grf>; 957 status = "disabled"; 958 }; 959 960 i2s: i2s@ff890000 { 961 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 962 reg = <0x0 0xff890000 0x0 0x10000>; 963 #sound-dai-cells = <0>; 964 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; 966 clock-names = "i2s_clk", "i2s_hclk"; 967 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 968 dma-names = "tx", "rx"; 969 pinctrl-names = "default"; 970 pinctrl-0 = <&i2s0_bus>; 971 rockchip,playback-channels = <8>; 972 rockchip,capture-channels = <2>; 973 status = "disabled"; 974 }; 975 976 crypto: crypto@ff8a0000 { 977 compatible = "rockchip,rk3288-crypto"; 978 reg = <0x0 0xff8a0000 0x0 0x4000>; 979 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, 981 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; 982 clock-names = "aclk", "hclk", "sclk", "apb_pclk"; 983 resets = <&cru SRST_CRYPTO>; 984 reset-names = "crypto-rst"; 985 }; 986 987 iep_mmu: iommu@ff900800 { 988 compatible = "rockchip,iommu"; 989 reg = <0x0 0xff900800 0x0 0x40>; 990 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 992 clock-names = "aclk", "iface"; 993 #iommu-cells = <0>; 994 status = "disabled"; 995 }; 996 997 isp_mmu: iommu@ff914000 { 998 compatible = "rockchip,iommu"; 999 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1000 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1002 clock-names = "aclk", "iface"; 1003 #iommu-cells = <0>; 1004 rockchip,disable-mmu-reset; 1005 status = "disabled"; 1006 }; 1007 1008 rga: rga@ff920000 { 1009 compatible = "rockchip,rk3288-rga"; 1010 reg = <0x0 0xff920000 0x0 0x180>; 1011 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 1013 clock-names = "aclk", "hclk", "sclk"; 1014 power-domains = <&power RK3288_PD_VIO>; 1015 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; 1016 reset-names = "core", "axi", "ahb"; 1017 }; 1018 1019 vopb: vop@ff930000 { 1020 compatible = "rockchip,rk3288-vop"; 1021 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; 1022 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1024 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1025 power-domains = <&power RK3288_PD_VIO>; 1026 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 1027 reset-names = "axi", "ahb", "dclk"; 1028 iommus = <&vopb_mmu>; 1029 status = "disabled"; 1030 1031 vopb_out: port { 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 1035 vopb_out_hdmi: endpoint@0 { 1036 reg = <0>; 1037 remote-endpoint = <&hdmi_in_vopb>; 1038 }; 1039 1040 vopb_out_edp: endpoint@1 { 1041 reg = <1>; 1042 remote-endpoint = <&edp_in_vopb>; 1043 }; 1044 1045 vopb_out_mipi: endpoint@2 { 1046 reg = <2>; 1047 remote-endpoint = <&mipi_in_vopb>; 1048 }; 1049 1050 vopb_out_lvds: endpoint@3 { 1051 reg = <3>; 1052 remote-endpoint = <&lvds_in_vopb>; 1053 }; 1054 }; 1055 }; 1056 1057 vopb_mmu: iommu@ff930300 { 1058 compatible = "rockchip,iommu"; 1059 reg = <0x0 0xff930300 0x0 0x100>; 1060 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1061 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1062 clock-names = "aclk", "iface"; 1063 power-domains = <&power RK3288_PD_VIO>; 1064 #iommu-cells = <0>; 1065 status = "disabled"; 1066 }; 1067 1068 vopl: vop@ff940000 { 1069 compatible = "rockchip,rk3288-vop"; 1070 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; 1071 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1073 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1074 power-domains = <&power RK3288_PD_VIO>; 1075 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 1076 reset-names = "axi", "ahb", "dclk"; 1077 iommus = <&vopl_mmu>; 1078 status = "disabled"; 1079 1080 vopl_out: port { 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 1084 vopl_out_hdmi: endpoint@0 { 1085 reg = <0>; 1086 remote-endpoint = <&hdmi_in_vopl>; 1087 }; 1088 1089 vopl_out_edp: endpoint@1 { 1090 reg = <1>; 1091 remote-endpoint = <&edp_in_vopl>; 1092 }; 1093 1094 vopl_out_mipi: endpoint@2 { 1095 reg = <2>; 1096 remote-endpoint = <&mipi_in_vopl>; 1097 }; 1098 1099 vopl_out_lvds: endpoint@3 { 1100 reg = <3>; 1101 remote-endpoint = <&lvds_in_vopl>; 1102 }; 1103 }; 1104 }; 1105 1106 vopl_mmu: iommu@ff940300 { 1107 compatible = "rockchip,iommu"; 1108 reg = <0x0 0xff940300 0x0 0x100>; 1109 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1111 clock-names = "aclk", "iface"; 1112 power-domains = <&power RK3288_PD_VIO>; 1113 #iommu-cells = <0>; 1114 status = "disabled"; 1115 }; 1116 1117 mipi_dsi: dsi@ff960000 { 1118 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; 1119 reg = <0x0 0xff960000 0x0 0x4000>; 1120 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; 1122 clock-names = "ref", "pclk"; 1123 power-domains = <&power RK3288_PD_VIO>; 1124 rockchip,grf = <&grf>; 1125 status = "disabled"; 1126 1127 ports { 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 1131 mipi_in: port@0 { 1132 reg = <0>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 1136 mipi_in_vopb: endpoint@0 { 1137 reg = <0>; 1138 remote-endpoint = <&vopb_out_mipi>; 1139 }; 1140 1141 mipi_in_vopl: endpoint@1 { 1142 reg = <1>; 1143 remote-endpoint = <&vopl_out_mipi>; 1144 }; 1145 }; 1146 1147 mipi_out: port@1 { 1148 reg = <1>; 1149 }; 1150 }; 1151 }; 1152 1153 lvds: lvds@ff96c000 { 1154 compatible = "rockchip,rk3288-lvds"; 1155 reg = <0x0 0xff96c000 0x0 0x4000>; 1156 clocks = <&cru PCLK_LVDS_PHY>; 1157 clock-names = "pclk_lvds"; 1158 pinctrl-names = "lcdc"; 1159 pinctrl-0 = <&lcdc_ctl>; 1160 power-domains = <&power RK3288_PD_VIO>; 1161 rockchip,grf = <&grf>; 1162 status = "disabled"; 1163 1164 ports { 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 1168 lvds_in: port@0 { 1169 reg = <0>; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 1173 lvds_in_vopb: endpoint@0 { 1174 reg = <0>; 1175 remote-endpoint = <&vopb_out_lvds>; 1176 }; 1177 1178 lvds_in_vopl: endpoint@1 { 1179 reg = <1>; 1180 remote-endpoint = <&vopl_out_lvds>; 1181 }; 1182 }; 1183 1184 lvds_out: port@1 { 1185 reg = <1>; 1186 }; 1187 }; 1188 }; 1189 1190 edp: dp@ff970000 { 1191 compatible = "rockchip,rk3288-dp"; 1192 reg = <0x0 0xff970000 0x0 0x4000>; 1193 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1194 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; 1195 clock-names = "dp", "pclk"; 1196 phys = <&edp_phy>; 1197 phy-names = "dp"; 1198 power-domains = <&power RK3288_PD_VIO>; 1199 resets = <&cru SRST_EDP>; 1200 reset-names = "dp"; 1201 rockchip,grf = <&grf>; 1202 status = "disabled"; 1203 1204 ports { 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 1208 edp_in: port@0 { 1209 reg = <0>; 1210 #address-cells = <1>; 1211 #size-cells = <0>; 1212 1213 edp_in_vopb: endpoint@0 { 1214 reg = <0>; 1215 remote-endpoint = <&vopb_out_edp>; 1216 }; 1217 1218 edp_in_vopl: endpoint@1 { 1219 reg = <1>; 1220 remote-endpoint = <&vopl_out_edp>; 1221 }; 1222 }; 1223 1224 edp_out: port@1 { 1225 reg = <1>; 1226 }; 1227 }; 1228 }; 1229 1230 hdmi: hdmi@ff980000 { 1231 compatible = "rockchip,rk3288-dw-hdmi"; 1232 reg = <0x0 0xff980000 0x0 0x20000>; 1233 reg-io-width = <4>; 1234 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1235 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; 1236 clock-names = "iahb", "isfr", "cec"; 1237 power-domains = <&power RK3288_PD_VIO>; 1238 rockchip,grf = <&grf>; 1239 #sound-dai-cells = <0>; 1240 status = "disabled"; 1241 1242 ports { 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 1246 hdmi_in: port@0 { 1247 reg = <0>; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 1251 hdmi_in_vopb: endpoint@0 { 1252 reg = <0>; 1253 remote-endpoint = <&vopb_out_hdmi>; 1254 }; 1255 1256 hdmi_in_vopl: endpoint@1 { 1257 reg = <1>; 1258 remote-endpoint = <&vopl_out_hdmi>; 1259 }; 1260 }; 1261 1262 hdmi_out: port@1 { 1263 reg = <1>; 1264 }; 1265 }; 1266 }; 1267 1268 vpu: video-codec@ff9a0000 { 1269 compatible = "rockchip,rk3288-vpu"; 1270 reg = <0x0 0xff9a0000 0x0 0x800>; 1271 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1273 interrupt-names = "vepu", "vdpu"; 1274 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1275 clock-names = "aclk", "hclk"; 1276 iommus = <&vpu_mmu>; 1277 power-domains = <&power RK3288_PD_VIDEO>; 1278 }; 1279 1280 vpu_mmu: iommu@ff9a0800 { 1281 compatible = "rockchip,iommu"; 1282 reg = <0x0 0xff9a0800 0x0 0x100>; 1283 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1284 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1285 clock-names = "aclk", "iface"; 1286 #iommu-cells = <0>; 1287 power-domains = <&power RK3288_PD_VIDEO>; 1288 }; 1289 1290 hevc_mmu: iommu@ff9c0440 { 1291 compatible = "rockchip,iommu"; 1292 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; 1293 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1294 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; 1295 clock-names = "aclk", "iface"; 1296 #iommu-cells = <0>; 1297 status = "disabled"; 1298 }; 1299 1300 gpu: gpu@ffa30000 { 1301 compatible = "rockchip,rk3288-mali", "arm,mali-t760"; 1302 reg = <0x0 0xffa30000 0x0 0x10000>; 1303 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1306 interrupt-names = "job", "mmu", "gpu"; 1307 clocks = <&cru ACLK_GPU>; 1308 operating-points-v2 = <&gpu_opp_table>; 1309 #cooling-cells = <2>; /* min followed by max */ 1310 power-domains = <&power RK3288_PD_GPU>; 1311 status = "disabled"; 1312 }; 1313 1314 gpu_opp_table: opp-table-1 { 1315 compatible = "operating-points-v2"; 1316 1317 opp-100000000 { 1318 opp-hz = /bits/ 64 <100000000>; 1319 opp-microvolt = <950000>; 1320 }; 1321 opp-200000000 { 1322 opp-hz = /bits/ 64 <200000000>; 1323 opp-microvolt = <950000>; 1324 }; 1325 opp-300000000 { 1326 opp-hz = /bits/ 64 <300000000>; 1327 opp-microvolt = <1000000>; 1328 }; 1329 opp-400000000 { 1330 opp-hz = /bits/ 64 <400000000>; 1331 opp-microvolt = <1100000>; 1332 }; 1333 opp-600000000 { 1334 opp-hz = /bits/ 64 <600000000>; 1335 opp-microvolt = <1250000>; 1336 }; 1337 }; 1338 1339 qos_gpu_r: qos@ffaa0000 { 1340 compatible = "rockchip,rk3288-qos", "syscon"; 1341 reg = <0x0 0xffaa0000 0x0 0x20>; 1342 }; 1343 1344 qos_gpu_w: qos@ffaa0080 { 1345 compatible = "rockchip,rk3288-qos", "syscon"; 1346 reg = <0x0 0xffaa0080 0x0 0x20>; 1347 }; 1348 1349 qos_vio1_vop: qos@ffad0000 { 1350 compatible = "rockchip,rk3288-qos", "syscon"; 1351 reg = <0x0 0xffad0000 0x0 0x20>; 1352 }; 1353 1354 qos_vio1_isp_w0: qos@ffad0100 { 1355 compatible = "rockchip,rk3288-qos", "syscon"; 1356 reg = <0x0 0xffad0100 0x0 0x20>; 1357 }; 1358 1359 qos_vio1_isp_w1: qos@ffad0180 { 1360 compatible = "rockchip,rk3288-qos", "syscon"; 1361 reg = <0x0 0xffad0180 0x0 0x20>; 1362 }; 1363 1364 qos_vio0_vop: qos@ffad0400 { 1365 compatible = "rockchip,rk3288-qos", "syscon"; 1366 reg = <0x0 0xffad0400 0x0 0x20>; 1367 }; 1368 1369 qos_vio0_vip: qos@ffad0480 { 1370 compatible = "rockchip,rk3288-qos", "syscon"; 1371 reg = <0x0 0xffad0480 0x0 0x20>; 1372 }; 1373 1374 qos_vio0_iep: qos@ffad0500 { 1375 compatible = "rockchip,rk3288-qos", "syscon"; 1376 reg = <0x0 0xffad0500 0x0 0x20>; 1377 }; 1378 1379 qos_vio2_rga_r: qos@ffad0800 { 1380 compatible = "rockchip,rk3288-qos", "syscon"; 1381 reg = <0x0 0xffad0800 0x0 0x20>; 1382 }; 1383 1384 qos_vio2_rga_w: qos@ffad0880 { 1385 compatible = "rockchip,rk3288-qos", "syscon"; 1386 reg = <0x0 0xffad0880 0x0 0x20>; 1387 }; 1388 1389 qos_vio1_isp_r: qos@ffad0900 { 1390 compatible = "rockchip,rk3288-qos", "syscon"; 1391 reg = <0x0 0xffad0900 0x0 0x20>; 1392 }; 1393 1394 qos_video: qos@ffae0000 { 1395 compatible = "rockchip,rk3288-qos", "syscon"; 1396 reg = <0x0 0xffae0000 0x0 0x20>; 1397 }; 1398 1399 qos_hevc_r: qos@ffaf0000 { 1400 compatible = "rockchip,rk3288-qos", "syscon"; 1401 reg = <0x0 0xffaf0000 0x0 0x20>; 1402 }; 1403 1404 qos_hevc_w: qos@ffaf0080 { 1405 compatible = "rockchip,rk3288-qos", "syscon"; 1406 reg = <0x0 0xffaf0080 0x0 0x20>; 1407 }; 1408 1409 dmac_bus_s: dma-controller@ffb20000 { 1410 compatible = "arm,pl330", "arm,primecell"; 1411 reg = <0x0 0xffb20000 0x0 0x4000>; 1412 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1414 #dma-cells = <1>; 1415 arm,pl330-broken-no-flushp; 1416 arm,pl330-periph-burst; 1417 clocks = <&cru ACLK_DMAC1>; 1418 clock-names = "apb_pclk"; 1419 }; 1420 1421 efuse: efuse@ffb40000 { 1422 compatible = "rockchip,rk3288-efuse"; 1423 reg = <0x0 0xffb40000 0x0 0x20>; 1424 #address-cells = <1>; 1425 #size-cells = <1>; 1426 clocks = <&cru PCLK_EFUSE256>; 1427 clock-names = "pclk_efuse"; 1428 1429 cpu_id: cpu-id@7 { 1430 reg = <0x07 0x10>; 1431 }; 1432 cpu_leakage: cpu_leakage@17 { 1433 reg = <0x17 0x1>; 1434 }; 1435 }; 1436 1437 gic: interrupt-controller@ffc01000 { 1438 compatible = "arm,gic-400"; 1439 interrupt-controller; 1440 #interrupt-cells = <3>; 1441 #address-cells = <0>; 1442 1443 reg = <0x0 0xffc01000 0x0 0x1000>, 1444 <0x0 0xffc02000 0x0 0x2000>, 1445 <0x0 0xffc04000 0x0 0x2000>, 1446 <0x0 0xffc06000 0x0 0x2000>; 1447 interrupts = <GIC_PPI 9 0xf04>; 1448 }; 1449 1450 pinctrl: pinctrl { 1451 compatible = "rockchip,rk3288-pinctrl"; 1452 rockchip,grf = <&grf>; 1453 rockchip,pmu = <&pmu>; 1454 #address-cells = <2>; 1455 #size-cells = <2>; 1456 ranges; 1457 1458 gpio0: gpio@ff750000 { 1459 compatible = "rockchip,gpio-bank"; 1460 reg = <0x0 0xff750000 0x0 0x100>; 1461 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1462 clocks = <&cru PCLK_GPIO0>; 1463 1464 gpio-controller; 1465 #gpio-cells = <2>; 1466 1467 interrupt-controller; 1468 #interrupt-cells = <2>; 1469 }; 1470 1471 gpio1: gpio@ff780000 { 1472 compatible = "rockchip,gpio-bank"; 1473 reg = <0x0 0xff780000 0x0 0x100>; 1474 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1475 clocks = <&cru PCLK_GPIO1>; 1476 1477 gpio-controller; 1478 #gpio-cells = <2>; 1479 1480 interrupt-controller; 1481 #interrupt-cells = <2>; 1482 }; 1483 1484 gpio2: gpio@ff790000 { 1485 compatible = "rockchip,gpio-bank"; 1486 reg = <0x0 0xff790000 0x0 0x100>; 1487 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1488 clocks = <&cru PCLK_GPIO2>; 1489 1490 gpio-controller; 1491 #gpio-cells = <2>; 1492 1493 interrupt-controller; 1494 #interrupt-cells = <2>; 1495 }; 1496 1497 gpio3: gpio@ff7a0000 { 1498 compatible = "rockchip,gpio-bank"; 1499 reg = <0x0 0xff7a0000 0x0 0x100>; 1500 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1501 clocks = <&cru PCLK_GPIO3>; 1502 1503 gpio-controller; 1504 #gpio-cells = <2>; 1505 1506 interrupt-controller; 1507 #interrupt-cells = <2>; 1508 }; 1509 1510 gpio4: gpio@ff7b0000 { 1511 compatible = "rockchip,gpio-bank"; 1512 reg = <0x0 0xff7b0000 0x0 0x100>; 1513 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1514 clocks = <&cru PCLK_GPIO4>; 1515 1516 gpio-controller; 1517 #gpio-cells = <2>; 1518 1519 interrupt-controller; 1520 #interrupt-cells = <2>; 1521 }; 1522 1523 gpio5: gpio@ff7c0000 { 1524 compatible = "rockchip,gpio-bank"; 1525 reg = <0x0 0xff7c0000 0x0 0x100>; 1526 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1527 clocks = <&cru PCLK_GPIO5>; 1528 1529 gpio-controller; 1530 #gpio-cells = <2>; 1531 1532 interrupt-controller; 1533 #interrupt-cells = <2>; 1534 }; 1535 1536 gpio6: gpio@ff7d0000 { 1537 compatible = "rockchip,gpio-bank"; 1538 reg = <0x0 0xff7d0000 0x0 0x100>; 1539 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1540 clocks = <&cru PCLK_GPIO6>; 1541 1542 gpio-controller; 1543 #gpio-cells = <2>; 1544 1545 interrupt-controller; 1546 #interrupt-cells = <2>; 1547 }; 1548 1549 gpio7: gpio@ff7e0000 { 1550 compatible = "rockchip,gpio-bank"; 1551 reg = <0x0 0xff7e0000 0x0 0x100>; 1552 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1553 clocks = <&cru PCLK_GPIO7>; 1554 1555 gpio-controller; 1556 #gpio-cells = <2>; 1557 1558 interrupt-controller; 1559 #interrupt-cells = <2>; 1560 }; 1561 1562 gpio8: gpio@ff7f0000 { 1563 compatible = "rockchip,gpio-bank"; 1564 reg = <0x0 0xff7f0000 0x0 0x100>; 1565 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1566 clocks = <&cru PCLK_GPIO8>; 1567 1568 gpio-controller; 1569 #gpio-cells = <2>; 1570 1571 interrupt-controller; 1572 #interrupt-cells = <2>; 1573 }; 1574 1575 hdmi { 1576 hdmi_cec_c0: hdmi-cec-c0 { 1577 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; 1578 }; 1579 1580 hdmi_cec_c7: hdmi-cec-c7 { 1581 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>; 1582 }; 1583 1584 hdmi_ddc: hdmi-ddc { 1585 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, 1586 <7 RK_PC4 2 &pcfg_pull_none>; 1587 }; 1588 1589 hdmi_ddc_unwedge: hdmi-ddc-unwedge { 1590 rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>, 1591 <7 RK_PC4 2 &pcfg_pull_none>; 1592 }; 1593 }; 1594 1595 pcfg_output_low: pcfg-output-low { 1596 output-low; 1597 }; 1598 1599 pcfg_pull_up: pcfg-pull-up { 1600 bias-pull-up; 1601 }; 1602 1603 pcfg_pull_down: pcfg-pull-down { 1604 bias-pull-down; 1605 }; 1606 1607 pcfg_pull_none: pcfg-pull-none { 1608 bias-disable; 1609 }; 1610 1611 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1612 bias-disable; 1613 drive-strength = <12>; 1614 }; 1615 1616 suspend { 1617 global_pwroff: global-pwroff { 1618 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; 1619 }; 1620 1621 ddrio_pwroff: ddrio-pwroff { 1622 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 1623 }; 1624 1625 ddr0_retention: ddr0-retention { 1626 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; 1627 }; 1628 1629 ddr1_retention: ddr1-retention { 1630 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; 1631 }; 1632 }; 1633 1634 edp { 1635 edp_hpd: edp-hpd { 1636 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>; 1637 }; 1638 }; 1639 1640 i2c0 { 1641 i2c0_xfer: i2c0-xfer { 1642 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>, 1643 <0 RK_PC0 1 &pcfg_pull_none>; 1644 }; 1645 }; 1646 1647 i2c1 { 1648 i2c1_xfer: i2c1-xfer { 1649 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>, 1650 <8 RK_PA5 1 &pcfg_pull_none>; 1651 }; 1652 }; 1653 1654 i2c2 { 1655 i2c2_xfer: i2c2-xfer { 1656 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>, 1657 <6 RK_PB2 1 &pcfg_pull_none>; 1658 }; 1659 }; 1660 1661 i2c3 { 1662 i2c3_xfer: i2c3-xfer { 1663 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>, 1664 <2 RK_PC1 1 &pcfg_pull_none>; 1665 }; 1666 }; 1667 1668 i2c4 { 1669 i2c4_xfer: i2c4-xfer { 1670 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>, 1671 <7 RK_PC2 1 &pcfg_pull_none>; 1672 }; 1673 }; 1674 1675 i2c5 { 1676 i2c5_xfer: i2c5-xfer { 1677 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>, 1678 <7 RK_PC4 1 &pcfg_pull_none>; 1679 }; 1680 }; 1681 1682 i2s0 { 1683 i2s0_bus: i2s0-bus { 1684 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>, 1685 <6 RK_PA1 1 &pcfg_pull_none>, 1686 <6 RK_PA2 1 &pcfg_pull_none>, 1687 <6 RK_PA3 1 &pcfg_pull_none>, 1688 <6 RK_PA4 1 &pcfg_pull_none>, 1689 <6 RK_PB0 1 &pcfg_pull_none>; 1690 }; 1691 }; 1692 1693 lcdc { 1694 lcdc_ctl: lcdc-ctl { 1695 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 1696 <1 RK_PD1 1 &pcfg_pull_none>, 1697 <1 RK_PD2 1 &pcfg_pull_none>, 1698 <1 RK_PD3 1 &pcfg_pull_none>; 1699 }; 1700 }; 1701 1702 sdmmc { 1703 sdmmc_clk: sdmmc-clk { 1704 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>; 1705 }; 1706 1707 sdmmc_cmd: sdmmc-cmd { 1708 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; 1709 }; 1710 1711 sdmmc_cd: sdmmc-cd { 1712 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; 1713 }; 1714 1715 sdmmc_bus1: sdmmc-bus1 { 1716 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>; 1717 }; 1718 1719 sdmmc_bus4: sdmmc-bus4 { 1720 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>, 1721 <6 RK_PC1 1 &pcfg_pull_up>, 1722 <6 RK_PC2 1 &pcfg_pull_up>, 1723 <6 RK_PC3 1 &pcfg_pull_up>; 1724 }; 1725 }; 1726 1727 sdio0 { 1728 sdio0_bus1: sdio0-bus1 { 1729 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>; 1730 }; 1731 1732 sdio0_bus4: sdio0-bus4 { 1733 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>, 1734 <4 RK_PC5 1 &pcfg_pull_up>, 1735 <4 RK_PC6 1 &pcfg_pull_up>, 1736 <4 RK_PC7 1 &pcfg_pull_up>; 1737 }; 1738 1739 sdio0_cmd: sdio0-cmd { 1740 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>; 1741 }; 1742 1743 sdio0_clk: sdio0-clk { 1744 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>; 1745 }; 1746 1747 sdio0_cd: sdio0-cd { 1748 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>; 1749 }; 1750 1751 sdio0_wp: sdio0-wp { 1752 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>; 1753 }; 1754 1755 sdio0_pwr: sdio0-pwr { 1756 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>; 1757 }; 1758 1759 sdio0_bkpwr: sdio0-bkpwr { 1760 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>; 1761 }; 1762 1763 sdio0_int: sdio0-int { 1764 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>; 1765 }; 1766 }; 1767 1768 sdio1 { 1769 sdio1_bus1: sdio1-bus1 { 1770 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>; 1771 }; 1772 1773 sdio1_bus4: sdio1-bus4 { 1774 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>, 1775 <3 RK_PD1 4 &pcfg_pull_up>, 1776 <3 RK_PD2 4 &pcfg_pull_up>, 1777 <3 RK_PD3 4 &pcfg_pull_up>; 1778 }; 1779 1780 sdio1_cd: sdio1-cd { 1781 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>; 1782 }; 1783 1784 sdio1_wp: sdio1-wp { 1785 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>; 1786 }; 1787 1788 sdio1_bkpwr: sdio1-bkpwr { 1789 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>; 1790 }; 1791 1792 sdio1_int: sdio1-int { 1793 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>; 1794 }; 1795 1796 sdio1_cmd: sdio1-cmd { 1797 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>; 1798 }; 1799 1800 sdio1_clk: sdio1-clk { 1801 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>; 1802 }; 1803 1804 sdio1_pwr: sdio1-pwr { 1805 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>; 1806 }; 1807 }; 1808 1809 emmc { 1810 emmc_clk: emmc-clk { 1811 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>; 1812 }; 1813 1814 emmc_cmd: emmc-cmd { 1815 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>; 1816 }; 1817 1818 emmc_pwr: emmc-pwr { 1819 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>; 1820 }; 1821 1822 emmc_bus1: emmc-bus1 { 1823 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>; 1824 }; 1825 1826 emmc_bus4: emmc-bus4 { 1827 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, 1828 <3 RK_PA1 2 &pcfg_pull_up>, 1829 <3 RK_PA2 2 &pcfg_pull_up>, 1830 <3 RK_PA3 2 &pcfg_pull_up>; 1831 }; 1832 1833 emmc_bus8: emmc-bus8 { 1834 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, 1835 <3 RK_PA1 2 &pcfg_pull_up>, 1836 <3 RK_PA2 2 &pcfg_pull_up>, 1837 <3 RK_PA3 2 &pcfg_pull_up>, 1838 <3 RK_PA4 2 &pcfg_pull_up>, 1839 <3 RK_PA5 2 &pcfg_pull_up>, 1840 <3 RK_PA6 2 &pcfg_pull_up>, 1841 <3 RK_PA7 2 &pcfg_pull_up>; 1842 }; 1843 }; 1844 1845 spi0 { 1846 spi0_clk: spi0-clk { 1847 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>; 1848 }; 1849 spi0_cs0: spi0-cs0 { 1850 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>; 1851 }; 1852 spi0_tx: spi0-tx { 1853 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>; 1854 }; 1855 spi0_rx: spi0-rx { 1856 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>; 1857 }; 1858 spi0_cs1: spi0-cs1 { 1859 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>; 1860 }; 1861 }; 1862 spi1 { 1863 spi1_clk: spi1-clk { 1864 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>; 1865 }; 1866 spi1_cs0: spi1-cs0 { 1867 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>; 1868 }; 1869 spi1_rx: spi1-rx { 1870 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>; 1871 }; 1872 spi1_tx: spi1-tx { 1873 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>; 1874 }; 1875 }; 1876 1877 spi2 { 1878 spi2_cs1: spi2-cs1 { 1879 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>; 1880 }; 1881 spi2_clk: spi2-clk { 1882 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>; 1883 }; 1884 spi2_cs0: spi2-cs0 { 1885 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>; 1886 }; 1887 spi2_rx: spi2-rx { 1888 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>; 1889 }; 1890 spi2_tx: spi2-tx { 1891 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>; 1892 }; 1893 }; 1894 1895 uart0 { 1896 uart0_xfer: uart0-xfer { 1897 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>, 1898 <4 RK_PC1 1 &pcfg_pull_none>; 1899 }; 1900 1901 uart0_cts: uart0-cts { 1902 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>; 1903 }; 1904 1905 uart0_rts: uart0-rts { 1906 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>; 1907 }; 1908 }; 1909 1910 uart1 { 1911 uart1_xfer: uart1-xfer { 1912 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>, 1913 <5 RK_PB1 1 &pcfg_pull_none>; 1914 }; 1915 1916 uart1_cts: uart1-cts { 1917 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>; 1918 }; 1919 1920 uart1_rts: uart1-rts { 1921 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>; 1922 }; 1923 }; 1924 1925 uart2 { 1926 uart2_xfer: uart2-xfer { 1927 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>, 1928 <7 RK_PC7 1 &pcfg_pull_none>; 1929 }; 1930 /* no rts / cts for uart2 */ 1931 }; 1932 1933 uart3 { 1934 uart3_xfer: uart3-xfer { 1935 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>, 1936 <7 RK_PB0 1 &pcfg_pull_none>; 1937 }; 1938 1939 uart3_cts: uart3-cts { 1940 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>; 1941 }; 1942 1943 uart3_rts: uart3-rts { 1944 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>; 1945 }; 1946 }; 1947 1948 uart4 { 1949 uart4_xfer: uart4-xfer { 1950 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>, 1951 <5 RK_PB6 3 &pcfg_pull_none>; 1952 }; 1953 1954 uart4_cts: uart4-cts { 1955 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>; 1956 }; 1957 1958 uart4_rts: uart4-rts { 1959 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>; 1960 }; 1961 }; 1962 1963 tsadc { 1964 otp_pin: otp-pin { 1965 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1966 }; 1967 1968 otp_out: otp-out { 1969 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; 1970 }; 1971 }; 1972 1973 pwm0 { 1974 pwm0_pin: pwm0-pin { 1975 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>; 1976 }; 1977 }; 1978 1979 pwm1 { 1980 pwm1_pin: pwm1-pin { 1981 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>; 1982 }; 1983 }; 1984 1985 pwm2 { 1986 pwm2_pin: pwm2-pin { 1987 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>; 1988 }; 1989 }; 1990 1991 pwm3 { 1992 pwm3_pin: pwm3-pin { 1993 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>; 1994 }; 1995 }; 1996 1997 gmac { 1998 rgmii_pins: rgmii-pins { 1999 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, 2000 <3 RK_PD7 3 &pcfg_pull_none>, 2001 <3 RK_PD2 3 &pcfg_pull_none>, 2002 <3 RK_PD3 3 &pcfg_pull_none>, 2003 <3 RK_PD4 3 &pcfg_pull_none_12ma>, 2004 <3 RK_PD5 3 &pcfg_pull_none_12ma>, 2005 <3 RK_PD0 3 &pcfg_pull_none_12ma>, 2006 <3 RK_PD1 3 &pcfg_pull_none_12ma>, 2007 <4 RK_PA0 3 &pcfg_pull_none>, 2008 <4 RK_PA5 3 &pcfg_pull_none>, 2009 <4 RK_PA6 3 &pcfg_pull_none>, 2010 <4 RK_PB1 3 &pcfg_pull_none_12ma>, 2011 <4 RK_PA4 3 &pcfg_pull_none_12ma>, 2012 <4 RK_PA1 3 &pcfg_pull_none>, 2013 <4 RK_PA3 3 &pcfg_pull_none>; 2014 }; 2015 2016 rmii_pins: rmii-pins { 2017 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, 2018 <3 RK_PD7 3 &pcfg_pull_none>, 2019 <3 RK_PD4 3 &pcfg_pull_none>, 2020 <3 RK_PD5 3 &pcfg_pull_none>, 2021 <4 RK_PA0 3 &pcfg_pull_none>, 2022 <4 RK_PA5 3 &pcfg_pull_none>, 2023 <4 RK_PA4 3 &pcfg_pull_none>, 2024 <4 RK_PA1 3 &pcfg_pull_none>, 2025 <4 RK_PA2 3 &pcfg_pull_none>, 2026 <4 RK_PA3 3 &pcfg_pull_none>; 2027 }; 2028 }; 2029 2030 spdif { 2031 spdif_tx: spdif-tx { 2032 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>; 2033 }; 2034 }; 2035 }; 2036}; 2037