1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Google Veyron (and derivatives) board device tree source
4 *
5 * Copyright 2015 Google, Inc
6 */
7
8#include <dt-bindings/clock/rockchip,rk808.h>
9#include <dt-bindings/input/input.h>
10#include "rk3288.dtsi"
11
12/ {
13	aliases {
14		mmc0 = &emmc;
15	};
16
17	chosen {
18		stdout-path = "serial2:115200n8";
19	};
20
21	/*
22	 * The default coreboot on veyron devices ignores memory@0 nodes
23	 * and would instead create another memory node.
24	 */
25	memory {
26		device_type = "memory";
27		reg = <0x0 0x0 0x0 0x80000000>;
28	};
29
30
31	power_button: power-button {
32		compatible = "gpio-keys";
33		pinctrl-names = "default";
34		pinctrl-0 = <&pwr_key_l>;
35
36		key-power {
37			label = "Power";
38			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
39			linux,code = <KEY_POWER>;
40			debounce-interval = <100>;
41			wakeup-source;
42		};
43	};
44
45	gpio-restart {
46		compatible = "gpio-restart";
47		gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
48		pinctrl-names = "default";
49		pinctrl-0 = <&ap_warm_reset_h>;
50		priority = <200>;
51	};
52
53	emmc_pwrseq: emmc-pwrseq {
54		compatible = "mmc-pwrseq-emmc";
55		pinctrl-0 = <&emmc_reset>;
56		pinctrl-names = "default";
57		reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
58	};
59
60	sdio_pwrseq: sdio-pwrseq {
61		compatible = "mmc-pwrseq-simple";
62		clocks = <&rk808 RK808_CLKOUT1>;
63		clock-names = "ext_clock";
64		pinctrl-names = "default";
65		pinctrl-0 = <&wifi_enable_h>;
66
67		/*
68		 * Depending on the actual card populated GPIO4 D4
69		 * correspond to one of these signals on the module:
70		 *
71		 * D4:
72		 * - SDIO_RESET_L_WL_REG_ON
73		 * - PDN (power down when low)
74		 */
75		reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
76	};
77
78	vcc_5v: vcc-5v {
79		compatible = "regulator-fixed";
80		regulator-name = "vcc_5v";
81		regulator-always-on;
82		regulator-boot-on;
83		regulator-min-microvolt = <5000000>;
84		regulator-max-microvolt = <5000000>;
85	};
86
87	vcc33_sys: vcc33-sys {
88		compatible = "regulator-fixed";
89		regulator-name = "vcc33_sys";
90		regulator-always-on;
91		regulator-boot-on;
92		regulator-min-microvolt = <3300000>;
93		regulator-max-microvolt = <3300000>;
94	};
95
96	vcc50_hdmi: vcc50-hdmi {
97		compatible = "regulator-fixed";
98		regulator-name = "vcc50_hdmi";
99		regulator-always-on;
100		regulator-boot-on;
101		vin-supply = <&vcc_5v>;
102	};
103
104	vdd_logic: vdd-logic {
105		compatible = "pwm-regulator";
106		regulator-name = "vdd_logic";
107
108		pwms = <&pwm1 0 1994 0>;
109		pwm-supply = <&vcc33_sys>;
110
111		pwm-dutycycle-range = <0x7b 0>;
112		pwm-dutycycle-unit = <0x94>;
113
114		regulator-always-on;
115		regulator-boot-on;
116		regulator-min-microvolt = <950000>;
117		regulator-max-microvolt = <1350000>;
118		regulator-ramp-delay = <4000>;
119	};
120};
121
122&cpu0 {
123	cpu0-supply = <&vdd_cpu>;
124};
125
126&cpu_crit {
127	temperature = <100000>;
128};
129
130/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
131&cpu_opp_table {
132	/delete-node/ opp-312000000;
133
134	opp-1512000000 {
135		opp-microvolt = <1250000>;
136	};
137	opp-1608000000 {
138		opp-microvolt = <1300000>;
139	};
140	opp-1704000000 {
141		opp-hz = /bits/ 64 <1704000000>;
142		opp-microvolt = <1350000>;
143	};
144	opp-1800000000 {
145		opp-hz = /bits/ 64 <1800000000>;
146		opp-microvolt = <1400000>;
147	};
148};
149
150&emmc {
151	status = "okay";
152
153	bus-width = <8>;
154	cap-mmc-highspeed;
155	rockchip,default-sample-phase = <158>;
156	disable-wp;
157	mmc-hs200-1_8v;
158	mmc-pwrseq = <&emmc_pwrseq>;
159	non-removable;
160	pinctrl-names = "default";
161	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
162};
163
164&gpu {
165	mali-supply = <&vdd_gpu>;
166	status = "okay";
167};
168
169&gpu_alert0 {
170	temperature = <72500>;
171};
172
173&gpu_crit {
174	temperature = <100000>;
175};
176
177&hdmi {
178	pinctrl-names = "default", "unwedge";
179	pinctrl-0 = <&hdmi_ddc>;
180	pinctrl-1 = <&hdmi_ddc_unwedge>;
181	status = "okay";
182};
183
184&i2c0 {
185	status = "okay";
186
187	clock-frequency = <400000>;
188	i2c-scl-falling-time-ns = <50>;		/* 2.5ns measured */
189	i2c-scl-rising-time-ns = <100>;		/* 45ns measured */
190
191	rk808: pmic@1b {
192		compatible = "rockchip,rk808";
193		reg = <0x1b>;
194		clock-output-names = "xin32k", "wifibt_32kin";
195		interrupt-parent = <&gpio0>;
196		interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
197		pinctrl-names = "default";
198		pinctrl-0 = <&pmic_int_l>;
199		rockchip,system-power-controller;
200		wakeup-source;
201		#clock-cells = <1>;
202
203		vcc1-supply = <&vcc33_sys>;
204		vcc2-supply = <&vcc33_sys>;
205		vcc3-supply = <&vcc33_sys>;
206		vcc4-supply = <&vcc33_sys>;
207		vcc6-supply = <&vcc_5v>;
208		vcc7-supply = <&vcc33_sys>;
209		vcc8-supply = <&vcc33_sys>;
210		vcc12-supply = <&vcc_18>;
211		vddio-supply = <&vcc33_io>;
212
213		regulators {
214			vdd_cpu: DCDC_REG1 {
215				regulator-name = "vdd_arm";
216				regulator-always-on;
217				regulator-boot-on;
218				regulator-min-microvolt = <750000>;
219				regulator-max-microvolt = <1450000>;
220				regulator-ramp-delay = <6001>;
221				regulator-state-mem {
222					regulator-off-in-suspend;
223				};
224			};
225
226			vdd_gpu: DCDC_REG2 {
227				regulator-name = "vdd_gpu";
228				regulator-always-on;
229				regulator-boot-on;
230				regulator-min-microvolt = <800000>;
231				regulator-max-microvolt = <1250000>;
232				regulator-ramp-delay = <6001>;
233				regulator-state-mem {
234					regulator-off-in-suspend;
235				};
236			};
237
238			vcc135_ddr: DCDC_REG3 {
239				regulator-name = "vcc135_ddr";
240				regulator-always-on;
241				regulator-boot-on;
242				regulator-state-mem {
243					regulator-on-in-suspend;
244				};
245			};
246
247			/*
248			 * vcc_18 has several aliases.  (vcc18_flashio and
249			 * vcc18_wl).  We'll add those aliases here just to
250			 * make it easier to follow the schematic.  The signals
251			 * are actually hooked together and only separated for
252			 * power measurement purposes).
253			 */
254			vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
255				regulator-name = "vcc_18";
256				regulator-always-on;
257				regulator-boot-on;
258				regulator-min-microvolt = <1800000>;
259				regulator-max-microvolt = <1800000>;
260				regulator-state-mem {
261					regulator-on-in-suspend;
262					regulator-suspend-microvolt = <1800000>;
263				};
264			};
265
266			/*
267			 * Note that both vcc33_io and vcc33_pmuio are always
268			 * powered together. To simplify the logic in the dts
269			 * we just refer to vcc33_io every time something is
270			 * powered from vcc33_pmuio. In fact, on later boards
271			 * (such as danger) they're the same net.
272			 */
273			vcc33_io: LDO_REG1 {
274				regulator-name = "vcc33_io";
275				regulator-always-on;
276				regulator-boot-on;
277				regulator-min-microvolt = <3300000>;
278				regulator-max-microvolt = <3300000>;
279				regulator-state-mem {
280					regulator-on-in-suspend;
281					regulator-suspend-microvolt = <3300000>;
282				};
283			};
284
285			vdd_10: LDO_REG3 {
286				regulator-name = "vdd_10";
287				regulator-always-on;
288				regulator-boot-on;
289				regulator-min-microvolt = <1000000>;
290				regulator-max-microvolt = <1000000>;
291				regulator-state-mem {
292					regulator-on-in-suspend;
293					regulator-suspend-microvolt = <1000000>;
294				};
295			};
296
297			vdd10_lcd_pwren_h: LDO_REG7 {
298				regulator-name = "vdd10_lcd_pwren_h";
299				regulator-always-on;
300				regulator-boot-on;
301				regulator-min-microvolt = <2500000>;
302				regulator-max-microvolt = <2500000>;
303				regulator-state-mem {
304					regulator-off-in-suspend;
305				};
306			};
307
308			vcc33_lcd: SWITCH_REG1 {
309				regulator-name = "vcc33_lcd";
310				regulator-always-on;
311				regulator-boot-on;
312				regulator-state-mem {
313					regulator-off-in-suspend;
314				};
315			};
316		};
317	};
318};
319
320&i2c1 {
321	status = "okay";
322
323	clock-frequency = <400000>;
324	i2c-scl-falling-time-ns = <50>;		/* 2.5ns measured */
325	i2c-scl-rising-time-ns = <100>;		/* 40ns measured */
326
327	tpm: tpm@20 {
328		compatible = "infineon,slb9645tt";
329		reg = <0x20>;
330		powered-while-suspended;
331	};
332};
333
334&i2c2 {
335	status = "okay";
336
337	/* 100kHz since 4.7k resistors don't rise fast enough */
338	clock-frequency = <100000>;
339	i2c-scl-falling-time-ns = <50>;		/* 10ns measured */
340	i2c-scl-rising-time-ns = <800>;		/* 600ns measured */
341};
342
343&i2c4 {
344	status = "okay";
345
346	clock-frequency = <400000>;
347	i2c-scl-falling-time-ns = <50>;		/* 11ns measured */
348	i2c-scl-rising-time-ns = <300>;		/* 225ns measured */
349};
350
351&io_domains {
352	status = "okay";
353
354	bb-supply = <&vcc33_io>;
355	dvp-supply = <&vcc_18>;
356	flash0-supply = <&vcc18_flashio>;
357	gpio1830-supply = <&vcc33_io>;
358	gpio30-supply = <&vcc33_io>;
359	lcdc-supply = <&vcc33_lcd>;
360	wifi-supply = <&vcc18_wl>;
361};
362
363&pwm1 {
364	status = "okay";
365};
366
367&sdio0 {
368	status = "okay";
369
370	bus-width = <4>;
371	cap-sd-highspeed;
372	cap-sdio-irq;
373	keep-power-in-suspend;
374	mmc-pwrseq = <&sdio_pwrseq>;
375	non-removable;
376	pinctrl-names = "default";
377	pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
378	sd-uhs-sdr12;
379	sd-uhs-sdr25;
380	sd-uhs-sdr50;
381	sd-uhs-sdr104;
382	vmmc-supply = <&vcc33_sys>;
383	vqmmc-supply = <&vcc18_wl>;
384};
385
386&spi2 {
387	status = "okay";
388
389	rx-sample-delay-ns = <12>;
390
391	flash@0 {
392		compatible = "jedec,spi-nor";
393		spi-max-frequency = <50000000>;
394		reg = <0>;
395	};
396};
397
398&tsadc {
399	status = "okay";
400
401	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
402	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
403	rockchip,hw-tshut-temp = <125000>;
404};
405
406&uart0 {
407	status = "okay";
408
409	/* Pins don't include flow control by default; add that in */
410	pinctrl-names = "default";
411	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
412};
413
414&uart1 {
415	status = "okay";
416};
417
418&uart2 {
419	status = "okay";
420};
421
422&usbphy {
423	status = "okay";
424};
425
426&usb_host0_ehci {
427	status = "okay";
428
429	needs-reset-on-resume;
430};
431
432&usb_host1 {
433	status = "okay";
434	snps,need-phy-for-wake;
435};
436
437&usb_otg {
438	status = "okay";
439
440	assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
441	assigned-clock-parents = <&usbphy0>;
442	dr_mode = "host";
443	snps,need-phy-for-wake;
444};
445
446&vopb {
447	status = "okay";
448};
449
450&vopb_mmu {
451	status = "okay";
452};
453
454&wdt {
455	status = "okay";
456};
457
458&pinctrl {
459	pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
460		bias-disable;
461		drive-strength = <8>;
462	};
463
464	pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
465		bias-pull-up;
466		drive-strength = <8>;
467	};
468
469	pcfg_output_high: pcfg-output-high {
470		output-high;
471	};
472
473	pcfg_output_low: pcfg-output-low {
474		output-low;
475	};
476
477	buttons {
478		pwr_key_l: pwr-key-l {
479			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
480		};
481	};
482
483	emmc {
484		emmc_reset: emmc-reset {
485			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
486		};
487
488		/*
489		 * We run eMMC at max speed; bump up drive strength.
490		 * We also have external pulls, so disable the internal ones.
491		 */
492		emmc_clk: emmc-clk {
493			rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>;
494		};
495
496		emmc_cmd: emmc-cmd {
497			rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>;
498		};
499
500		emmc_bus8: emmc-bus8 {
501			rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>,
502					<3 RK_PA1 2 &pcfg_pull_none_drv_8ma>,
503					<3 RK_PA2 2 &pcfg_pull_none_drv_8ma>,
504					<3 RK_PA3 2 &pcfg_pull_none_drv_8ma>,
505					<3 RK_PA4 2 &pcfg_pull_none_drv_8ma>,
506					<3 RK_PA5 2 &pcfg_pull_none_drv_8ma>,
507					<3 RK_PA6 2 &pcfg_pull_none_drv_8ma>,
508					<3 RK_PA7 2 &pcfg_pull_none_drv_8ma>;
509		};
510	};
511
512	pmic {
513		pmic_int_l: pmic-int-l {
514			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
515		};
516	};
517
518	reboot {
519		ap_warm_reset_h: ap-warm-reset-h {
520			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
521		};
522	};
523
524	recovery-switch {
525		rec_mode_l: rec-mode-l {
526			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
527		};
528	};
529
530	sdio0 {
531		wifi_enable_h: wifienable-h {
532			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
533		};
534
535		/* NOTE: mislabelled on schematic; should be bt_enable_h */
536		bt_enable_l: bt-enable-l {
537			rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
538		};
539
540		bt_host_wake: bt-host-wake {
541			rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>;
542		};
543
544		bt_host_wake_l: bt-host-wake-l {
545			rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
546		};
547
548		/*
549		 * We run sdio0 at max speed; bump up drive strength.
550		 * We also have external pulls, so disable the internal ones.
551		 */
552		sdio0_bus4: sdio0-bus4 {
553			rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>,
554					<4 RK_PC5 1 &pcfg_pull_none_drv_8ma>,
555					<4 RK_PC6 1 &pcfg_pull_none_drv_8ma>,
556					<4 RK_PC7 1 &pcfg_pull_none_drv_8ma>;
557		};
558
559		sdio0_cmd: sdio0-cmd {
560			rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>;
561		};
562
563		sdio0_clk: sdio0-clk {
564			rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;
565		};
566
567		/*
568		 * These pins are only present on very new veyron boards; on
569		 * older boards bt_dev_wake is simply always high.  Note that
570		 * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt
571		 * to map this pin everywhere
572		 */
573		bt_dev_wake_sleep: bt-dev-wake-sleep {
574			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>;
575		};
576
577		bt_dev_wake_awake: bt-dev-wake-awake {
578			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
579		};
580
581		bt_dev_wake: bt-dev-wake {
582			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
583		};
584	};
585
586	tpm {
587		tpm_int_h: tpm-int-h {
588			rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
589		};
590	};
591
592	write-protect {
593		fw_wp_ap: fw-wp-ap {
594			rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
595		};
596	};
597};
598