1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3066a-cru.h> 10#include <dt-bindings/power/rk3066-power.h> 11#include "rk3xxx.dtsi" 12 13/ { 14 compatible = "rockchip,rk3066a"; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 enable-method = "rockchip,rk3066-smp"; 20 21 cpu0: cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a9"; 24 next-level-cache = <&L2>; 25 reg = <0x0>; 26 operating-points = 27 /* kHz uV */ 28 <1416000 1300000>, 29 <1200000 1175000>, 30 <1008000 1125000>, 31 <816000 1125000>, 32 <600000 1100000>, 33 <504000 1100000>, 34 <312000 1075000>; 35 clock-latency = <40000>; 36 clocks = <&cru ARMCLK>; 37 }; 38 cpu1: cpu@1 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a9"; 41 next-level-cache = <&L2>; 42 reg = <0x1>; 43 }; 44 }; 45 46 display-subsystem { 47 compatible = "rockchip,display-subsystem"; 48 ports = <&vop0_out>, <&vop1_out>; 49 }; 50 51 sram: sram@10080000 { 52 compatible = "mmio-sram"; 53 reg = <0x10080000 0x10000>; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 ranges = <0 0x10080000 0x10000>; 57 58 smp-sram@0 { 59 compatible = "rockchip,rk3066-smp-sram"; 60 reg = <0x0 0x50>; 61 }; 62 }; 63 64 vop0: vop@1010c000 { 65 compatible = "rockchip,rk3066-vop"; 66 reg = <0x1010c000 0x19c>; 67 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 68 clocks = <&cru ACLK_LCDC0>, 69 <&cru DCLK_LCDC0>, 70 <&cru HCLK_LCDC0>; 71 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 72 power-domains = <&power RK3066_PD_VIO>; 73 resets = <&cru SRST_LCDC0_AXI>, 74 <&cru SRST_LCDC0_AHB>, 75 <&cru SRST_LCDC0_DCLK>; 76 reset-names = "axi", "ahb", "dclk"; 77 status = "disabled"; 78 79 vop0_out: port { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 vop0_out_hdmi: endpoint@0 { 84 reg = <0>; 85 remote-endpoint = <&hdmi_in_vop0>; 86 }; 87 }; 88 }; 89 90 vop1: vop@1010e000 { 91 compatible = "rockchip,rk3066-vop"; 92 reg = <0x1010e000 0x19c>; 93 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 94 clocks = <&cru ACLK_LCDC1>, 95 <&cru DCLK_LCDC1>, 96 <&cru HCLK_LCDC1>; 97 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 98 power-domains = <&power RK3066_PD_VIO>; 99 resets = <&cru SRST_LCDC1_AXI>, 100 <&cru SRST_LCDC1_AHB>, 101 <&cru SRST_LCDC1_DCLK>; 102 reset-names = "axi", "ahb", "dclk"; 103 status = "disabled"; 104 105 vop1_out: port { 106 #address-cells = <1>; 107 #size-cells = <0>; 108 109 vop1_out_hdmi: endpoint@0 { 110 reg = <0>; 111 remote-endpoint = <&hdmi_in_vop1>; 112 }; 113 }; 114 }; 115 116 hdmi: hdmi@10116000 { 117 compatible = "rockchip,rk3066-hdmi"; 118 reg = <0x10116000 0x2000>; 119 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 120 clocks = <&cru HCLK_HDMI>; 121 clock-names = "hclk"; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; 124 power-domains = <&power RK3066_PD_VIO>; 125 rockchip,grf = <&grf>; 126 #sound-dai-cells = <0>; 127 status = "disabled"; 128 129 ports { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 hdmi_in: port@0 { 134 reg = <0>; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 hdmi_in_vop0: endpoint@0 { 139 reg = <0>; 140 remote-endpoint = <&vop0_out_hdmi>; 141 }; 142 143 hdmi_in_vop1: endpoint@1 { 144 reg = <1>; 145 remote-endpoint = <&vop1_out_hdmi>; 146 }; 147 }; 148 149 hdmi_out: port@1 { 150 reg = <1>; 151 }; 152 }; 153 }; 154 155 i2s0: i2s@10118000 { 156 compatible = "rockchip,rk3066-i2s"; 157 reg = <0x10118000 0x2000>; 158 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&i2s0_bus>; 161 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; 162 clock-names = "i2s_clk", "i2s_hclk"; 163 dmas = <&dmac1_s 4>, <&dmac1_s 5>; 164 dma-names = "tx", "rx"; 165 rockchip,playback-channels = <8>; 166 rockchip,capture-channels = <2>; 167 #sound-dai-cells = <0>; 168 status = "disabled"; 169 }; 170 171 i2s1: i2s@1011a000 { 172 compatible = "rockchip,rk3066-i2s"; 173 reg = <0x1011a000 0x2000>; 174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 175 pinctrl-names = "default"; 176 pinctrl-0 = <&i2s1_bus>; 177 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 178 clock-names = "i2s_clk", "i2s_hclk"; 179 dmas = <&dmac1_s 6>, <&dmac1_s 7>; 180 dma-names = "tx", "rx"; 181 rockchip,playback-channels = <2>; 182 rockchip,capture-channels = <2>; 183 #sound-dai-cells = <0>; 184 status = "disabled"; 185 }; 186 187 i2s2: i2s@1011c000 { 188 compatible = "rockchip,rk3066-i2s"; 189 reg = <0x1011c000 0x2000>; 190 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&i2s2_bus>; 193 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 194 clock-names = "i2s_clk", "i2s_hclk"; 195 dmas = <&dmac1_s 9>, <&dmac1_s 10>; 196 dma-names = "tx", "rx"; 197 rockchip,playback-channels = <2>; 198 rockchip,capture-channels = <2>; 199 #sound-dai-cells = <0>; 200 status = "disabled"; 201 }; 202 203 cru: clock-controller@20000000 { 204 compatible = "rockchip,rk3066a-cru"; 205 reg = <0x20000000 0x1000>; 206 clocks = <&xin24m>; 207 clock-names = "xin24m"; 208 rockchip,grf = <&grf>; 209 #clock-cells = <1>; 210 #reset-cells = <1>; 211 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, 212 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 213 <&cru PCLK_CPU>, <&cru ACLK_PERI>, 214 <&cru HCLK_PERI>, <&cru PCLK_PERI>; 215 assigned-clock-rates = <400000000>, <594000000>, 216 <300000000>, <150000000>, 217 <75000000>, <300000000>, 218 <150000000>, <75000000>; 219 }; 220 221 timer2: timer@2000e000 { 222 compatible = "snps,dw-apb-timer"; 223 reg = <0x2000e000 0x100>; 224 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; 226 clock-names = "timer", "pclk"; 227 }; 228 229 efuse: efuse@20010000 { 230 compatible = "rockchip,rk3066a-efuse"; 231 reg = <0x20010000 0x4000>; 232 #address-cells = <1>; 233 #size-cells = <1>; 234 clocks = <&cru PCLK_EFUSE>; 235 clock-names = "pclk_efuse"; 236 237 cpu_leakage: cpu_leakage@17 { 238 reg = <0x17 0x1>; 239 }; 240 }; 241 242 timer0: timer@20038000 { 243 compatible = "snps,dw-apb-timer"; 244 reg = <0x20038000 0x100>; 245 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; 247 clock-names = "timer", "pclk"; 248 }; 249 250 timer1: timer@2003a000 { 251 compatible = "snps,dw-apb-timer"; 252 reg = <0x2003a000 0x100>; 253 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; 255 clock-names = "timer", "pclk"; 256 }; 257 258 tsadc: tsadc@20060000 { 259 compatible = "rockchip,rk3066-tsadc"; 260 reg = <0x20060000 0x100>; 261 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 262 clock-names = "saradc", "apb_pclk"; 263 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 264 #io-channel-cells = <1>; 265 resets = <&cru SRST_TSADC>; 266 reset-names = "saradc-apb"; 267 status = "disabled"; 268 }; 269 270 pinctrl: pinctrl { 271 compatible = "rockchip,rk3066a-pinctrl"; 272 rockchip,grf = <&grf>; 273 #address-cells = <1>; 274 #size-cells = <1>; 275 ranges; 276 277 gpio0: gpio@20034000 { 278 compatible = "rockchip,gpio-bank"; 279 reg = <0x20034000 0x100>; 280 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&cru PCLK_GPIO0>; 282 283 gpio-controller; 284 #gpio-cells = <2>; 285 286 interrupt-controller; 287 #interrupt-cells = <2>; 288 }; 289 290 gpio1: gpio@2003c000 { 291 compatible = "rockchip,gpio-bank"; 292 reg = <0x2003c000 0x100>; 293 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&cru PCLK_GPIO1>; 295 296 gpio-controller; 297 #gpio-cells = <2>; 298 299 interrupt-controller; 300 #interrupt-cells = <2>; 301 }; 302 303 gpio2: gpio@2003e000 { 304 compatible = "rockchip,gpio-bank"; 305 reg = <0x2003e000 0x100>; 306 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&cru PCLK_GPIO2>; 308 309 gpio-controller; 310 #gpio-cells = <2>; 311 312 interrupt-controller; 313 #interrupt-cells = <2>; 314 }; 315 316 gpio3: gpio@20080000 { 317 compatible = "rockchip,gpio-bank"; 318 reg = <0x20080000 0x100>; 319 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&cru PCLK_GPIO3>; 321 322 gpio-controller; 323 #gpio-cells = <2>; 324 325 interrupt-controller; 326 #interrupt-cells = <2>; 327 }; 328 329 gpio4: gpio@20084000 { 330 compatible = "rockchip,gpio-bank"; 331 reg = <0x20084000 0x100>; 332 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&cru PCLK_GPIO4>; 334 335 gpio-controller; 336 #gpio-cells = <2>; 337 338 interrupt-controller; 339 #interrupt-cells = <2>; 340 }; 341 342 gpio6: gpio@2000a000 { 343 compatible = "rockchip,gpio-bank"; 344 reg = <0x2000a000 0x100>; 345 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&cru PCLK_GPIO6>; 347 348 gpio-controller; 349 #gpio-cells = <2>; 350 351 interrupt-controller; 352 #interrupt-cells = <2>; 353 }; 354 355 pcfg_pull_default: pcfg-pull-default { 356 bias-pull-pin-default; 357 }; 358 359 pcfg_pull_none: pcfg-pull-none { 360 bias-disable; 361 }; 362 363 emac { 364 emac_xfer: emac-xfer { 365 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ 366 <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ 367 <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ 368 <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ 369 <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ 370 <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ 371 <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ 372 <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ 373 }; 374 375 emac_mdio: emac-mdio { 376 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ 377 <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ 378 }; 379 }; 380 381 emmc { 382 emmc_clk: emmc-clk { 383 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; 384 }; 385 386 emmc_cmd: emmc-cmd { 387 rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; 388 }; 389 390 emmc_rst: emmc-rst { 391 rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; 392 }; 393 394 /* 395 * The data pins are shared between nandc and emmc and 396 * not accessible through pinctrl. Also they should've 397 * been already set correctly by firmware, as 398 * flash/emmc is the boot-device. 399 */ 400 }; 401 402 hdmi { 403 hdmi_hpd: hdmi-hpd { 404 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; 405 }; 406 407 hdmii2c_xfer: hdmii2c-xfer { 408 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, 409 <0 RK_PA2 1 &pcfg_pull_none>; 410 }; 411 }; 412 413 i2c0 { 414 i2c0_xfer: i2c0-xfer { 415 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, 416 <2 RK_PD5 1 &pcfg_pull_none>; 417 }; 418 }; 419 420 i2c1 { 421 i2c1_xfer: i2c1-xfer { 422 rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, 423 <2 RK_PD7 1 &pcfg_pull_none>; 424 }; 425 }; 426 427 i2c2 { 428 i2c2_xfer: i2c2-xfer { 429 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, 430 <3 RK_PA1 1 &pcfg_pull_none>; 431 }; 432 }; 433 434 i2c3 { 435 i2c3_xfer: i2c3-xfer { 436 rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, 437 <3 RK_PA3 2 &pcfg_pull_none>; 438 }; 439 }; 440 441 i2c4 { 442 i2c4_xfer: i2c4-xfer { 443 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, 444 <3 RK_PA5 1 &pcfg_pull_none>; 445 }; 446 }; 447 448 pwm0 { 449 pwm0_out: pwm0-out { 450 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 451 }; 452 }; 453 454 pwm1 { 455 pwm1_out: pwm1-out { 456 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; 457 }; 458 }; 459 460 pwm2 { 461 pwm2_out: pwm2-out { 462 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 463 }; 464 }; 465 466 pwm3 { 467 pwm3_out: pwm3-out { 468 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; 469 }; 470 }; 471 472 spi0 { 473 spi0_clk: spi0-clk { 474 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; 475 }; 476 spi0_cs0: spi0-cs0 { 477 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; 478 }; 479 spi0_tx: spi0-tx { 480 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; 481 }; 482 spi0_rx: spi0-rx { 483 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; 484 }; 485 spi0_cs1: spi0-cs1 { 486 rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; 487 }; 488 }; 489 490 spi1 { 491 spi1_clk: spi1-clk { 492 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; 493 }; 494 spi1_cs0: spi1-cs0 { 495 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; 496 }; 497 spi1_rx: spi1-rx { 498 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; 499 }; 500 spi1_tx: spi1-tx { 501 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; 502 }; 503 spi1_cs1: spi1-cs1 { 504 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; 505 }; 506 }; 507 508 uart0 { 509 uart0_xfer: uart0-xfer { 510 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, 511 <1 RK_PA1 1 &pcfg_pull_default>; 512 }; 513 514 uart0_cts: uart0-cts { 515 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; 516 }; 517 518 uart0_rts: uart0-rts { 519 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; 520 }; 521 }; 522 523 uart1 { 524 uart1_xfer: uart1-xfer { 525 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, 526 <1 RK_PA5 1 &pcfg_pull_default>; 527 }; 528 529 uart1_cts: uart1-cts { 530 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; 531 }; 532 533 uart1_rts: uart1-rts { 534 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 535 }; 536 }; 537 538 uart2 { 539 uart2_xfer: uart2-xfer { 540 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, 541 <1 RK_PB1 1 &pcfg_pull_default>; 542 }; 543 /* no rts / cts for uart2 */ 544 }; 545 546 uart3 { 547 uart3_xfer: uart3-xfer { 548 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, 549 <3 RK_PD4 1 &pcfg_pull_default>; 550 }; 551 552 uart3_cts: uart3-cts { 553 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; 554 }; 555 556 uart3_rts: uart3-rts { 557 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; 558 }; 559 }; 560 561 sd0 { 562 sd0_clk: sd0-clk { 563 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; 564 }; 565 566 sd0_cmd: sd0-cmd { 567 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; 568 }; 569 570 sd0_cd: sd0-cd { 571 rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; 572 }; 573 574 sd0_wp: sd0-wp { 575 rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; 576 }; 577 578 sd0_bus1: sd0-bus-width1 { 579 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; 580 }; 581 582 sd0_bus4: sd0-bus-width4 { 583 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, 584 <3 RK_PB3 1 &pcfg_pull_default>, 585 <3 RK_PB4 1 &pcfg_pull_default>, 586 <3 RK_PB5 1 &pcfg_pull_default>; 587 }; 588 }; 589 590 sd1 { 591 sd1_clk: sd1-clk { 592 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; 593 }; 594 595 sd1_cmd: sd1-cmd { 596 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; 597 }; 598 599 sd1_cd: sd1-cd { 600 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; 601 }; 602 603 sd1_wp: sd1-wp { 604 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; 605 }; 606 607 sd1_bus1: sd1-bus-width1 { 608 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; 609 }; 610 611 sd1_bus4: sd1-bus-width4 { 612 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, 613 <3 RK_PC2 1 &pcfg_pull_default>, 614 <3 RK_PC3 1 &pcfg_pull_default>, 615 <3 RK_PC4 1 &pcfg_pull_default>; 616 }; 617 }; 618 619 i2s0 { 620 i2s0_bus: i2s0-bus { 621 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, 622 <0 RK_PB0 1 &pcfg_pull_default>, 623 <0 RK_PB1 1 &pcfg_pull_default>, 624 <0 RK_PB2 1 &pcfg_pull_default>, 625 <0 RK_PB3 1 &pcfg_pull_default>, 626 <0 RK_PB4 1 &pcfg_pull_default>, 627 <0 RK_PB5 1 &pcfg_pull_default>, 628 <0 RK_PB6 1 &pcfg_pull_default>, 629 <0 RK_PB7 1 &pcfg_pull_default>; 630 }; 631 }; 632 633 i2s1 { 634 i2s1_bus: i2s1-bus { 635 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, 636 <0 RK_PC1 1 &pcfg_pull_default>, 637 <0 RK_PC2 1 &pcfg_pull_default>, 638 <0 RK_PC3 1 &pcfg_pull_default>, 639 <0 RK_PC4 1 &pcfg_pull_default>, 640 <0 RK_PC5 1 &pcfg_pull_default>; 641 }; 642 }; 643 644 i2s2 { 645 i2s2_bus: i2s2-bus { 646 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, 647 <0 RK_PD1 1 &pcfg_pull_default>, 648 <0 RK_PD2 1 &pcfg_pull_default>, 649 <0 RK_PD3 1 &pcfg_pull_default>, 650 <0 RK_PD4 1 &pcfg_pull_default>, 651 <0 RK_PD5 1 &pcfg_pull_default>; 652 }; 653 }; 654 }; 655}; 656 657&gpu { 658 compatible = "rockchip,rk3066-mali", "arm,mali-400"; 659 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 669 interrupt-names = "gp", 670 "gpmmu", 671 "pp0", 672 "ppmmu0", 673 "pp1", 674 "ppmmu1", 675 "pp2", 676 "ppmmu2", 677 "pp3", 678 "ppmmu3"; 679 power-domains = <&power RK3066_PD_GPU>; 680}; 681 682&grf { 683 compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd"; 684 685 usbphy: usbphy { 686 compatible = "rockchip,rk3066a-usb-phy"; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 status = "disabled"; 690 691 usbphy0: usb-phy@17c { 692 reg = <0x17c>; 693 clocks = <&cru SCLK_OTGPHY0>; 694 clock-names = "phyclk"; 695 #clock-cells = <0>; 696 #phy-cells = <0>; 697 }; 698 699 usbphy1: usb-phy@188 { 700 reg = <0x188>; 701 clocks = <&cru SCLK_OTGPHY1>; 702 clock-names = "phyclk"; 703 #clock-cells = <0>; 704 #phy-cells = <0>; 705 }; 706 }; 707}; 708 709&i2c0 { 710 pinctrl-names = "default"; 711 pinctrl-0 = <&i2c0_xfer>; 712}; 713 714&i2c1 { 715 pinctrl-names = "default"; 716 pinctrl-0 = <&i2c1_xfer>; 717}; 718 719&i2c2 { 720 pinctrl-names = "default"; 721 pinctrl-0 = <&i2c2_xfer>; 722}; 723 724&i2c3 { 725 pinctrl-names = "default"; 726 pinctrl-0 = <&i2c3_xfer>; 727}; 728 729&i2c4 { 730 pinctrl-names = "default"; 731 pinctrl-0 = <&i2c4_xfer>; 732}; 733 734&mmc0 { 735 clock-frequency = <50000000>; 736 dmas = <&dmac2 1>; 737 dma-names = "rx-tx"; 738 max-frequency = <50000000>; 739 pinctrl-names = "default"; 740 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; 741}; 742 743&mmc1 { 744 dmas = <&dmac2 3>; 745 dma-names = "rx-tx"; 746 pinctrl-names = "default"; 747 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; 748}; 749 750&emmc { 751 dmas = <&dmac2 4>; 752 dma-names = "rx-tx"; 753}; 754 755&pmu { 756 power: power-controller { 757 compatible = "rockchip,rk3066-power-controller"; 758 #power-domain-cells = <1>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 762 power-domain@RK3066_PD_VIO { 763 reg = <RK3066_PD_VIO>; 764 clocks = <&cru ACLK_LCDC0>, 765 <&cru ACLK_LCDC1>, 766 <&cru DCLK_LCDC0>, 767 <&cru DCLK_LCDC1>, 768 <&cru HCLK_LCDC0>, 769 <&cru HCLK_LCDC1>, 770 <&cru SCLK_CIF1>, 771 <&cru ACLK_CIF1>, 772 <&cru HCLK_CIF1>, 773 <&cru SCLK_CIF0>, 774 <&cru ACLK_CIF0>, 775 <&cru HCLK_CIF0>, 776 <&cru HCLK_HDMI>, 777 <&cru ACLK_IPP>, 778 <&cru HCLK_IPP>, 779 <&cru ACLK_RGA>, 780 <&cru HCLK_RGA>; 781 pm_qos = <&qos_lcdc0>, 782 <&qos_lcdc1>, 783 <&qos_cif0>, 784 <&qos_cif1>, 785 <&qos_ipp>, 786 <&qos_rga>; 787 #power-domain-cells = <0>; 788 }; 789 790 power-domain@RK3066_PD_VIDEO { 791 reg = <RK3066_PD_VIDEO>; 792 clocks = <&cru ACLK_VDPU>, 793 <&cru ACLK_VEPU>, 794 <&cru HCLK_VDPU>, 795 <&cru HCLK_VEPU>; 796 pm_qos = <&qos_vpu>; 797 #power-domain-cells = <0>; 798 }; 799 800 power-domain@RK3066_PD_GPU { 801 reg = <RK3066_PD_GPU>; 802 clocks = <&cru ACLK_GPU>; 803 pm_qos = <&qos_gpu>; 804 #power-domain-cells = <0>; 805 }; 806 }; 807}; 808 809&pwm0 { 810 pinctrl-names = "default"; 811 pinctrl-0 = <&pwm0_out>; 812}; 813 814&pwm1 { 815 pinctrl-names = "default"; 816 pinctrl-0 = <&pwm1_out>; 817}; 818 819&pwm2 { 820 pinctrl-names = "default"; 821 pinctrl-0 = <&pwm2_out>; 822}; 823 824&pwm3 { 825 pinctrl-names = "default"; 826 pinctrl-0 = <&pwm3_out>; 827}; 828 829&spi0 { 830 pinctrl-names = "default"; 831 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 832}; 833 834&spi1 { 835 pinctrl-names = "default"; 836 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 837}; 838 839&uart0 { 840 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 841 dmas = <&dmac1_s 0>, <&dmac1_s 1>; 842 dma-names = "tx", "rx"; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&uart0_xfer>; 845}; 846 847&uart1 { 848 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 849 dmas = <&dmac1_s 2>, <&dmac1_s 3>; 850 dma-names = "tx", "rx"; 851 pinctrl-names = "default"; 852 pinctrl-0 = <&uart1_xfer>; 853}; 854 855&uart2 { 856 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 857 dmas = <&dmac2 6>, <&dmac2 7>; 858 dma-names = "tx", "rx"; 859 pinctrl-names = "default"; 860 pinctrl-0 = <&uart2_xfer>; 861}; 862 863&uart3 { 864 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; 865 dmas = <&dmac2 8>, <&dmac2 9>; 866 dma-names = "tx", "rx"; 867 pinctrl-names = "default"; 868 pinctrl-0 = <&uart3_xfer>; 869}; 870 871&vpu { 872 power-domains = <&power RK3066_PD_VIDEO>; 873}; 874 875&wdt { 876 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; 877}; 878 879&emac { 880 compatible = "rockchip,rk3066-emac"; 881}; 882