1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SDX65 SoC device tree source 4 * 5 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-sdx65.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15#include <dt-bindings/interconnect/qcom,sdx65.h> 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; 21 interrupt-parent = <&intc>; 22 23 memory { 24 device_type = "memory"; 25 reg = <0 0>; 26 }; 27 28 clocks { 29 xo_board: xo-board { 30 compatible = "fixed-clock"; 31 clock-frequency = <76800000>; 32 clock-output-names = "xo_board"; 33 #clock-cells = <0>; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 clock-frequency = <32764>; 39 clock-output-names = "sleep_clk"; 40 #clock-cells = <0>; 41 }; 42 43 nand_clk_dummy: nand-clk-dummy { 44 compatible = "fixed-clock"; 45 clock-frequency = <32764>; 46 #clock-cells = <0>; 47 }; 48 }; 49 50 cpus { 51 #address-cells = <1>; 52 #size-cells = <0>; 53 54 cpu0: cpu@0 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a7"; 57 reg = <0x0>; 58 enable-method = "psci"; 59 clocks = <&apcs>; 60 power-domains = <&rpmhpd SDX65_CX_AO>; 61 power-domain-names = "rpmhpd"; 62 operating-points-v2 = <&cpu_opp_table>; 63 }; 64 }; 65 66 firmware { 67 scm { 68 compatible = "qcom,scm-sdx65", "qcom,scm"; 69 }; 70 }; 71 72 mc_virt: interconnect-mc-virt { 73 compatible = "qcom,sdx65-mc-virt"; 74 #interconnect-cells = <1>; 75 qcom,bcm-voters = <&apps_bcm_voter>; 76 }; 77 78 cpu_opp_table: opp-table-cpu { 79 compatible = "operating-points-v2"; 80 opp-shared; 81 82 opp-345600000 { 83 opp-hz = /bits/ 64 <345600000>; 84 required-opps = <&rpmhpd_opp_low_svs>; 85 }; 86 87 opp-576000000 { 88 opp-hz = /bits/ 64 <576000000>; 89 required-opps = <&rpmhpd_opp_svs>; 90 }; 91 92 opp-1094400000 { 93 opp-hz = /bits/ 64 <1094400000>; 94 required-opps = <&rpmhpd_opp_nom>; 95 }; 96 97 opp-1497600000 { 98 opp-hz = /bits/ 64 <1497600000>; 99 required-opps = <&rpmhpd_opp_turbo>; 100 }; 101 }; 102 103 psci { 104 compatible = "arm,psci-1.0"; 105 method = "smc"; 106 }; 107 108 reserved_memory: reserved-memory { 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges; 112 113 tz_heap_mem: memory@8fcad000 { 114 no-map; 115 reg = <0x8fcad000 0x40000>; 116 }; 117 118 secdata_mem: memory@8fcfd000 { 119 no-map; 120 reg = <0x8fcfd000 0x1000>; 121 }; 122 123 hyp_mem: memory@8fd00000 { 124 no-map; 125 reg = <0x8fd00000 0x80000>; 126 }; 127 128 access_control_mem: memory@8fd80000 { 129 no-map; 130 reg = <0x8fd80000 0x80000>; 131 }; 132 133 aop_mem: memory@8fe00000 { 134 no-map; 135 reg = <0x8fe00000 0x20000>; 136 }; 137 138 smem_mem: memory@8fe20000 { 139 compatible = "qcom,smem"; 140 reg = <0x8fe20000 0xc0000>; 141 hwlocks = <&tcsr_mutex 3>; 142 no-map; 143 }; 144 145 cmd_db: reserved-memory@8fee0000 { 146 compatible = "qcom,cmd-db"; 147 reg = <0x8fee0000 0x20000>; 148 no-map; 149 }; 150 151 tz_mem: memory@8ff00000 { 152 no-map; 153 reg = <0x8ff00000 0x100000>; 154 }; 155 156 tz_apps_mem: memory@90000000 { 157 no-map; 158 reg = <0x90000000 0x500000>; 159 }; 160 161 llcc_tcm_mem: memory@15800000 { 162 no-map; 163 reg = <0x15800000 0x800000>; 164 }; 165 }; 166 167 smp2p-mpss { 168 compatible = "qcom,smp2p"; 169 qcom,smem = <435>, <428>; 170 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 171 mboxes = <&apcs 14>; 172 qcom,local-pid = <0>; 173 qcom,remote-pid = <1>; 174 175 modem_smp2p_out: master-kernel { 176 qcom,entry-name = "master-kernel"; 177 #qcom,smem-state-cells = <1>; 178 }; 179 180 modem_smp2p_in: slave-kernel { 181 qcom,entry-name = "slave-kernel"; 182 interrupt-controller; 183 #interrupt-cells = <2>; 184 }; 185 186 ipa_smp2p_out: ipa-ap-to-modem { 187 qcom,entry-name = "ipa"; 188 #qcom,smem-state-cells = <1>; 189 }; 190 191 ipa_smp2p_in: ipa-modem-to-ap { 192 qcom,entry-name = "ipa"; 193 interrupt-controller; 194 #interrupt-cells = <2>; 195 }; 196 }; 197 198 soc: soc { 199 #address-cells = <1>; 200 #size-cells = <1>; 201 ranges; 202 compatible = "simple-bus"; 203 204 gcc: clock-controller@100000 { 205 compatible = "qcom,gcc-sdx65"; 206 reg = <0x00100000 0x001f7400>; 207 clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; 208 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 209 #power-domain-cells = <1>; 210 #clock-cells = <1>; 211 #reset-cells = <1>; 212 }; 213 214 blsp1_uart3: serial@831000 { 215 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 216 reg = <0x00831000 0x200>; 217 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 219 clock-names = "core", "iface"; 220 status = "disabled"; 221 }; 222 223 usb_hsphy: phy@ff4000 { 224 compatible = "qcom,sdx65-usb-hs-phy", 225 "qcom,usb-snps-hs-7nm-phy"; 226 reg = <0xff4000 0x120>; 227 #phy-cells = <0>; 228 clocks = <&rpmhcc RPMH_CXO_CLK>; 229 clock-names = "ref"; 230 resets = <&gcc GCC_QUSB2PHY_BCR>; 231 status = "disabled"; 232 }; 233 234 usb_qmpphy: phy@ff6000 { 235 compatible = "qcom,sdx65-qmp-usb3-uni-phy"; 236 reg = <0x00ff6000 0x1c8>; 237 #address-cells = <1>; 238 #size-cells = <1>; 239 ranges; 240 241 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 242 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 243 <&gcc GCC_USB3_PRIM_CLKREF_EN>; 244 clock-names = "aux", "cfg_ahb", "ref"; 245 246 resets = <&gcc GCC_USB3PHY_PHY_BCR>, 247 <&gcc GCC_USB3_PHY_BCR>; 248 reset-names = "phy", "common"; 249 250 status = "disabled"; 251 252 usb_ssphy: phy@ff6200 { 253 reg = <0x00ff6e00 0x160>, 254 <0x00ff7000 0x1ec>, 255 <0x00ff6200 0x1e00>; 256 #phy-cells = <0>; 257 #clock-cells = <0>; 258 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 259 clock-names = "pipe0"; 260 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 261 }; 262 }; 263 264 system_noc: interconnect@1620000 { 265 compatible = "qcom,sdx65-system-noc"; 266 reg = <0x01620000 0x31200>; 267 #interconnect-cells = <1>; 268 qcom,bcm-voters = <&apps_bcm_voter>; 269 }; 270 271 qpic_bam: dma-controller@1b04000 { 272 compatible = "qcom,bam-v1.7.0"; 273 reg = <0x01b04000 0x1c000>; 274 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&rpmhcc RPMH_QPIC_CLK>; 276 clock-names = "bam_clk"; 277 #dma-cells = <1>; 278 qcom,ee = <0>; 279 qcom,controlled-remotely; 280 status = "disabled"; 281 }; 282 283 qpic_nand: nand-controller@1b30000 { 284 compatible = "qcom,sdx55-nand"; 285 reg = <0x01b30000 0x10000>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 clocks = <&rpmhcc RPMH_QPIC_CLK>, 289 <&nand_clk_dummy>; 290 clock-names = "core", "aon"; 291 292 dmas = <&qpic_bam 0>, 293 <&qpic_bam 1>, 294 <&qpic_bam 2>; 295 dma-names = "tx", "rx", "cmd"; 296 status = "disabled"; 297 }; 298 299 pcie_ep: pcie-ep@1c00000 { 300 compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep"; 301 reg = <0x01c00000 0x3000>, 302 <0x40000000 0xf1d>, 303 <0x40000f20 0xa8>, 304 <0x40001000 0x1000>, 305 <0x40200000 0x100000>, 306 <0x01c03000 0x3000>; 307 reg-names = "parf", 308 "dbi", 309 "elbi", 310 "atu", 311 "addr_space", 312 "mmio"; 313 314 qcom,perst-regs = <&tcsr 0xb258 0xb270>; 315 316 clocks = <&gcc GCC_PCIE_AUX_CLK>, 317 <&gcc GCC_PCIE_CFG_AHB_CLK>, 318 <&gcc GCC_PCIE_MSTR_AXI_CLK>, 319 <&gcc GCC_PCIE_SLV_AXI_CLK>, 320 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, 321 <&gcc GCC_PCIE_SLEEP_CLK>, 322 <&gcc GCC_PCIE_0_CLKREF_EN>; 323 clock-names = "aux", 324 "cfg", 325 "bus_master", 326 "bus_slave", 327 "slave_q2a", 328 "sleep", 329 "ref"; 330 331 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 333 interrupt-names = "global", "doorbell"; 334 335 resets = <&gcc GCC_PCIE_BCR>; 336 reset-names = "core"; 337 338 power-domains = <&gcc PCIE_GDSC>; 339 340 phys = <&pcie_phy>; 341 phy-names = "pciephy"; 342 343 max-link-speed = <3>; 344 num-lanes = <2>; 345 346 status = "disabled"; 347 }; 348 349 pcie_phy: phy@1c06000 { 350 compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; 351 reg = <0x01c06000 0x2000>; 352 353 clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, 354 <&gcc GCC_PCIE_CFG_AHB_CLK>, 355 <&gcc GCC_PCIE_0_CLKREF_EN>, 356 <&gcc GCC_PCIE_RCHNG_PHY_CLK>, 357 <&gcc GCC_PCIE_PIPE_CLK>; 358 clock-names = "aux", 359 "cfg_ahb", 360 "ref", 361 "rchng", 362 "pipe"; 363 364 resets = <&gcc GCC_PCIE_PHY_BCR>; 365 reset-names = "phy"; 366 367 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; 368 assigned-clock-rates = <100000000>; 369 370 power-domains = <&gcc PCIE_GDSC>; 371 372 #clock-cells = <0>; 373 clock-output-names = "pcie_pipe_clk"; 374 375 #phy-cells = <0>; 376 377 status = "disabled"; 378 }; 379 380 tcsr_mutex: hwlock@1f40000 { 381 compatible = "qcom,tcsr-mutex"; 382 reg = <0x01f40000 0x40000>; 383 #hwlock-cells = <1>; 384 }; 385 386 tcsr: syscon@1fcb000 { 387 compatible = "qcom,sdx65-tcsr", "syscon"; 388 reg = <0x01fc0000 0x1000>; 389 }; 390 391 ipa: ipa@3f40000 { 392 compatible = "qcom,sdx65-ipa"; 393 394 reg = <0x03f40000 0x10000>, 395 <0x03f50000 0x5000>, 396 <0x03e04000 0xfc000>; 397 reg-names = "ipa-reg", 398 "ipa-shared", 399 "gsi"; 400 401 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, 402 <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 403 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 404 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 405 interrupt-names = "ipa", 406 "gsi", 407 "ipa-clock-query", 408 "ipa-setup-ready"; 409 410 iommus = <&apps_smmu 0x5e0 0x0>, 411 <&apps_smmu 0x5e2 0x0>; 412 413 clocks = <&rpmhcc RPMH_IPA_CLK>; 414 clock-names = "core"; 415 416 interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI1>, 417 <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>; 418 interconnect-names = "memory", 419 "config"; 420 421 qcom,smem-states = <&ipa_smp2p_out 0>, 422 <&ipa_smp2p_out 1>; 423 qcom,smem-state-names = "ipa-clock-enabled-valid", 424 "ipa-clock-enabled"; 425 426 status = "disabled"; 427 }; 428 429 remoteproc_mpss: remoteproc@4080000 { 430 compatible = "qcom,sdx55-mpss-pas"; 431 reg = <0x04080000 0x4040>; 432 433 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 434 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 435 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 436 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 437 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 438 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 439 interrupt-names = "wdog", "fatal", "ready", "handover", 440 "stop-ack", "shutdown-ack"; 441 442 clocks = <&rpmhcc RPMH_CXO_CLK>; 443 clock-names = "xo"; 444 445 power-domains = <&rpmhpd SDX65_CX>, 446 <&rpmhpd SDX65_MSS>; 447 power-domain-names = "cx", "mss"; 448 449 qcom,smem-states = <&modem_smp2p_out 0>; 450 qcom,smem-state-names = "stop"; 451 452 status = "disabled"; 453 454 glink-edge { 455 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; 456 label = "mpss"; 457 qcom,remote-pid = <1>; 458 mboxes = <&apcs 15>; 459 }; 460 }; 461 462 sdhc_1: mmc@8804000 { 463 compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; 464 reg = <0x08804000 0x1000>; 465 reg-names = "hc"; 466 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 468 interrupt-names = "hc_irq", "pwr_irq"; 469 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 470 <&gcc GCC_SDCC1_AHB_CLK>; 471 clock-names = "core", "iface"; 472 status = "disabled"; 473 }; 474 475 mem_noc: interconnect@9680000 { 476 compatible = "qcom,sdx65-mem-noc"; 477 reg = <0x09680000 0x27200>; 478 #interconnect-cells = <1>; 479 qcom,bcm-voters = <&apps_bcm_voter>; 480 }; 481 482 usb: usb@a6f8800 { 483 compatible = "qcom,sdx65-dwc3", "qcom,dwc3"; 484 reg = <0x0a6f8800 0x400>; 485 #address-cells = <1>; 486 #size-cells = <1>; 487 ranges; 488 489 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, 490 <&gcc GCC_USB30_MASTER_CLK>, 491 <&gcc GCC_USB30_MSTR_AXI_CLK>, 492 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 493 <&gcc GCC_USB30_SLEEP_CLK>; 494 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 495 "sleep"; 496 497 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 498 <&gcc GCC_USB30_MASTER_CLK>; 499 assigned-clock-rates = <19200000>, <200000000>; 500 501 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 502 <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, 503 <&pdc 18 IRQ_TYPE_EDGE_BOTH>, 504 <&pdc 19 IRQ_TYPE_EDGE_BOTH>; 505 interrupt-names = "hs_phy_irq", 506 "ss_phy_irq", 507 "dm_hs_phy_irq", 508 "dp_hs_phy_irq"; 509 510 power-domains = <&gcc USB30_GDSC>; 511 512 resets = <&gcc GCC_USB30_BCR>; 513 514 status = "disabled"; 515 516 usb_dwc3: usb@a600000 { 517 compatible = "snps,dwc3"; 518 reg = <0x0a600000 0xcd00>; 519 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 520 iommus = <&apps_smmu 0x1a0 0x0>; 521 snps,dis_u2_susphy_quirk; 522 snps,dis_enblslpm_quirk; 523 phys = <&usb_hsphy>, <&usb_ssphy>; 524 phy-names = "usb2-phy", "usb3-phy"; 525 }; 526 }; 527 528 restart@c264000 { 529 compatible = "qcom,pshold"; 530 reg = <0x0c264000 0x1000>; 531 }; 532 533 spmi_bus: spmi@c440000 { 534 compatible = "qcom,spmi-pmic-arb"; 535 reg = <0xc440000 0xd00>, 536 <0xc600000 0x2000000>, 537 <0xe600000 0x100000>, 538 <0xe700000 0xa0000>, 539 <0xc40a000 0x26000>; 540 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 541 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 542 interrupt-names = "periph_irq"; 543 interrupt-controller; 544 #interrupt-cells = <4>; 545 #address-cells = <2>; 546 #size-cells = <0>; 547 cell-index = <0>; 548 qcom,channel = <0>; 549 qcom,ee = <0>; 550 }; 551 552 tlmm: pinctrl@f100000 { 553 compatible = "qcom,sdx65-tlmm"; 554 reg = <0xf100000 0x300000>; 555 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 556 gpio-controller; 557 #gpio-cells = <2>; 558 gpio-ranges = <&tlmm 0 0 109>; 559 interrupt-controller; 560 interrupt-parent = <&intc>; 561 #interrupt-cells = <2>; 562 }; 563 564 pdc: interrupt-controller@b210000 { 565 compatible = "qcom,sdx65-pdc", "qcom,pdc"; 566 reg = <0xb210000 0x10000>; 567 qcom,pdc-ranges = <0 147 52>, <52 266 32>; 568 #interrupt-cells = <2>; 569 interrupt-parent = <&intc>; 570 interrupt-controller; 571 }; 572 573 sram@1468f000 { 574 compatible = "qcom,sdx65-imem", "syscon", "simple-mfd"; 575 reg = <0x1468f000 0x1000>; 576 ranges = <0x0 0x1468f000 0x1000>; 577 #address-cells = <1>; 578 #size-cells = <1>; 579 580 pil-reloc@94c { 581 compatible = "qcom,pil-reloc-info"; 582 reg = <0x94c 0xc8>; 583 }; 584 }; 585 586 apps_smmu: iommu@15000000 { 587 compatible = "qcom,sdx65-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 588 reg = <0x15000000 0x40000>; 589 #iommu-cells = <2>; 590 #global-interrupts = <1>; 591 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 624 }; 625 626 intc: interrupt-controller@17800000 { 627 compatible = "qcom,msm-qgic2"; 628 interrupt-controller; 629 interrupt-parent = <&intc>; 630 #interrupt-cells = <3>; 631 reg = <0x17800000 0x1000>, 632 <0x17802000 0x1000>; 633 }; 634 635 a7pll: clock@17808000 { 636 compatible = "qcom,sdx55-a7pll"; 637 reg = <0x17808000 0x1000>; 638 clocks = <&rpmhcc RPMH_CXO_CLK>; 639 clock-names = "bi_tcxo"; 640 #clock-cells = <0>; 641 }; 642 643 apcs: mailbox@17810000 { 644 compatible = "qcom,sdx55-apcs-gcc", "syscon"; 645 reg = <0x17810000 0x2000>; 646 #mbox-cells = <1>; 647 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; 648 clock-names = "ref", "pll", "aux"; 649 #clock-cells = <0>; 650 }; 651 652 watchdog@17817000 { 653 compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt"; 654 reg = <0x17817000 0x1000>; 655 clocks = <&sleep_clk>; 656 }; 657 658 timer@17820000 { 659 #address-cells = <1>; 660 #size-cells = <1>; 661 ranges; 662 compatible = "arm,armv7-timer-mem"; 663 reg = <0x17820000 0x1000>; 664 clock-frequency = <19200000>; 665 666 frame@17821000 { 667 frame-number = <0>; 668 interrupts = <GIC_SPI 7 0x4>, 669 <GIC_SPI 6 0x4>; 670 reg = <0x17821000 0x1000>, 671 <0x17822000 0x1000>; 672 }; 673 674 frame@17823000 { 675 frame-number = <1>; 676 interrupts = <GIC_SPI 8 0x4>; 677 reg = <0x17823000 0x1000>; 678 status = "disabled"; 679 }; 680 681 frame@17824000 { 682 frame-number = <2>; 683 interrupts = <GIC_SPI 9 0x4>; 684 reg = <0x17824000 0x1000>; 685 status = "disabled"; 686 }; 687 688 frame@17825000 { 689 frame-number = <3>; 690 interrupts = <GIC_SPI 10 0x4>; 691 reg = <0x17825000 0x1000>; 692 status = "disabled"; 693 }; 694 695 frame@17826000 { 696 frame-number = <4>; 697 interrupts = <GIC_SPI 11 0x4>; 698 reg = <0x17826000 0x1000>; 699 status = "disabled"; 700 }; 701 702 frame@17827000 { 703 frame-number = <5>; 704 interrupts = <GIC_SPI 12 0x4>; 705 reg = <0x17827000 0x1000>; 706 status = "disabled"; 707 }; 708 709 frame@17828000 { 710 frame-number = <6>; 711 interrupts = <GIC_SPI 13 0x4>; 712 reg = <0x17828000 0x1000>; 713 status = "disabled"; 714 }; 715 716 frame@17829000 { 717 frame-number = <7>; 718 interrupts = <GIC_SPI 14 0x4>; 719 reg = <0x17829000 0x1000>; 720 status = "disabled"; 721 }; 722 }; 723 724 apps_rsc: rsc@17830000 { 725 label = "apps_rsc"; 726 compatible = "qcom,rpmh-rsc"; 727 reg = <0x17830000 0x10000>, 728 <0x17840000 0x10000>; 729 reg-names = "drv-0", "drv-1"; 730 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 732 qcom,tcs-offset = <0xd00>; 733 qcom,drv-id = <1>; 734 qcom,tcs-config = <ACTIVE_TCS 2>, 735 <SLEEP_TCS 2>, 736 <WAKE_TCS 2>, 737 <CONTROL_TCS 1>; 738 739 rpmhcc: clock-controller { 740 compatible = "qcom,sdx65-rpmh-clk"; 741 #clock-cells = <1>; 742 clock-names = "xo"; 743 clocks = <&xo_board>; 744 }; 745 746 rpmhpd: power-controller { 747 compatible = "qcom,sdx65-rpmhpd"; 748 #power-domain-cells = <1>; 749 operating-points-v2 = <&rpmhpd_opp_table>; 750 751 rpmhpd_opp_table: opp-table { 752 compatible = "operating-points-v2"; 753 754 rpmhpd_opp_ret: opp1 { 755 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 756 }; 757 758 rpmhpd_opp_min_svs: opp2 { 759 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 760 }; 761 762 rpmhpd_opp_low_svs: opp3 { 763 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 764 }; 765 766 rpmhpd_opp_svs: opp4 { 767 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 768 }; 769 770 rpmhpd_opp_svs_l1: opp5 { 771 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 772 }; 773 774 rpmhpd_opp_nom: opp6 { 775 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 776 }; 777 778 rpmhpd_opp_nom_l1: opp7 { 779 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 780 }; 781 782 rpmhpd_opp_nom_l2: opp8 { 783 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 784 }; 785 786 rpmhpd_opp_turbo: opp9 { 787 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 788 }; 789 790 rpmhpd_opp_turbo_l1: opp10 { 791 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 792 }; 793 }; 794 }; 795 796 apps_bcm_voter: bcm-voter { 797 compatible = "qcom,bcm-voter"; 798 }; 799 800 }; 801 }; 802 803 timer { 804 compatible = "arm,armv7-timer"; 805 interrupts = <1 13 0xf08>, 806 <1 12 0xf08>, 807 <1 10 0xf08>, 808 <1 11 0xf08>; 809 clock-frequency = <19200000>; 810 }; 811}; 812