1*724ba675SRob Herring// SPDX-License-Identifier: BSD-3-Clause 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring/dts-v1/; 7*724ba675SRob Herring 8*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 9*724ba675SRob Herring#include <dt-bindings/clock/qcom,gcc-msm8974.h> 10*724ba675SRob Herring#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 11*724ba675SRob Herring#include <dt-bindings/clock/qcom,rpmcc.h> 12*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h> 13*724ba675SRob Herring#include <dt-bindings/power/qcom-rpmpd.h> 14*724ba675SRob Herring#include <dt-bindings/reset/qcom,gcc-msm8974.h> 15*724ba675SRob Herring 16*724ba675SRob Herring/ { 17*724ba675SRob Herring #address-cells = <1>; 18*724ba675SRob Herring #size-cells = <1>; 19*724ba675SRob Herring interrupt-parent = <&intc>; 20*724ba675SRob Herring 21*724ba675SRob Herring chosen { }; 22*724ba675SRob Herring 23*724ba675SRob Herring memory@0 { 24*724ba675SRob Herring device_type = "memory"; 25*724ba675SRob Herring reg = <0x0 0x0>; 26*724ba675SRob Herring }; 27*724ba675SRob Herring 28*724ba675SRob Herring clocks { 29*724ba675SRob Herring xo_board: xo_board { 30*724ba675SRob Herring compatible = "fixed-clock"; 31*724ba675SRob Herring #clock-cells = <0>; 32*724ba675SRob Herring clock-frequency = <19200000>; 33*724ba675SRob Herring }; 34*724ba675SRob Herring 35*724ba675SRob Herring sleep_clk: sleep_clk { 36*724ba675SRob Herring compatible = "fixed-clock"; 37*724ba675SRob Herring #clock-cells = <0>; 38*724ba675SRob Herring clock-frequency = <32768>; 39*724ba675SRob Herring }; 40*724ba675SRob Herring }; 41*724ba675SRob Herring 42*724ba675SRob Herring firmware { 43*724ba675SRob Herring scm { 44*724ba675SRob Herring compatible = "qcom,scm-msm8226", "qcom,scm"; 45*724ba675SRob Herring clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 46*724ba675SRob Herring clock-names = "core", "bus", "iface"; 47*724ba675SRob Herring }; 48*724ba675SRob Herring }; 49*724ba675SRob Herring 50*724ba675SRob Herring pmu { 51*724ba675SRob Herring compatible = "arm,cortex-a7-pmu"; 52*724ba675SRob Herring interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 53*724ba675SRob Herring IRQ_TYPE_LEVEL_HIGH)>; 54*724ba675SRob Herring }; 55*724ba675SRob Herring 56*724ba675SRob Herring reserved-memory { 57*724ba675SRob Herring #address-cells = <1>; 58*724ba675SRob Herring #size-cells = <1>; 59*724ba675SRob Herring ranges; 60*724ba675SRob Herring 61*724ba675SRob Herring smem_region: smem@3000000 { 62*724ba675SRob Herring reg = <0x3000000 0x100000>; 63*724ba675SRob Herring no-map; 64*724ba675SRob Herring }; 65*724ba675SRob Herring 66*724ba675SRob Herring adsp_region: adsp@dc00000 { 67*724ba675SRob Herring reg = <0x0dc00000 0x1900000>; 68*724ba675SRob Herring no-map; 69*724ba675SRob Herring }; 70*724ba675SRob Herring }; 71*724ba675SRob Herring 72*724ba675SRob Herring smd { 73*724ba675SRob Herring compatible = "qcom,smd"; 74*724ba675SRob Herring 75*724ba675SRob Herring rpm { 76*724ba675SRob Herring interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 77*724ba675SRob Herring qcom,ipc = <&apcs 8 0>; 78*724ba675SRob Herring qcom,smd-edge = <15>; 79*724ba675SRob Herring 80*724ba675SRob Herring rpm_requests: rpm-requests { 81*724ba675SRob Herring compatible = "qcom,rpm-msm8226"; 82*724ba675SRob Herring qcom,smd-channels = "rpm_requests"; 83*724ba675SRob Herring 84*724ba675SRob Herring rpmcc: clock-controller { 85*724ba675SRob Herring compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc"; 86*724ba675SRob Herring #clock-cells = <1>; 87*724ba675SRob Herring clocks = <&xo_board>; 88*724ba675SRob Herring clock-names = "xo"; 89*724ba675SRob Herring }; 90*724ba675SRob Herring 91*724ba675SRob Herring rpmpd: power-controller { 92*724ba675SRob Herring compatible = "qcom,msm8226-rpmpd"; 93*724ba675SRob Herring #power-domain-cells = <1>; 94*724ba675SRob Herring operating-points-v2 = <&rpmpd_opp_table>; 95*724ba675SRob Herring 96*724ba675SRob Herring rpmpd_opp_table: opp-table { 97*724ba675SRob Herring compatible = "operating-points-v2"; 98*724ba675SRob Herring 99*724ba675SRob Herring rpmpd_opp_ret: opp1 { 100*724ba675SRob Herring opp-level = <1>; 101*724ba675SRob Herring }; 102*724ba675SRob Herring rpmpd_opp_svs_krait: opp2 { 103*724ba675SRob Herring opp-level = <2>; 104*724ba675SRob Herring }; 105*724ba675SRob Herring rpmpd_opp_svs_soc: opp3 { 106*724ba675SRob Herring opp-level = <3>; 107*724ba675SRob Herring }; 108*724ba675SRob Herring rpmpd_opp_nom: opp4 { 109*724ba675SRob Herring opp-level = <4>; 110*724ba675SRob Herring }; 111*724ba675SRob Herring rpmpd_opp_turbo: opp5 { 112*724ba675SRob Herring opp-level = <5>; 113*724ba675SRob Herring }; 114*724ba675SRob Herring rpmpd_opp_super_turbo: opp6 { 115*724ba675SRob Herring opp-level = <6>; 116*724ba675SRob Herring }; 117*724ba675SRob Herring }; 118*724ba675SRob Herring }; 119*724ba675SRob Herring }; 120*724ba675SRob Herring }; 121*724ba675SRob Herring }; 122*724ba675SRob Herring 123*724ba675SRob Herring smem { 124*724ba675SRob Herring compatible = "qcom,smem"; 125*724ba675SRob Herring 126*724ba675SRob Herring memory-region = <&smem_region>; 127*724ba675SRob Herring qcom,rpm-msg-ram = <&rpm_msg_ram>; 128*724ba675SRob Herring 129*724ba675SRob Herring hwlocks = <&tcsr_mutex 3>; 130*724ba675SRob Herring }; 131*724ba675SRob Herring 132*724ba675SRob Herring smp2p-adsp { 133*724ba675SRob Herring compatible = "qcom,smp2p"; 134*724ba675SRob Herring qcom,smem = <443>, <429>; 135*724ba675SRob Herring 136*724ba675SRob Herring interrupt-parent = <&intc>; 137*724ba675SRob Herring interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 138*724ba675SRob Herring 139*724ba675SRob Herring qcom,ipc = <&apcs 8 10>; 140*724ba675SRob Herring 141*724ba675SRob Herring qcom,local-pid = <0>; 142*724ba675SRob Herring qcom,remote-pid = <2>; 143*724ba675SRob Herring 144*724ba675SRob Herring adsp_smp2p_out: master-kernel { 145*724ba675SRob Herring qcom,entry-name = "master-kernel"; 146*724ba675SRob Herring #qcom,smem-state-cells = <1>; 147*724ba675SRob Herring }; 148*724ba675SRob Herring 149*724ba675SRob Herring adsp_smp2p_in: slave-kernel { 150*724ba675SRob Herring qcom,entry-name = "slave-kernel"; 151*724ba675SRob Herring 152*724ba675SRob Herring interrupt-controller; 153*724ba675SRob Herring #interrupt-cells = <2>; 154*724ba675SRob Herring }; 155*724ba675SRob Herring }; 156*724ba675SRob Herring 157*724ba675SRob Herring soc: soc { 158*724ba675SRob Herring compatible = "simple-bus"; 159*724ba675SRob Herring #address-cells = <1>; 160*724ba675SRob Herring #size-cells = <1>; 161*724ba675SRob Herring ranges; 162*724ba675SRob Herring 163*724ba675SRob Herring intc: interrupt-controller@f9000000 { 164*724ba675SRob Herring compatible = "qcom,msm-qgic2"; 165*724ba675SRob Herring reg = <0xf9000000 0x1000>, 166*724ba675SRob Herring <0xf9002000 0x1000>; 167*724ba675SRob Herring interrupt-controller; 168*724ba675SRob Herring #interrupt-cells = <3>; 169*724ba675SRob Herring }; 170*724ba675SRob Herring 171*724ba675SRob Herring apcs: syscon@f9011000 { 172*724ba675SRob Herring compatible = "syscon"; 173*724ba675SRob Herring reg = <0xf9011000 0x1000>; 174*724ba675SRob Herring }; 175*724ba675SRob Herring 176*724ba675SRob Herring sdhc_1: mmc@f9824900 { 177*724ba675SRob Herring compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 178*724ba675SRob Herring reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 179*724ba675SRob Herring reg-names = "hc", "core"; 180*724ba675SRob Herring interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 181*724ba675SRob Herring <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 182*724ba675SRob Herring interrupt-names = "hc_irq", "pwr_irq"; 183*724ba675SRob Herring clocks = <&gcc GCC_SDCC1_AHB_CLK>, 184*724ba675SRob Herring <&gcc GCC_SDCC1_APPS_CLK>, 185*724ba675SRob Herring <&rpmcc RPM_SMD_XO_CLK_SRC>; 186*724ba675SRob Herring clock-names = "iface", "core", "xo"; 187*724ba675SRob Herring pinctrl-names = "default"; 188*724ba675SRob Herring pinctrl-0 = <&sdhc1_default_state>; 189*724ba675SRob Herring status = "disabled"; 190*724ba675SRob Herring }; 191*724ba675SRob Herring 192*724ba675SRob Herring sdhc_2: mmc@f98a4900 { 193*724ba675SRob Herring compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 194*724ba675SRob Herring reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 195*724ba675SRob Herring reg-names = "hc", "core"; 196*724ba675SRob Herring interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 197*724ba675SRob Herring <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 198*724ba675SRob Herring interrupt-names = "hc_irq", "pwr_irq"; 199*724ba675SRob Herring clocks = <&gcc GCC_SDCC2_AHB_CLK>, 200*724ba675SRob Herring <&gcc GCC_SDCC2_APPS_CLK>, 201*724ba675SRob Herring <&rpmcc RPM_SMD_XO_CLK_SRC>; 202*724ba675SRob Herring clock-names = "iface", "core", "xo"; 203*724ba675SRob Herring pinctrl-names = "default"; 204*724ba675SRob Herring pinctrl-0 = <&sdhc2_default_state>; 205*724ba675SRob Herring status = "disabled"; 206*724ba675SRob Herring }; 207*724ba675SRob Herring 208*724ba675SRob Herring sdhc_3: mmc@f9864900 { 209*724ba675SRob Herring compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 210*724ba675SRob Herring reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 211*724ba675SRob Herring reg-names = "hc", "core"; 212*724ba675SRob Herring interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 213*724ba675SRob Herring <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 214*724ba675SRob Herring interrupt-names = "hc_irq", "pwr_irq"; 215*724ba675SRob Herring clocks = <&gcc GCC_SDCC3_AHB_CLK>, 216*724ba675SRob Herring <&gcc GCC_SDCC3_APPS_CLK>, 217*724ba675SRob Herring <&rpmcc RPM_SMD_XO_CLK_SRC>; 218*724ba675SRob Herring clock-names = "iface", "core", "xo"; 219*724ba675SRob Herring pinctrl-names = "default"; 220*724ba675SRob Herring pinctrl-0 = <&sdhc3_default_state>; 221*724ba675SRob Herring status = "disabled"; 222*724ba675SRob Herring }; 223*724ba675SRob Herring 224*724ba675SRob Herring blsp1_uart1: serial@f991d000 { 225*724ba675SRob Herring compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 226*724ba675SRob Herring reg = <0xf991d000 0x1000>; 227*724ba675SRob Herring interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 228*724ba675SRob Herring clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 229*724ba675SRob Herring clock-names = "core", "iface"; 230*724ba675SRob Herring status = "disabled"; 231*724ba675SRob Herring }; 232*724ba675SRob Herring 233*724ba675SRob Herring blsp1_uart3: serial@f991f000 { 234*724ba675SRob Herring compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 235*724ba675SRob Herring reg = <0xf991f000 0x1000>; 236*724ba675SRob Herring interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 237*724ba675SRob Herring clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 238*724ba675SRob Herring clock-names = "core", "iface"; 239*724ba675SRob Herring status = "disabled"; 240*724ba675SRob Herring }; 241*724ba675SRob Herring 242*724ba675SRob Herring blsp1_uart4: serial@f9920000 { 243*724ba675SRob Herring compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 244*724ba675SRob Herring reg = <0xf9920000 0x1000>; 245*724ba675SRob Herring interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 246*724ba675SRob Herring clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 247*724ba675SRob Herring clock-names = "core", "iface"; 248*724ba675SRob Herring status = "disabled"; 249*724ba675SRob Herring }; 250*724ba675SRob Herring 251*724ba675SRob Herring blsp1_i2c1: i2c@f9923000 { 252*724ba675SRob Herring status = "disabled"; 253*724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 254*724ba675SRob Herring reg = <0xf9923000 0x1000>; 255*724ba675SRob Herring interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 256*724ba675SRob Herring clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 257*724ba675SRob Herring clock-names = "core", "iface"; 258*724ba675SRob Herring pinctrl-names = "default"; 259*724ba675SRob Herring pinctrl-0 = <&blsp1_i2c1_pins>; 260*724ba675SRob Herring #address-cells = <1>; 261*724ba675SRob Herring #size-cells = <0>; 262*724ba675SRob Herring }; 263*724ba675SRob Herring 264*724ba675SRob Herring blsp1_i2c2: i2c@f9924000 { 265*724ba675SRob Herring status = "disabled"; 266*724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 267*724ba675SRob Herring reg = <0xf9924000 0x1000>; 268*724ba675SRob Herring interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 269*724ba675SRob Herring clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 270*724ba675SRob Herring clock-names = "core", "iface"; 271*724ba675SRob Herring pinctrl-names = "default"; 272*724ba675SRob Herring pinctrl-0 = <&blsp1_i2c2_pins>; 273*724ba675SRob Herring #address-cells = <1>; 274*724ba675SRob Herring #size-cells = <0>; 275*724ba675SRob Herring }; 276*724ba675SRob Herring 277*724ba675SRob Herring blsp1_i2c3: i2c@f9925000 { 278*724ba675SRob Herring status = "disabled"; 279*724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 280*724ba675SRob Herring reg = <0xf9925000 0x1000>; 281*724ba675SRob Herring interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 282*724ba675SRob Herring clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 283*724ba675SRob Herring clock-names = "core", "iface"; 284*724ba675SRob Herring pinctrl-names = "default"; 285*724ba675SRob Herring pinctrl-0 = <&blsp1_i2c3_pins>; 286*724ba675SRob Herring #address-cells = <1>; 287*724ba675SRob Herring #size-cells = <0>; 288*724ba675SRob Herring }; 289*724ba675SRob Herring 290*724ba675SRob Herring blsp1_i2c4: i2c@f9926000 { 291*724ba675SRob Herring status = "disabled"; 292*724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 293*724ba675SRob Herring reg = <0xf9926000 0x1000>; 294*724ba675SRob Herring interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 295*724ba675SRob Herring clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 296*724ba675SRob Herring clock-names = "core", "iface"; 297*724ba675SRob Herring pinctrl-names = "default"; 298*724ba675SRob Herring pinctrl-0 = <&blsp1_i2c4_pins>; 299*724ba675SRob Herring #address-cells = <1>; 300*724ba675SRob Herring #size-cells = <0>; 301*724ba675SRob Herring }; 302*724ba675SRob Herring 303*724ba675SRob Herring blsp1_i2c5: i2c@f9927000 { 304*724ba675SRob Herring status = "disabled"; 305*724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 306*724ba675SRob Herring reg = <0xf9927000 0x1000>; 307*724ba675SRob Herring interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 308*724ba675SRob Herring clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 309*724ba675SRob Herring clock-names = "core", "iface"; 310*724ba675SRob Herring pinctrl-names = "default"; 311*724ba675SRob Herring pinctrl-0 = <&blsp1_i2c5_pins>; 312*724ba675SRob Herring #address-cells = <1>; 313*724ba675SRob Herring #size-cells = <0>; 314*724ba675SRob Herring }; 315*724ba675SRob Herring 316*724ba675SRob Herring cci: cci@fda0c000 { 317*724ba675SRob Herring compatible = "qcom,msm8226-cci"; 318*724ba675SRob Herring #address-cells = <1>; 319*724ba675SRob Herring #size-cells = <0>; 320*724ba675SRob Herring reg = <0xfda0c000 0x1000>; 321*724ba675SRob Herring interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 322*724ba675SRob Herring clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 323*724ba675SRob Herring <&mmcc CAMSS_CCI_CCI_AHB_CLK>, 324*724ba675SRob Herring <&mmcc CAMSS_CCI_CCI_CLK>; 325*724ba675SRob Herring clock-names = "camss_top_ahb", 326*724ba675SRob Herring "cci_ahb", 327*724ba675SRob Herring "cci"; 328*724ba675SRob Herring 329*724ba675SRob Herring pinctrl-names = "default", "sleep"; 330*724ba675SRob Herring pinctrl-0 = <&cci_default>; 331*724ba675SRob Herring pinctrl-1 = <&cci_sleep>; 332*724ba675SRob Herring 333*724ba675SRob Herring status = "disabled"; 334*724ba675SRob Herring 335*724ba675SRob Herring cci_i2c0: i2c-bus@0 { 336*724ba675SRob Herring reg = <0>; 337*724ba675SRob Herring clock-frequency = <400000>; 338*724ba675SRob Herring #address-cells = <1>; 339*724ba675SRob Herring #size-cells = <0>; 340*724ba675SRob Herring }; 341*724ba675SRob Herring }; 342*724ba675SRob Herring 343*724ba675SRob Herring usb: usb@f9a55000 { 344*724ba675SRob Herring compatible = "qcom,ci-hdrc"; 345*724ba675SRob Herring reg = <0xf9a55000 0x200>, 346*724ba675SRob Herring <0xf9a55200 0x200>; 347*724ba675SRob Herring interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 348*724ba675SRob Herring clocks = <&gcc GCC_USB_HS_AHB_CLK>, 349*724ba675SRob Herring <&gcc GCC_USB_HS_SYSTEM_CLK>; 350*724ba675SRob Herring clock-names = "iface", "core"; 351*724ba675SRob Herring assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 352*724ba675SRob Herring assigned-clock-rates = <75000000>; 353*724ba675SRob Herring resets = <&gcc GCC_USB_HS_BCR>; 354*724ba675SRob Herring reset-names = "core"; 355*724ba675SRob Herring phy_type = "ulpi"; 356*724ba675SRob Herring dr_mode = "otg"; 357*724ba675SRob Herring hnp-disable; 358*724ba675SRob Herring srp-disable; 359*724ba675SRob Herring adp-disable; 360*724ba675SRob Herring ahb-burst-config = <0>; 361*724ba675SRob Herring phy-names = "usb-phy"; 362*724ba675SRob Herring phys = <&usb_hs_phy>; 363*724ba675SRob Herring status = "disabled"; 364*724ba675SRob Herring #reset-cells = <1>; 365*724ba675SRob Herring 366*724ba675SRob Herring ulpi { 367*724ba675SRob Herring usb_hs_phy: phy { 368*724ba675SRob Herring compatible = "qcom,usb-hs-phy-msm8226", 369*724ba675SRob Herring "qcom,usb-hs-phy"; 370*724ba675SRob Herring #phy-cells = <0>; 371*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 372*724ba675SRob Herring <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 373*724ba675SRob Herring clock-names = "ref", "sleep"; 374*724ba675SRob Herring resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 375*724ba675SRob Herring reset-names = "phy", "por"; 376*724ba675SRob Herring qcom,init-seq = /bits/ 8 <0x0 0x44 377*724ba675SRob Herring 0x1 0x68 0x2 0x24 0x3 0x13>; 378*724ba675SRob Herring }; 379*724ba675SRob Herring }; 380*724ba675SRob Herring }; 381*724ba675SRob Herring 382*724ba675SRob Herring gcc: clock-controller@fc400000 { 383*724ba675SRob Herring compatible = "qcom,gcc-msm8226"; 384*724ba675SRob Herring reg = <0xfc400000 0x4000>; 385*724ba675SRob Herring #clock-cells = <1>; 386*724ba675SRob Herring #reset-cells = <1>; 387*724ba675SRob Herring #power-domain-cells = <1>; 388*724ba675SRob Herring 389*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 390*724ba675SRob Herring <&sleep_clk>; 391*724ba675SRob Herring clock-names = "xo", 392*724ba675SRob Herring "sleep_clk"; 393*724ba675SRob Herring }; 394*724ba675SRob Herring 395*724ba675SRob Herring mmcc: clock-controller@fd8c0000 { 396*724ba675SRob Herring compatible = "qcom,mmcc-msm8226"; 397*724ba675SRob Herring reg = <0xfd8c0000 0x6000>; 398*724ba675SRob Herring #clock-cells = <1>; 399*724ba675SRob Herring #reset-cells = <1>; 400*724ba675SRob Herring #power-domain-cells = <1>; 401*724ba675SRob Herring 402*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 403*724ba675SRob Herring <&gcc GCC_MMSS_GPLL0_CLK_SRC>, 404*724ba675SRob Herring <&gcc GPLL0_VOTE>, 405*724ba675SRob Herring <&gcc GPLL1_VOTE>, 406*724ba675SRob Herring <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 407*724ba675SRob Herring <0>, 408*724ba675SRob Herring <0>; 409*724ba675SRob Herring clock-names = "xo", 410*724ba675SRob Herring "mmss_gpll0_vote", 411*724ba675SRob Herring "gpll0_vote", 412*724ba675SRob Herring "gpll1_vote", 413*724ba675SRob Herring "gfx3d_clk_src", 414*724ba675SRob Herring "dsi0pll", 415*724ba675SRob Herring "dsi0pllbyte"; 416*724ba675SRob Herring }; 417*724ba675SRob Herring 418*724ba675SRob Herring tlmm: pinctrl@fd510000 { 419*724ba675SRob Herring compatible = "qcom,msm8226-pinctrl"; 420*724ba675SRob Herring reg = <0xfd510000 0x4000>; 421*724ba675SRob Herring gpio-controller; 422*724ba675SRob Herring #gpio-cells = <2>; 423*724ba675SRob Herring gpio-ranges = <&tlmm 0 0 117>; 424*724ba675SRob Herring interrupt-controller; 425*724ba675SRob Herring #interrupt-cells = <2>; 426*724ba675SRob Herring interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 427*724ba675SRob Herring 428*724ba675SRob Herring blsp1_i2c1_pins: blsp1-i2c1-state { 429*724ba675SRob Herring pins = "gpio2", "gpio3"; 430*724ba675SRob Herring function = "blsp_i2c1"; 431*724ba675SRob Herring drive-strength = <2>; 432*724ba675SRob Herring bias-disable; 433*724ba675SRob Herring }; 434*724ba675SRob Herring 435*724ba675SRob Herring blsp1_i2c2_pins: blsp1-i2c2-state { 436*724ba675SRob Herring pins = "gpio6", "gpio7"; 437*724ba675SRob Herring function = "blsp_i2c2"; 438*724ba675SRob Herring drive-strength = <2>; 439*724ba675SRob Herring bias-disable; 440*724ba675SRob Herring }; 441*724ba675SRob Herring 442*724ba675SRob Herring blsp1_i2c3_pins: blsp1-i2c3-state { 443*724ba675SRob Herring pins = "gpio10", "gpio11"; 444*724ba675SRob Herring function = "blsp_i2c3"; 445*724ba675SRob Herring drive-strength = <2>; 446*724ba675SRob Herring bias-disable; 447*724ba675SRob Herring }; 448*724ba675SRob Herring 449*724ba675SRob Herring blsp1_i2c4_pins: blsp1-i2c4-state { 450*724ba675SRob Herring pins = "gpio14", "gpio15"; 451*724ba675SRob Herring function = "blsp_i2c4"; 452*724ba675SRob Herring drive-strength = <2>; 453*724ba675SRob Herring bias-disable; 454*724ba675SRob Herring }; 455*724ba675SRob Herring 456*724ba675SRob Herring blsp1_i2c5_pins: blsp1-i2c5-state { 457*724ba675SRob Herring pins = "gpio18", "gpio19"; 458*724ba675SRob Herring function = "blsp_i2c5"; 459*724ba675SRob Herring drive-strength = <2>; 460*724ba675SRob Herring bias-disable; 461*724ba675SRob Herring }; 462*724ba675SRob Herring 463*724ba675SRob Herring cci_default: cci-default-state { 464*724ba675SRob Herring pins = "gpio29", "gpio30"; 465*724ba675SRob Herring function = "cci_i2c0"; 466*724ba675SRob Herring 467*724ba675SRob Herring drive-strength = <2>; 468*724ba675SRob Herring bias-disable; 469*724ba675SRob Herring }; 470*724ba675SRob Herring 471*724ba675SRob Herring cci_sleep: cci-sleep-state { 472*724ba675SRob Herring pins = "gpio29", "gpio30"; 473*724ba675SRob Herring function = "gpio"; 474*724ba675SRob Herring 475*724ba675SRob Herring drive-strength = <2>; 476*724ba675SRob Herring bias-disable; 477*724ba675SRob Herring }; 478*724ba675SRob Herring 479*724ba675SRob Herring sdhc1_default_state: sdhc1-default-state { 480*724ba675SRob Herring clk-pins { 481*724ba675SRob Herring pins = "sdc1_clk"; 482*724ba675SRob Herring drive-strength = <10>; 483*724ba675SRob Herring bias-disable; 484*724ba675SRob Herring }; 485*724ba675SRob Herring 486*724ba675SRob Herring cmd-data-pins { 487*724ba675SRob Herring pins = "sdc1_cmd", "sdc1_data"; 488*724ba675SRob Herring drive-strength = <10>; 489*724ba675SRob Herring bias-pull-up; 490*724ba675SRob Herring }; 491*724ba675SRob Herring }; 492*724ba675SRob Herring 493*724ba675SRob Herring sdhc2_default_state: sdhc2-default-state { 494*724ba675SRob Herring clk-pins { 495*724ba675SRob Herring pins = "sdc2_clk"; 496*724ba675SRob Herring drive-strength = <10>; 497*724ba675SRob Herring bias-disable; 498*724ba675SRob Herring }; 499*724ba675SRob Herring 500*724ba675SRob Herring cmd-data-pins { 501*724ba675SRob Herring pins = "sdc2_cmd", "sdc2_data"; 502*724ba675SRob Herring drive-strength = <10>; 503*724ba675SRob Herring bias-pull-up; 504*724ba675SRob Herring }; 505*724ba675SRob Herring }; 506*724ba675SRob Herring 507*724ba675SRob Herring sdhc3_default_state: sdhc3-default-state { 508*724ba675SRob Herring clk-pins { 509*724ba675SRob Herring pins = "gpio44"; 510*724ba675SRob Herring function = "sdc3"; 511*724ba675SRob Herring drive-strength = <8>; 512*724ba675SRob Herring bias-disable; 513*724ba675SRob Herring }; 514*724ba675SRob Herring 515*724ba675SRob Herring cmd-pins { 516*724ba675SRob Herring pins = "gpio43"; 517*724ba675SRob Herring function = "sdc3"; 518*724ba675SRob Herring drive-strength = <8>; 519*724ba675SRob Herring bias-pull-up; 520*724ba675SRob Herring }; 521*724ba675SRob Herring 522*724ba675SRob Herring data-pins { 523*724ba675SRob Herring pins = "gpio39", "gpio40", "gpio41", "gpio42"; 524*724ba675SRob Herring function = "sdc3"; 525*724ba675SRob Herring drive-strength = <8>; 526*724ba675SRob Herring bias-pull-up; 527*724ba675SRob Herring }; 528*724ba675SRob Herring }; 529*724ba675SRob Herring }; 530*724ba675SRob Herring 531*724ba675SRob Herring tsens: thermal-sensor@fc4a9000 { 532*724ba675SRob Herring compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1"; 533*724ba675SRob Herring reg = <0xfc4a9000 0x1000>, /* TM */ 534*724ba675SRob Herring <0xfc4a8000 0x1000>; /* SROT */ 535*724ba675SRob Herring nvmem-cells = <&tsens_mode>, 536*724ba675SRob Herring <&tsens_base1>, <&tsens_base2>, 537*724ba675SRob Herring <&tsens_s0_p1>, <&tsens_s0_p2>, 538*724ba675SRob Herring <&tsens_s1_p1>, <&tsens_s1_p2>, 539*724ba675SRob Herring <&tsens_s2_p1>, <&tsens_s2_p2>, 540*724ba675SRob Herring <&tsens_s3_p1>, <&tsens_s3_p2>, 541*724ba675SRob Herring <&tsens_s4_p1>, <&tsens_s4_p2>, 542*724ba675SRob Herring <&tsens_s5_p1>, <&tsens_s5_p2>, 543*724ba675SRob Herring <&tsens_s6_p1>, <&tsens_s6_p2>; 544*724ba675SRob Herring nvmem-cell-names = "mode", 545*724ba675SRob Herring "base1", "base2", 546*724ba675SRob Herring "s0_p1", "s0_p2", 547*724ba675SRob Herring "s1_p1", "s1_p2", 548*724ba675SRob Herring "s2_p1", "s2_p2", 549*724ba675SRob Herring "s3_p1", "s3_p2", 550*724ba675SRob Herring "s4_p1", "s4_p2", 551*724ba675SRob Herring "s5_p1", "s5_p2", 552*724ba675SRob Herring "s6_p1", "s6_p2"; 553*724ba675SRob Herring #qcom,sensors = <6>; 554*724ba675SRob Herring interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 555*724ba675SRob Herring interrupt-names = "uplow"; 556*724ba675SRob Herring #thermal-sensor-cells = <1>; 557*724ba675SRob Herring }; 558*724ba675SRob Herring 559*724ba675SRob Herring restart@fc4ab000 { 560*724ba675SRob Herring compatible = "qcom,pshold"; 561*724ba675SRob Herring reg = <0xfc4ab000 0x4>; 562*724ba675SRob Herring }; 563*724ba675SRob Herring 564*724ba675SRob Herring qfprom: qfprom@fc4bc000 { 565*724ba675SRob Herring compatible = "qcom,msm8226-qfprom", "qcom,qfprom"; 566*724ba675SRob Herring reg = <0xfc4bc000 0x1000>; 567*724ba675SRob Herring #address-cells = <1>; 568*724ba675SRob Herring #size-cells = <1>; 569*724ba675SRob Herring 570*724ba675SRob Herring tsens_base1: base1@1c1 { 571*724ba675SRob Herring reg = <0x1c1 0x2>; 572*724ba675SRob Herring bits = <5 8>; 573*724ba675SRob Herring }; 574*724ba675SRob Herring 575*724ba675SRob Herring tsens_s0_p1: s0-p1@1c2 { 576*724ba675SRob Herring reg = <0x1c2 0x2>; 577*724ba675SRob Herring bits = <5 6>; 578*724ba675SRob Herring }; 579*724ba675SRob Herring 580*724ba675SRob Herring tsens_s1_p1: s1-p1@1c4 { 581*724ba675SRob Herring reg = <0x1c4 0x1>; 582*724ba675SRob Herring bits = <0 6>; 583*724ba675SRob Herring }; 584*724ba675SRob Herring 585*724ba675SRob Herring tsens_s2_p1: s2-p1@1c4 { 586*724ba675SRob Herring reg = <0x1c4 0x2>; 587*724ba675SRob Herring bits = <6 6>; 588*724ba675SRob Herring }; 589*724ba675SRob Herring 590*724ba675SRob Herring tsens_s3_p1: s3-p1@1c5 { 591*724ba675SRob Herring reg = <0x1c5 0x2>; 592*724ba675SRob Herring bits = <4 6>; 593*724ba675SRob Herring }; 594*724ba675SRob Herring 595*724ba675SRob Herring tsens_s4_p1: s4-p1@1c6 { 596*724ba675SRob Herring reg = <0x1c6 0x1>; 597*724ba675SRob Herring bits = <2 6>; 598*724ba675SRob Herring }; 599*724ba675SRob Herring 600*724ba675SRob Herring tsens_s5_p1: s5-p1@1c7 { 601*724ba675SRob Herring reg = <0x1c7 0x1>; 602*724ba675SRob Herring bits = <0 6>; 603*724ba675SRob Herring }; 604*724ba675SRob Herring 605*724ba675SRob Herring tsens_s6_p1: s6-p1@1ca { 606*724ba675SRob Herring reg = <0x1ca 0x2>; 607*724ba675SRob Herring bits = <4 6>; 608*724ba675SRob Herring }; 609*724ba675SRob Herring 610*724ba675SRob Herring tsens_base2: base2@1cc { 611*724ba675SRob Herring reg = <0x1cc 0x1>; 612*724ba675SRob Herring bits = <0 8>; 613*724ba675SRob Herring }; 614*724ba675SRob Herring 615*724ba675SRob Herring tsens_s0_p2: s0-p2@1cd { 616*724ba675SRob Herring reg = <0x1cd 0x1>; 617*724ba675SRob Herring bits = <0 6>; 618*724ba675SRob Herring }; 619*724ba675SRob Herring 620*724ba675SRob Herring tsens_s1_p2: s1-p2@1cd { 621*724ba675SRob Herring reg = <0x1cd 0x2>; 622*724ba675SRob Herring bits = <6 6>; 623*724ba675SRob Herring }; 624*724ba675SRob Herring 625*724ba675SRob Herring tsens_s2_p2: s2-p2@1ce { 626*724ba675SRob Herring reg = <0x1ce 0x2>; 627*724ba675SRob Herring bits = <4 6>; 628*724ba675SRob Herring }; 629*724ba675SRob Herring 630*724ba675SRob Herring tsens_s3_p2: s3-p2@1cf { 631*724ba675SRob Herring reg = <0x1cf 0x1>; 632*724ba675SRob Herring bits = <2 6>; 633*724ba675SRob Herring }; 634*724ba675SRob Herring 635*724ba675SRob Herring tsens_s4_p2: s4-p2@446 { 636*724ba675SRob Herring reg = <0x446 0x2>; 637*724ba675SRob Herring bits = <4 6>; 638*724ba675SRob Herring }; 639*724ba675SRob Herring 640*724ba675SRob Herring tsens_s5_p2: s5-p2@447 { 641*724ba675SRob Herring reg = <0x447 0x1>; 642*724ba675SRob Herring bits = <2 6>; 643*724ba675SRob Herring }; 644*724ba675SRob Herring 645*724ba675SRob Herring tsens_s6_p2: s6-p2@44e { 646*724ba675SRob Herring reg = <0x44e 0x1>; 647*724ba675SRob Herring bits = <1 6>; 648*724ba675SRob Herring }; 649*724ba675SRob Herring 650*724ba675SRob Herring tsens_mode: mode@44f { 651*724ba675SRob Herring reg = <0x44f 0x1>; 652*724ba675SRob Herring bits = <5 3>; 653*724ba675SRob Herring }; 654*724ba675SRob Herring }; 655*724ba675SRob Herring 656*724ba675SRob Herring spmi_bus: spmi@fc4cf000 { 657*724ba675SRob Herring compatible = "qcom,spmi-pmic-arb"; 658*724ba675SRob Herring reg-names = "core", "intr", "cnfg"; 659*724ba675SRob Herring reg = <0xfc4cf000 0x1000>, 660*724ba675SRob Herring <0xfc4cb000 0x1000>, 661*724ba675SRob Herring <0xfc4ca000 0x1000>; 662*724ba675SRob Herring interrupt-names = "periph_irq"; 663*724ba675SRob Herring interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 664*724ba675SRob Herring qcom,ee = <0>; 665*724ba675SRob Herring qcom,channel = <0>; 666*724ba675SRob Herring #address-cells = <2>; 667*724ba675SRob Herring #size-cells = <0>; 668*724ba675SRob Herring interrupt-controller; 669*724ba675SRob Herring #interrupt-cells = <4>; 670*724ba675SRob Herring }; 671*724ba675SRob Herring 672*724ba675SRob Herring rng@f9bff000 { 673*724ba675SRob Herring compatible = "qcom,prng"; 674*724ba675SRob Herring reg = <0xf9bff000 0x200>; 675*724ba675SRob Herring clocks = <&gcc GCC_PRNG_AHB_CLK>; 676*724ba675SRob Herring clock-names = "core"; 677*724ba675SRob Herring }; 678*724ba675SRob Herring 679*724ba675SRob Herring timer@f9020000 { 680*724ba675SRob Herring compatible = "arm,armv7-timer-mem"; 681*724ba675SRob Herring reg = <0xf9020000 0x1000>; 682*724ba675SRob Herring #address-cells = <1>; 683*724ba675SRob Herring #size-cells = <1>; 684*724ba675SRob Herring ranges; 685*724ba675SRob Herring 686*724ba675SRob Herring frame@f9021000 { 687*724ba675SRob Herring frame-number = <0>; 688*724ba675SRob Herring interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 689*724ba675SRob Herring <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 690*724ba675SRob Herring reg = <0xf9021000 0x1000>, 691*724ba675SRob Herring <0xf9022000 0x1000>; 692*724ba675SRob Herring }; 693*724ba675SRob Herring 694*724ba675SRob Herring frame@f9023000 { 695*724ba675SRob Herring frame-number = <1>; 696*724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 697*724ba675SRob Herring reg = <0xf9023000 0x1000>; 698*724ba675SRob Herring status = "disabled"; 699*724ba675SRob Herring }; 700*724ba675SRob Herring 701*724ba675SRob Herring frame@f9024000 { 702*724ba675SRob Herring frame-number = <2>; 703*724ba675SRob Herring interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 704*724ba675SRob Herring reg = <0xf9024000 0x1000>; 705*724ba675SRob Herring status = "disabled"; 706*724ba675SRob Herring }; 707*724ba675SRob Herring 708*724ba675SRob Herring frame@f9025000 { 709*724ba675SRob Herring frame-number = <3>; 710*724ba675SRob Herring interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 711*724ba675SRob Herring reg = <0xf9025000 0x1000>; 712*724ba675SRob Herring status = "disabled"; 713*724ba675SRob Herring }; 714*724ba675SRob Herring 715*724ba675SRob Herring frame@f9026000 { 716*724ba675SRob Herring frame-number = <4>; 717*724ba675SRob Herring interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 718*724ba675SRob Herring reg = <0xf9026000 0x1000>; 719*724ba675SRob Herring status = "disabled"; 720*724ba675SRob Herring }; 721*724ba675SRob Herring 722*724ba675SRob Herring frame@f9027000 { 723*724ba675SRob Herring frame-number = <5>; 724*724ba675SRob Herring interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 725*724ba675SRob Herring reg = <0xf9027000 0x1000>; 726*724ba675SRob Herring status = "disabled"; 727*724ba675SRob Herring }; 728*724ba675SRob Herring 729*724ba675SRob Herring frame@f9028000 { 730*724ba675SRob Herring frame-number = <6>; 731*724ba675SRob Herring interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 732*724ba675SRob Herring reg = <0xf9028000 0x1000>; 733*724ba675SRob Herring status = "disabled"; 734*724ba675SRob Herring }; 735*724ba675SRob Herring }; 736*724ba675SRob Herring 737*724ba675SRob Herring sram@fc190000 { 738*724ba675SRob Herring compatible = "qcom,msm8226-rpm-stats"; 739*724ba675SRob Herring reg = <0xfc190000 0x10000>; 740*724ba675SRob Herring }; 741*724ba675SRob Herring 742*724ba675SRob Herring rpm_msg_ram: sram@fc428000 { 743*724ba675SRob Herring compatible = "qcom,rpm-msg-ram"; 744*724ba675SRob Herring reg = <0xfc428000 0x4000>; 745*724ba675SRob Herring }; 746*724ba675SRob Herring 747*724ba675SRob Herring tcsr_mutex: hwlock@fd484000 { 748*724ba675SRob Herring compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; 749*724ba675SRob Herring reg = <0xfd484000 0x1000>; 750*724ba675SRob Herring #hwlock-cells = <1>; 751*724ba675SRob Herring }; 752*724ba675SRob Herring 753*724ba675SRob Herring adsp: remoteproc@fe200000 { 754*724ba675SRob Herring compatible = "qcom,msm8226-adsp-pil"; 755*724ba675SRob Herring reg = <0xfe200000 0x100>; 756*724ba675SRob Herring 757*724ba675SRob Herring interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 758*724ba675SRob Herring <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 759*724ba675SRob Herring <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 760*724ba675SRob Herring <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 761*724ba675SRob Herring <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 762*724ba675SRob Herring interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 763*724ba675SRob Herring 764*724ba675SRob Herring power-domains = <&rpmpd MSM8226_VDDCX>; 765*724ba675SRob Herring power-domain-names = "cx"; 766*724ba675SRob Herring 767*724ba675SRob Herring clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 768*724ba675SRob Herring clock-names = "xo"; 769*724ba675SRob Herring 770*724ba675SRob Herring memory-region = <&adsp_region>; 771*724ba675SRob Herring 772*724ba675SRob Herring qcom,smem-states = <&adsp_smp2p_out 0>; 773*724ba675SRob Herring qcom,smem-state-names = "stop"; 774*724ba675SRob Herring 775*724ba675SRob Herring status = "disabled"; 776*724ba675SRob Herring 777*724ba675SRob Herring smd-edge { 778*724ba675SRob Herring interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 779*724ba675SRob Herring 780*724ba675SRob Herring qcom,ipc = <&apcs 8 8>; 781*724ba675SRob Herring qcom,smd-edge = <1>; 782*724ba675SRob Herring 783*724ba675SRob Herring label = "lpass"; 784*724ba675SRob Herring }; 785*724ba675SRob Herring }; 786*724ba675SRob Herring 787*724ba675SRob Herring sram@fe805000 { 788*724ba675SRob Herring compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; 789*724ba675SRob Herring reg = <0xfe805000 0x1000>; 790*724ba675SRob Herring 791*724ba675SRob Herring reboot-mode { 792*724ba675SRob Herring compatible = "syscon-reboot-mode"; 793*724ba675SRob Herring offset = <0x65c>; 794*724ba675SRob Herring 795*724ba675SRob Herring mode-bootloader = <0x77665500>; 796*724ba675SRob Herring mode-normal = <0x77665501>; 797*724ba675SRob Herring mode-recovery = <0x77665502>; 798*724ba675SRob Herring }; 799*724ba675SRob Herring }; 800*724ba675SRob Herring }; 801*724ba675SRob Herring 802*724ba675SRob Herring thermal-zones { 803*724ba675SRob Herring cpu0-thermal { 804*724ba675SRob Herring polling-delay-passive = <250>; 805*724ba675SRob Herring polling-delay = <1000>; 806*724ba675SRob Herring 807*724ba675SRob Herring thermal-sensors = <&tsens 5>; 808*724ba675SRob Herring 809*724ba675SRob Herring trips { 810*724ba675SRob Herring cpu_alert0: trip0 { 811*724ba675SRob Herring temperature = <75000>; 812*724ba675SRob Herring hysteresis = <2000>; 813*724ba675SRob Herring type = "passive"; 814*724ba675SRob Herring }; 815*724ba675SRob Herring 816*724ba675SRob Herring cpu_crit0: trip1 { 817*724ba675SRob Herring temperature = <110000>; 818*724ba675SRob Herring hysteresis = <2000>; 819*724ba675SRob Herring type = "critical"; 820*724ba675SRob Herring }; 821*724ba675SRob Herring }; 822*724ba675SRob Herring }; 823*724ba675SRob Herring 824*724ba675SRob Herring cpu1-thermal { 825*724ba675SRob Herring polling-delay-passive = <250>; 826*724ba675SRob Herring polling-delay = <1000>; 827*724ba675SRob Herring 828*724ba675SRob Herring thermal-sensors = <&tsens 2>; 829*724ba675SRob Herring 830*724ba675SRob Herring trips { 831*724ba675SRob Herring cpu_alert1: trip0 { 832*724ba675SRob Herring temperature = <75000>; 833*724ba675SRob Herring hysteresis = <2000>; 834*724ba675SRob Herring type = "passive"; 835*724ba675SRob Herring }; 836*724ba675SRob Herring 837*724ba675SRob Herring cpu_crit1: trip1 { 838*724ba675SRob Herring temperature = <110000>; 839*724ba675SRob Herring hysteresis = <2000>; 840*724ba675SRob Herring type = "critical"; 841*724ba675SRob Herring }; 842*724ba675SRob Herring }; 843*724ba675SRob Herring }; 844*724ba675SRob Herring }; 845*724ba675SRob Herring 846*724ba675SRob Herring timer { 847*724ba675SRob Herring compatible = "arm,armv7-timer"; 848*724ba675SRob Herring interrupts = <GIC_PPI 2 849*724ba675SRob Herring (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 850*724ba675SRob Herring <GIC_PPI 3 851*724ba675SRob Herring (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 852*724ba675SRob Herring <GIC_PPI 4 853*724ba675SRob Herring (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 854*724ba675SRob Herring <GIC_PPI 1 855*724ba675SRob Herring (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>; 856*724ba675SRob Herring }; 857*724ba675SRob Herring}; 858