1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Device Tree Source for Qualcomm MDM9615 SoC 4 * 5 * Copyright (C) 2016 BayLibre, SAS. 6 * Author : Neil Armstrong <narmstrong@baylibre.com> 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/clock/qcom,gcc-mdm9615.h> 13#include <dt-bindings/clock/qcom,lcc-msm8960.h> 14#include <dt-bindings/reset/qcom,gcc-mdm9615.h> 15#include <dt-bindings/mfd/qcom-rpm.h> 16#include <dt-bindings/soc/qcom,gsbi.h> 17 18/ { 19 #address-cells = <1>; 20 #size-cells = <1>; 21 model = "Qualcomm MDM9615"; 22 compatible = "qcom,mdm9615"; 23 interrupt-parent = <&intc>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 compatible = "arm,cortex-a5"; 31 reg = <0>; 32 device_type = "cpu"; 33 next-level-cache = <&L2>; 34 }; 35 }; 36 37 cpu-pmu { 38 compatible = "arm,cortex-a5-pmu"; 39 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 40 }; 41 42 clocks { 43 cxo_board: cxo_board { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <19200000>; 47 }; 48 }; 49 50 vsdcc_fixed: vsdcc-regulator { 51 compatible = "regulator-fixed"; 52 regulator-name = "SDCC Power"; 53 regulator-min-microvolt = <2700000>; 54 regulator-max-microvolt = <2700000>; 55 regulator-always-on; 56 }; 57 58 soc: soc { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 compatible = "simple-bus"; 63 64 L2: cache-controller@2040000 { 65 compatible = "arm,pl310-cache"; 66 reg = <0x02040000 0x1000>; 67 arm,data-latency = <2 2 0>; 68 cache-unified; 69 cache-level = <2>; 70 }; 71 72 intc: interrupt-controller@2000000 { 73 compatible = "qcom,msm-qgic2"; 74 interrupt-controller; 75 #interrupt-cells = <3>; 76 reg = <0x02000000 0x1000>, 77 <0x02002000 0x1000>; 78 }; 79 80 timer@200a000 { 81 compatible = "qcom,kpss-wdt-mdm9615", "qcom,kpss-timer", 82 "qcom,msm-timer"; 83 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>, 84 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>, 85 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>; 86 reg = <0x0200a000 0x100>; 87 clock-frequency = <27000000>; 88 cpu-offset = <0x80000>; 89 }; 90 91 msmgpio: pinctrl@800000 { 92 compatible = "qcom,mdm9615-pinctrl"; 93 gpio-controller; 94 gpio-ranges = <&msmgpio 0 0 88>; 95 #gpio-cells = <2>; 96 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 97 interrupt-controller; 98 #interrupt-cells = <2>; 99 reg = <0x800000 0x4000>; 100 }; 101 102 gcc: clock-controller@900000 { 103 compatible = "qcom,gcc-mdm9615"; 104 #clock-cells = <1>; 105 #power-domain-cells = <1>; 106 #reset-cells = <1>; 107 reg = <0x900000 0x4000>; 108 clocks = <&cxo_board>, 109 <&lcc PLL4>; 110 }; 111 112 lcc: clock-controller@28000000 { 113 compatible = "qcom,lcc-mdm9615"; 114 reg = <0x28000000 0x1000>; 115 #clock-cells = <1>; 116 #reset-cells = <1>; 117 clocks = <&cxo_board>, 118 <&gcc PLL4_VOTE>, 119 <0>, 120 <0>, <0>, 121 <0>, <0>, 122 <0>; 123 clock-names = "cxo", 124 "pll4_vote", 125 "mi2s_codec_clk", 126 "codec_i2s_mic_codec_clk", 127 "spare_i2s_mic_codec_clk", 128 "codec_i2s_spkr_codec_clk", 129 "spare_i2s_spkr_codec_clk", 130 "pcm_codec_clk"; 131 }; 132 133 l2cc: clock-controller@2011000 { 134 compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; 135 reg = <0x02011000 0x1000>; 136 }; 137 138 rng@1a500000 { 139 compatible = "qcom,prng"; 140 reg = <0x1a500000 0x200>; 141 clocks = <&gcc PRNG_CLK>; 142 clock-names = "core"; 143 assigned-clocks = <&gcc PRNG_CLK>; 144 assigned-clock-rates = <32000000>; 145 }; 146 147 gsbi2: gsbi@16100000 { 148 compatible = "qcom,gsbi-v1.0.0"; 149 cell-index = <2>; 150 reg = <0x16100000 0x100>; 151 clocks = <&gcc GSBI2_H_CLK>; 152 clock-names = "iface"; 153 status = "disabled"; 154 #address-cells = <1>; 155 #size-cells = <1>; 156 ranges; 157 158 gsbi2_i2c: i2c@16180000 { 159 compatible = "qcom,i2c-qup-v1.1.1"; 160 #address-cells = <1>; 161 #size-cells = <0>; 162 reg = <0x16180000 0x1000>; 163 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 164 165 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 166 clock-names = "core", "iface"; 167 status = "disabled"; 168 }; 169 }; 170 171 gsbi3: gsbi@16200000 { 172 compatible = "qcom,gsbi-v1.0.0"; 173 cell-index = <3>; 174 reg = <0x16200000 0x100>; 175 clocks = <&gcc GSBI3_H_CLK>; 176 clock-names = "iface"; 177 status = "disabled"; 178 #address-cells = <1>; 179 #size-cells = <1>; 180 ranges; 181 182 gsbi3_spi: spi@16280000 { 183 compatible = "qcom,spi-qup-v1.1.1"; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 reg = <0x16280000 0x1000>; 187 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 188 189 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; 190 clock-names = "core", "iface"; 191 status = "disabled"; 192 }; 193 }; 194 195 gsbi4: gsbi@16300000 { 196 compatible = "qcom,gsbi-v1.0.0"; 197 cell-index = <4>; 198 reg = <0x16300000 0x100>; 199 clocks = <&gcc GSBI4_H_CLK>; 200 clock-names = "iface"; 201 status = "disabled"; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 ranges; 205 206 syscon-tcsr = <&tcsr>; 207 208 gsbi4_serial: serial@16340000 { 209 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 210 reg = <0x16340000 0x1000>, 211 <0x16300000 0x1000>; 212 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 214 clock-names = "core", "iface"; 215 status = "disabled"; 216 }; 217 }; 218 219 gsbi5: gsbi@16400000 { 220 compatible = "qcom,gsbi-v1.0.0"; 221 cell-index = <5>; 222 reg = <0x16400000 0x100>; 223 clocks = <&gcc GSBI5_H_CLK>; 224 clock-names = "iface"; 225 status = "disabled"; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 ranges; 229 230 syscon-tcsr = <&tcsr>; 231 232 gsbi5_i2c: i2c@16480000 { 233 compatible = "qcom,i2c-qup-v1.1.1"; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 reg = <0x16480000 0x1000>; 237 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 238 239 /* QUP clock is not initialized, set rate */ 240 assigned-clocks = <&gcc GSBI5_QUP_CLK>; 241 assigned-clock-rates = <24000000>; 242 243 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 244 clock-names = "core", "iface"; 245 status = "disabled"; 246 }; 247 248 gsbi5_serial: serial@16440000 { 249 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 250 reg = <0x16440000 0x1000>, 251 <0x16400000 0x1000>; 252 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 254 clock-names = "core", "iface"; 255 status = "disabled"; 256 }; 257 }; 258 259 qcom,ssbi@500000 { 260 compatible = "qcom,ssbi"; 261 reg = <0x500000 0x1000>; 262 qcom,controller-type = "pmic-arbiter"; 263 264 pmicintc: pmic { 265 compatible = "qcom,pm8018", "qcom,pm8921"; 266 interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>; 267 #interrupt-cells = <2>; 268 interrupt-controller; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 272 pwrkey@1c { 273 compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey"; 274 reg = <0x1c>; 275 interrupt-parent = <&pmicintc>; 276 interrupts = <50 IRQ_TYPE_EDGE_RISING>, 277 <51 IRQ_TYPE_EDGE_RISING>; 278 debounce = <15625>; 279 pull-up; 280 }; 281 282 pmicmpp: mpps@50 { 283 compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp"; 284 interrupt-controller; 285 #interrupt-cells = <2>; 286 reg = <0x50>; 287 gpio-controller; 288 #gpio-cells = <2>; 289 gpio-ranges = <&pmicmpp 0 0 6>; 290 }; 291 292 rtc@11d { 293 compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc"; 294 interrupt-parent = <&pmicintc>; 295 interrupts = <39 IRQ_TYPE_EDGE_RISING>; 296 reg = <0x11d>; 297 allow-set-time; 298 }; 299 300 pmicgpio: gpio@150 { 301 compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; 302 reg = <0x150>; 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 gpio-controller; 306 gpio-ranges = <&pmicgpio 0 0 6>; 307 #gpio-cells = <2>; 308 }; 309 }; 310 }; 311 312 sdcc1bam: dma-controller@12182000 { 313 compatible = "qcom,bam-v1.3.0"; 314 reg = <0x12182000 0x8000>; 315 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&gcc SDC1_H_CLK>; 317 clock-names = "bam_clk"; 318 #dma-cells = <1>; 319 qcom,ee = <0>; 320 }; 321 322 sdcc2bam: dma-controller@12142000 { 323 compatible = "qcom,bam-v1.3.0"; 324 reg = <0x12142000 0x8000>; 325 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&gcc SDC2_H_CLK>; 327 clock-names = "bam_clk"; 328 #dma-cells = <1>; 329 qcom,ee = <0>; 330 }; 331 332 sdcc1: mmc@12180000 { 333 status = "disabled"; 334 compatible = "arm,pl18x", "arm,primecell"; 335 arm,primecell-periphid = <0x00051180>; 336 reg = <0x12180000 0x2000>; 337 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 339 clock-names = "mclk", "apb_pclk"; 340 bus-width = <8>; 341 max-frequency = <48000000>; 342 cap-sd-highspeed; 343 cap-mmc-highspeed; 344 vmmc-supply = <&vsdcc_fixed>; 345 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 346 dma-names = "tx", "rx"; 347 assigned-clocks = <&gcc SDC1_CLK>; 348 assigned-clock-rates = <400000>; 349 }; 350 351 sdcc2: mmc@12140000 { 352 compatible = "arm,pl18x", "arm,primecell"; 353 arm,primecell-periphid = <0x00051180>; 354 status = "disabled"; 355 reg = <0x12140000 0x2000>; 356 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; 358 clock-names = "mclk", "apb_pclk"; 359 bus-width = <4>; 360 cap-sd-highspeed; 361 cap-mmc-highspeed; 362 max-frequency = <48000000>; 363 no-1-8-v; 364 vmmc-supply = <&vsdcc_fixed>; 365 dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; 366 dma-names = "tx", "rx"; 367 assigned-clocks = <&gcc SDC2_CLK>; 368 assigned-clock-rates = <400000>; 369 }; 370 371 tcsr: syscon@1a400000 { 372 compatible = "qcom,tcsr-mdm9615", "syscon"; 373 reg = <0x1a400000 0x100>; 374 }; 375 376 rpm: rpm@108000 { 377 compatible = "qcom,rpm-mdm9615"; 378 reg = <0x108000 0x1000>; 379 380 qcom,ipc = <&l2cc 0x8 2>; 381 382 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 383 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 384 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 385 interrupt-names = "ack", "err", "wakeup"; 386 387 regulators { 388 compatible = "qcom,rpm-pm8018-regulators"; 389 390 vin_lvs1-supply = <&pm8018_s3>; 391 392 vdd_l7-supply = <&pm8018_s4>; 393 vdd_l8-supply = <&pm8018_s3>; 394 vdd_l9_l10_l11_l12-supply = <&pm8018_s5>; 395 396 /* Buck SMPS */ 397 pm8018_s1: s1 { 398 regulator-min-microvolt = <500000>; 399 regulator-max-microvolt = <1150000>; 400 qcom,switch-mode-frequency = <1600000>; 401 bias-pull-down; 402 }; 403 404 pm8018_s2: s2 { 405 regulator-min-microvolt = <1225000>; 406 regulator-max-microvolt = <1300000>; 407 qcom,switch-mode-frequency = <1600000>; 408 bias-pull-down; 409 }; 410 411 pm8018_s3: s3 { 412 regulator-always-on; 413 regulator-min-microvolt = <1800000>; 414 regulator-max-microvolt = <1800000>; 415 qcom,switch-mode-frequency = <1600000>; 416 bias-pull-down; 417 }; 418 419 pm8018_s4: s4 { 420 regulator-min-microvolt = <2100000>; 421 regulator-max-microvolt = <2200000>; 422 qcom,switch-mode-frequency = <1600000>; 423 bias-pull-down; 424 }; 425 426 pm8018_s5: s5 { 427 regulator-always-on; 428 regulator-min-microvolt = <1350000>; 429 regulator-max-microvolt = <1350000>; 430 qcom,switch-mode-frequency = <1600000>; 431 bias-pull-down; 432 }; 433 434 /* PMOS LDO */ 435 pm8018_l2: l2 { 436 regulator-always-on; 437 regulator-min-microvolt = <1800000>; 438 regulator-max-microvolt = <1800000>; 439 bias-pull-down; 440 }; 441 442 pm8018_l3: l3 { 443 regulator-always-on; 444 regulator-min-microvolt = <1800000>; 445 regulator-max-microvolt = <1800000>; 446 bias-pull-down; 447 }; 448 449 pm8018_l4: l4 { 450 regulator-min-microvolt = <3300000>; 451 regulator-max-microvolt = <3300000>; 452 bias-pull-down; 453 }; 454 455 pm8018_l5: l5 { 456 regulator-min-microvolt = <2850000>; 457 regulator-max-microvolt = <2850000>; 458 bias-pull-down; 459 }; 460 461 pm8018_l6: l6 { 462 regulator-min-microvolt = <1800000>; 463 regulator-max-microvolt = <2850000>; 464 bias-pull-down; 465 }; 466 467 pm8018_l7: l7 { 468 regulator-min-microvolt = <1850000>; 469 regulator-max-microvolt = <1900000>; 470 bias-pull-down; 471 }; 472 473 pm8018_l8: l8 { 474 regulator-min-microvolt = <1200000>; 475 regulator-max-microvolt = <1200000>; 476 bias-pull-down; 477 }; 478 479 pm8018_l9: l9 { 480 regulator-min-microvolt = <750000>; 481 regulator-max-microvolt = <1150000>; 482 bias-pull-down; 483 }; 484 485 pm8018_l10: l10 { 486 regulator-min-microvolt = <1050000>; 487 regulator-max-microvolt = <1050000>; 488 bias-pull-down; 489 }; 490 491 pm8018_l11: l11 { 492 regulator-min-microvolt = <1050000>; 493 regulator-max-microvolt = <1050000>; 494 bias-pull-down; 495 }; 496 497 pm8018_l12: l12 { 498 regulator-min-microvolt = <1050000>; 499 regulator-max-microvolt = <1050000>; 500 bias-pull-down; 501 }; 502 503 pm8018_l13: l13 { 504 regulator-min-microvolt = <1850000>; 505 regulator-max-microvolt = <2950000>; 506 bias-pull-down; 507 }; 508 509 pm8018_l14: l14 { 510 regulator-min-microvolt = <2850000>; 511 regulator-max-microvolt = <2850000>; 512 bias-pull-down; 513 }; 514 515 /* Low Voltage Switch */ 516 pm8018_lvs1: lvs1 { 517 bias-pull-down; 518 }; 519 }; 520 }; 521 }; 522}; 523