1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/clock/qcom,gcc-ipq4019.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 model = "Qualcomm Technologies, Inc. IPQ4019"; 17 compatible = "qcom,ipq4019"; 18 interrupt-parent = <&intc>; 19 20 reserved-memory { 21 #address-cells = <0x1>; 22 #size-cells = <0x1>; 23 ranges; 24 25 smem_region: smem@87e00000 { 26 reg = <0x87e00000 0x080000>; 27 no-map; 28 }; 29 30 tz@87e80000 { 31 reg = <0x87e80000 0x180000>; 32 no-map; 33 }; 34 }; 35 36 aliases { 37 spi0 = &blsp1_spi1; 38 spi1 = &blsp1_spi2; 39 i2c0 = &blsp1_i2c3; 40 i2c1 = &blsp1_i2c4; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 enable-method = "qcom,kpss-acc-v2"; 50 next-level-cache = <&L2>; 51 qcom,acc = <&acc0>; 52 qcom,saw = <&saw0>; 53 reg = <0x0>; 54 clocks = <&gcc GCC_APPS_CLK_SRC>; 55 clock-frequency = <0>; 56 clock-latency = <256000>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 }; 59 60 cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 enable-method = "qcom,kpss-acc-v2"; 64 next-level-cache = <&L2>; 65 qcom,acc = <&acc1>; 66 qcom,saw = <&saw1>; 67 reg = <0x1>; 68 clocks = <&gcc GCC_APPS_CLK_SRC>; 69 clock-frequency = <0>; 70 clock-latency = <256000>; 71 operating-points-v2 = <&cpu0_opp_table>; 72 }; 73 74 cpu@2 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a7"; 77 enable-method = "qcom,kpss-acc-v2"; 78 next-level-cache = <&L2>; 79 qcom,acc = <&acc2>; 80 qcom,saw = <&saw2>; 81 reg = <0x2>; 82 clocks = <&gcc GCC_APPS_CLK_SRC>; 83 clock-frequency = <0>; 84 clock-latency = <256000>; 85 operating-points-v2 = <&cpu0_opp_table>; 86 }; 87 88 cpu@3 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a7"; 91 enable-method = "qcom,kpss-acc-v2"; 92 next-level-cache = <&L2>; 93 qcom,acc = <&acc3>; 94 qcom,saw = <&saw3>; 95 reg = <0x3>; 96 clocks = <&gcc GCC_APPS_CLK_SRC>; 97 clock-frequency = <0>; 98 clock-latency = <256000>; 99 operating-points-v2 = <&cpu0_opp_table>; 100 }; 101 102 L2: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 qcom,saw = <&saw_l2>; 106 }; 107 }; 108 109 cpu0_opp_table: opp-table { 110 compatible = "operating-points-v2"; 111 opp-shared; 112 113 opp-48000000 { 114 opp-hz = /bits/ 64 <48000000>; 115 clock-latency-ns = <256000>; 116 }; 117 opp-200000000 { 118 opp-hz = /bits/ 64 <200000000>; 119 clock-latency-ns = <256000>; 120 }; 121 opp-500000000 { 122 opp-hz = /bits/ 64 <500000000>; 123 clock-latency-ns = <256000>; 124 }; 125 opp-716000000 { 126 opp-hz = /bits/ 64 <716000000>; 127 clock-latency-ns = <256000>; 128 }; 129 }; 130 131 memory { 132 device_type = "memory"; 133 reg = <0x0 0x0>; 134 }; 135 136 pmu { 137 compatible = "arm,cortex-a7-pmu"; 138 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 139 IRQ_TYPE_LEVEL_HIGH)>; 140 }; 141 142 clocks { 143 sleep_clk: sleep_clk { 144 compatible = "fixed-clock"; 145 clock-frequency = <32000>; 146 #clock-cells = <0>; 147 }; 148 149 xo: xo { 150 compatible = "fixed-clock"; 151 clock-frequency = <48000000>; 152 #clock-cells = <0>; 153 }; 154 }; 155 156 firmware { 157 scm { 158 compatible = "qcom,scm-ipq4019", "qcom,scm"; 159 }; 160 }; 161 162 timer { 163 compatible = "arm,armv7-timer"; 164 interrupts = <1 2 0xf08>, 165 <1 3 0xf08>, 166 <1 4 0xf08>, 167 <1 1 0xf08>; 168 clock-frequency = <48000000>; 169 always-on; 170 }; 171 172 soc { 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges; 176 compatible = "simple-bus"; 177 178 intc: interrupt-controller@b000000 { 179 compatible = "qcom,msm-qgic2"; 180 interrupt-controller; 181 #interrupt-cells = <3>; 182 reg = <0x0b000000 0x1000>, 183 <0x0b002000 0x1000>; 184 }; 185 186 gcc: clock-controller@1800000 { 187 compatible = "qcom,gcc-ipq4019"; 188 #clock-cells = <1>; 189 #power-domain-cells = <1>; 190 #reset-cells = <1>; 191 reg = <0x1800000 0x60000>; 192 clocks = <&xo>, <&sleep_clk>; 193 clock-names = "xo", "sleep_clk"; 194 }; 195 196 prng: rng@22000 { 197 compatible = "qcom,prng"; 198 reg = <0x22000 0x140>; 199 clocks = <&gcc GCC_PRNG_AHB_CLK>; 200 clock-names = "core"; 201 status = "disabled"; 202 }; 203 204 tlmm: pinctrl@1000000 { 205 compatible = "qcom,ipq4019-pinctrl"; 206 reg = <0x01000000 0x300000>; 207 gpio-controller; 208 gpio-ranges = <&tlmm 0 0 100>; 209 #gpio-cells = <2>; 210 interrupt-controller; 211 #interrupt-cells = <2>; 212 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 213 }; 214 215 vqmmc: regulator@1948000 { 216 compatible = "qcom,vqmmc-ipq4019-regulator"; 217 reg = <0x01948000 0x4>; 218 regulator-name = "vqmmc"; 219 regulator-min-microvolt = <1500000>; 220 regulator-max-microvolt = <3000000>; 221 regulator-always-on; 222 status = "disabled"; 223 }; 224 225 sdhci: mmc@7824900 { 226 compatible = "qcom,sdhci-msm-v4"; 227 reg = <0x7824900 0x11c>, <0x7824000 0x800>; 228 reg-names = "hc", "core"; 229 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 230 interrupt-names = "hc_irq", "pwr_irq"; 231 bus-width = <8>; 232 clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, 233 <&gcc GCC_DCD_XO_CLK>; 234 clock-names = "iface", "core", "xo"; 235 status = "disabled"; 236 }; 237 238 blsp_dma: dma-controller@7884000 { 239 compatible = "qcom,bam-v1.7.0"; 240 reg = <0x07884000 0x23000>; 241 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 243 clock-names = "bam_clk"; 244 #dma-cells = <1>; 245 qcom,ee = <0>; 246 status = "disabled"; 247 }; 248 249 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ 250 compatible = "qcom,spi-qup-v2.2.1"; 251 reg = <0x78b5000 0x600>; 252 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 254 <&gcc GCC_BLSP1_AHB_CLK>; 255 clock-names = "core", "iface"; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 259 dma-names = "tx", "rx"; 260 status = "disabled"; 261 }; 262 263 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ 264 compatible = "qcom,spi-qup-v2.2.1"; 265 reg = <0x78b6000 0x600>; 266 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 268 <&gcc GCC_BLSP1_AHB_CLK>; 269 clock-names = "core", "iface"; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 273 dma-names = "tx", "rx"; 274 status = "disabled"; 275 }; 276 277 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ 278 compatible = "qcom,i2c-qup-v2.2.1"; 279 reg = <0x78b7000 0x600>; 280 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 282 <&gcc GCC_BLSP1_AHB_CLK>; 283 clock-names = "core", "iface"; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 287 dma-names = "tx", "rx"; 288 status = "disabled"; 289 }; 290 291 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ 292 compatible = "qcom,i2c-qup-v2.2.1"; 293 reg = <0x78b8000 0x600>; 294 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 296 <&gcc GCC_BLSP1_AHB_CLK>; 297 clock-names = "core", "iface"; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 301 dma-names = "tx", "rx"; 302 status = "disabled"; 303 }; 304 305 cryptobam: dma-controller@8e04000 { 306 compatible = "qcom,bam-v1.7.0"; 307 reg = <0x08e04000 0x20000>; 308 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 310 clock-names = "bam_clk"; 311 #dma-cells = <1>; 312 qcom,ee = <1>; 313 qcom,controlled-remotely; 314 status = "disabled"; 315 }; 316 317 crypto: crypto@8e3a000 { 318 compatible = "qcom,crypto-v5.1"; 319 reg = <0x08e3a000 0x6000>; 320 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 321 <&gcc GCC_CRYPTO_AXI_CLK>, 322 <&gcc GCC_CRYPTO_CLK>; 323 clock-names = "iface", "bus", "core"; 324 dmas = <&cryptobam 2>, <&cryptobam 3>; 325 dma-names = "rx", "tx"; 326 status = "disabled"; 327 }; 328 329 acc0: power-manager@b088000 { 330 compatible = "qcom,kpss-acc-v2"; 331 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; 332 }; 333 334 acc1: power-manager@b098000 { 335 compatible = "qcom,kpss-acc-v2"; 336 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; 337 }; 338 339 acc2: power-manager@b0a8000 { 340 compatible = "qcom,kpss-acc-v2"; 341 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; 342 }; 343 344 acc3: power-manager@b0b8000 { 345 compatible = "qcom,kpss-acc-v2"; 346 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; 347 }; 348 349 saw0: regulator@b089000 { 350 compatible = "qcom,saw2"; 351 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; 352 regulator; 353 }; 354 355 saw1: regulator@b099000 { 356 compatible = "qcom,saw2"; 357 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; 358 regulator; 359 }; 360 361 saw2: regulator@b0a9000 { 362 compatible = "qcom,saw2"; 363 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; 364 regulator; 365 }; 366 367 saw3: regulator@b0b9000 { 368 compatible = "qcom,saw2"; 369 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; 370 regulator; 371 }; 372 373 saw_l2: regulator@b012000 { 374 compatible = "qcom,saw2"; 375 reg = <0xb012000 0x1000>; 376 regulator; 377 }; 378 379 blsp1_uart1: serial@78af000 { 380 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 381 reg = <0x78af000 0x200>; 382 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 383 status = "disabled"; 384 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 385 <&gcc GCC_BLSP1_AHB_CLK>; 386 clock-names = "core", "iface"; 387 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 388 dma-names = "tx", "rx"; 389 }; 390 391 blsp1_uart2: serial@78b0000 { 392 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 393 reg = <0x78b0000 0x200>; 394 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 395 status = "disabled"; 396 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 397 <&gcc GCC_BLSP1_AHB_CLK>; 398 clock-names = "core", "iface"; 399 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 400 dma-names = "tx", "rx"; 401 }; 402 403 watchdog: watchdog@b017000 { 404 compatible = "qcom,kpss-wdt-ipq4019", "qcom,kpss-wdt"; 405 reg = <0xb017000 0x40>; 406 clocks = <&sleep_clk>; 407 timeout-sec = <10>; 408 status = "disabled"; 409 }; 410 411 restart@4ab000 { 412 compatible = "qcom,pshold"; 413 reg = <0x4ab000 0x4>; 414 }; 415 416 pcie0: pci@40000000 { 417 compatible = "qcom,pcie-ipq4019"; 418 reg = <0x40000000 0xf1d 419 0x40000f20 0xa8 420 0x80000 0x2000 421 0x40100000 0x1000>; 422 reg-names = "dbi", "elbi", "parf", "config"; 423 device_type = "pci"; 424 linux,pci-domain = <0>; 425 bus-range = <0x00 0xff>; 426 num-lanes = <1>; 427 #address-cells = <3>; 428 #size-cells = <2>; 429 430 ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>, 431 <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>; 432 433 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 434 interrupt-names = "msi"; 435 #interrupt-cells = <1>; 436 interrupt-map-mask = <0 0 0 0x7>; 437 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 438 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 439 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 440 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 441 clocks = <&gcc GCC_PCIE_AHB_CLK>, 442 <&gcc GCC_PCIE_AXI_M_CLK>, 443 <&gcc GCC_PCIE_AXI_S_CLK>; 444 clock-names = "aux", 445 "master_bus", 446 "slave_bus"; 447 448 resets = <&gcc PCIE_AXI_M_ARES>, 449 <&gcc PCIE_AXI_S_ARES>, 450 <&gcc PCIE_PIPE_ARES>, 451 <&gcc PCIE_AXI_M_VMIDMT_ARES>, 452 <&gcc PCIE_AXI_S_XPU_ARES>, 453 <&gcc PCIE_PARF_XPU_ARES>, 454 <&gcc PCIE_PHY_ARES>, 455 <&gcc PCIE_AXI_M_STICKY_ARES>, 456 <&gcc PCIE_PIPE_STICKY_ARES>, 457 <&gcc PCIE_PWR_ARES>, 458 <&gcc PCIE_AHB_ARES>, 459 <&gcc PCIE_PHY_AHB_ARES>; 460 reset-names = "axi_m", 461 "axi_s", 462 "pipe", 463 "axi_m_vmid", 464 "axi_s_xpu", 465 "parf", 466 "phy", 467 "axi_m_sticky", 468 "pipe_sticky", 469 "pwr", 470 "ahb", 471 "phy_ahb"; 472 473 status = "disabled"; 474 }; 475 476 qpic_bam: dma-controller@7984000 { 477 compatible = "qcom,bam-v1.7.0"; 478 reg = <0x7984000 0x1a000>; 479 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&gcc GCC_QPIC_CLK>; 481 clock-names = "bam_clk"; 482 #dma-cells = <1>; 483 qcom,ee = <0>; 484 status = "disabled"; 485 }; 486 487 nand: nand-controller@79b0000 { 488 compatible = "qcom,ipq4019-nand"; 489 reg = <0x79b0000 0x1000>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 clocks = <&gcc GCC_QPIC_CLK>, 493 <&gcc GCC_QPIC_AHB_CLK>; 494 clock-names = "core", "aon"; 495 496 dmas = <&qpic_bam 0>, 497 <&qpic_bam 1>, 498 <&qpic_bam 2>; 499 dma-names = "tx", "rx", "cmd"; 500 status = "disabled"; 501 502 nand@0 { 503 reg = <0>; 504 505 nand-ecc-strength = <4>; 506 nand-ecc-step-size = <512>; 507 nand-bus-width = <8>; 508 }; 509 }; 510 511 wifi0: wifi@a000000 { 512 compatible = "qcom,ipq4019-wifi"; 513 reg = <0xa000000 0x200000>; 514 resets = <&gcc WIFI0_CPU_INIT_RESET>, 515 <&gcc WIFI0_RADIO_SRIF_RESET>, 516 <&gcc WIFI0_RADIO_WARM_RESET>, 517 <&gcc WIFI0_RADIO_COLD_RESET>, 518 <&gcc WIFI0_CORE_WARM_RESET>, 519 <&gcc WIFI0_CORE_COLD_RESET>; 520 reset-names = "wifi_cpu_init", "wifi_radio_srif", 521 "wifi_radio_warm", "wifi_radio_cold", 522 "wifi_core_warm", "wifi_core_cold"; 523 clocks = <&gcc GCC_WCSS2G_CLK>, 524 <&gcc GCC_WCSS2G_REF_CLK>, 525 <&gcc GCC_WCSS2G_RTC_CLK>; 526 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 527 "wifi_wcss_rtc"; 528 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 529 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 530 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 531 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 532 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 533 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 534 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 535 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 536 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, 537 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 538 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 539 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 540 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 541 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 542 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 543 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 544 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 545 interrupt-names = "msi0", "msi1", "msi2", "msi3", 546 "msi4", "msi5", "msi6", "msi7", 547 "msi8", "msi9", "msi10", "msi11", 548 "msi12", "msi13", "msi14", "msi15", 549 "legacy"; 550 status = "disabled"; 551 }; 552 553 wifi1: wifi@a800000 { 554 compatible = "qcom,ipq4019-wifi"; 555 reg = <0xa800000 0x200000>; 556 resets = <&gcc WIFI1_CPU_INIT_RESET>, 557 <&gcc WIFI1_RADIO_SRIF_RESET>, 558 <&gcc WIFI1_RADIO_WARM_RESET>, 559 <&gcc WIFI1_RADIO_COLD_RESET>, 560 <&gcc WIFI1_CORE_WARM_RESET>, 561 <&gcc WIFI1_CORE_COLD_RESET>; 562 reset-names = "wifi_cpu_init", "wifi_radio_srif", 563 "wifi_radio_warm", "wifi_radio_cold", 564 "wifi_core_warm", "wifi_core_cold"; 565 clocks = <&gcc GCC_WCSS5G_CLK>, 566 <&gcc GCC_WCSS5G_REF_CLK>, 567 <&gcc GCC_WCSS5G_RTC_CLK>; 568 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 569 "wifi_wcss_rtc"; 570 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 571 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 572 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 573 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 574 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 575 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 576 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 577 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 578 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>, 579 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 580 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 581 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 582 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 583 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 584 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 585 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 586 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 587 interrupt-names = "msi0", "msi1", "msi2", "msi3", 588 "msi4", "msi5", "msi6", "msi7", 589 "msi8", "msi9", "msi10", "msi11", 590 "msi12", "msi13", "msi14", "msi15", 591 "legacy"; 592 status = "disabled"; 593 }; 594 595 mdio: mdio@90000 { 596 #address-cells = <1>; 597 #size-cells = <0>; 598 compatible = "qcom,ipq4019-mdio"; 599 reg = <0x90000 0x64>; 600 status = "disabled"; 601 602 ethphy0: ethernet-phy@0 { 603 reg = <0>; 604 }; 605 606 ethphy1: ethernet-phy@1 { 607 reg = <1>; 608 }; 609 610 ethphy2: ethernet-phy@2 { 611 reg = <2>; 612 }; 613 614 ethphy3: ethernet-phy@3 { 615 reg = <3>; 616 }; 617 618 ethphy4: ethernet-phy@4 { 619 reg = <4>; 620 }; 621 }; 622 623 usb3_ss_phy: ssphy@9a000 { 624 compatible = "qcom,usb-ss-ipq4019-phy"; 625 #phy-cells = <0>; 626 reg = <0x9a000 0x800>; 627 reg-names = "phy_base"; 628 resets = <&gcc USB3_UNIPHY_PHY_ARES>; 629 reset-names = "por_rst"; 630 status = "disabled"; 631 }; 632 633 usb3_hs_phy: hsphy@a6000 { 634 compatible = "qcom,usb-hs-ipq4019-phy"; 635 #phy-cells = <0>; 636 reg = <0xa6000 0x40>; 637 reg-names = "phy_base"; 638 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; 639 reset-names = "por_rst", "srif_rst"; 640 status = "disabled"; 641 }; 642 643 usb3: usb3@8af8800 { 644 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; 645 reg = <0x8af8800 0x100>; 646 #address-cells = <1>; 647 #size-cells = <1>; 648 clocks = <&gcc GCC_USB3_MASTER_CLK>, 649 <&gcc GCC_USB3_SLEEP_CLK>, 650 <&gcc GCC_USB3_MOCK_UTMI_CLK>; 651 clock-names = "core", "sleep", "mock_utmi"; 652 ranges; 653 status = "disabled"; 654 655 dwc3@8a00000 { 656 compatible = "snps,dwc3"; 657 reg = <0x8a00000 0xf8000>; 658 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 659 phys = <&usb3_hs_phy>, <&usb3_ss_phy>; 660 phy-names = "usb2-phy", "usb3-phy"; 661 dr_mode = "host"; 662 }; 663 }; 664 665 usb2_hs_phy: hsphy@a8000 { 666 compatible = "qcom,usb-hs-ipq4019-phy"; 667 #phy-cells = <0>; 668 reg = <0xa8000 0x40>; 669 reg-names = "phy_base"; 670 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; 671 reset-names = "por_rst", "srif_rst"; 672 status = "disabled"; 673 }; 674 675 usb2: usb2@60f8800 { 676 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; 677 reg = <0x60f8800 0x100>; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 clocks = <&gcc GCC_USB2_MASTER_CLK>, 681 <&gcc GCC_USB2_SLEEP_CLK>, 682 <&gcc GCC_USB2_MOCK_UTMI_CLK>; 683 clock-names = "master", "sleep", "mock_utmi"; 684 ranges; 685 status = "disabled"; 686 687 dwc3@6000000 { 688 compatible = "snps,dwc3"; 689 reg = <0x6000000 0xf8000>; 690 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 691 phys = <&usb2_hs_phy>; 692 phy-names = "usb2-phy"; 693 dr_mode = "host"; 694 }; 695 }; 696 }; 697}; 698