1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/clock/qcom,gcc-ipq4019.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 model = "Qualcomm Technologies, Inc. IPQ4019"; 17 compatible = "qcom,ipq4019"; 18 interrupt-parent = <&intc>; 19 20 reserved-memory { 21 #address-cells = <0x1>; 22 #size-cells = <0x1>; 23 ranges; 24 25 smem_region: smem@87e00000 { 26 reg = <0x87e00000 0x080000>; 27 no-map; 28 }; 29 30 tz@87e80000 { 31 reg = <0x87e80000 0x180000>; 32 no-map; 33 }; 34 }; 35 36 aliases { 37 spi0 = &blsp1_spi1; 38 spi1 = &blsp1_spi2; 39 i2c0 = &blsp1_i2c3; 40 i2c1 = &blsp1_i2c4; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 enable-method = "qcom,kpss-acc-v2"; 50 next-level-cache = <&L2>; 51 qcom,acc = <&acc0>; 52 qcom,saw = <&saw0>; 53 reg = <0x0>; 54 clocks = <&gcc GCC_APPS_CLK_SRC>; 55 clock-frequency = <0>; 56 clock-latency = <256000>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 }; 59 60 cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 enable-method = "qcom,kpss-acc-v2"; 64 next-level-cache = <&L2>; 65 qcom,acc = <&acc1>; 66 qcom,saw = <&saw1>; 67 reg = <0x1>; 68 clocks = <&gcc GCC_APPS_CLK_SRC>; 69 clock-frequency = <0>; 70 clock-latency = <256000>; 71 operating-points-v2 = <&cpu0_opp_table>; 72 }; 73 74 cpu@2 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a7"; 77 enable-method = "qcom,kpss-acc-v2"; 78 next-level-cache = <&L2>; 79 qcom,acc = <&acc2>; 80 qcom,saw = <&saw2>; 81 reg = <0x2>; 82 clocks = <&gcc GCC_APPS_CLK_SRC>; 83 clock-frequency = <0>; 84 clock-latency = <256000>; 85 operating-points-v2 = <&cpu0_opp_table>; 86 }; 87 88 cpu@3 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a7"; 91 enable-method = "qcom,kpss-acc-v2"; 92 next-level-cache = <&L2>; 93 qcom,acc = <&acc3>; 94 qcom,saw = <&saw3>; 95 reg = <0x3>; 96 clocks = <&gcc GCC_APPS_CLK_SRC>; 97 clock-frequency = <0>; 98 clock-latency = <256000>; 99 operating-points-v2 = <&cpu0_opp_table>; 100 }; 101 102 L2: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 cache-unified; 106 qcom,saw = <&saw_l2>; 107 }; 108 }; 109 110 cpu0_opp_table: opp-table { 111 compatible = "operating-points-v2"; 112 opp-shared; 113 114 opp-48000000 { 115 opp-hz = /bits/ 64 <48000000>; 116 clock-latency-ns = <256000>; 117 }; 118 opp-200000000 { 119 opp-hz = /bits/ 64 <200000000>; 120 clock-latency-ns = <256000>; 121 }; 122 opp-500000000 { 123 opp-hz = /bits/ 64 <500000000>; 124 clock-latency-ns = <256000>; 125 }; 126 opp-716000000 { 127 opp-hz = /bits/ 64 <716000000>; 128 clock-latency-ns = <256000>; 129 }; 130 }; 131 132 memory { 133 device_type = "memory"; 134 reg = <0x0 0x0>; 135 }; 136 137 pmu { 138 compatible = "arm,cortex-a7-pmu"; 139 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 140 IRQ_TYPE_LEVEL_HIGH)>; 141 }; 142 143 clocks { 144 sleep_clk: sleep_clk { 145 compatible = "fixed-clock"; 146 clock-frequency = <32000>; 147 #clock-cells = <0>; 148 }; 149 150 xo: xo { 151 compatible = "fixed-clock"; 152 clock-frequency = <48000000>; 153 #clock-cells = <0>; 154 }; 155 }; 156 157 firmware { 158 scm { 159 compatible = "qcom,scm-ipq4019", "qcom,scm"; 160 }; 161 }; 162 163 timer { 164 compatible = "arm,armv7-timer"; 165 interrupts = <1 2 0xf08>, 166 <1 3 0xf08>, 167 <1 4 0xf08>, 168 <1 1 0xf08>; 169 clock-frequency = <48000000>; 170 always-on; 171 }; 172 173 soc { 174 #address-cells = <1>; 175 #size-cells = <1>; 176 ranges; 177 compatible = "simple-bus"; 178 179 intc: interrupt-controller@b000000 { 180 compatible = "qcom,msm-qgic2"; 181 interrupt-controller; 182 #interrupt-cells = <3>; 183 reg = <0x0b000000 0x1000>, 184 <0x0b002000 0x1000>; 185 }; 186 187 gcc: clock-controller@1800000 { 188 compatible = "qcom,gcc-ipq4019"; 189 #clock-cells = <1>; 190 #power-domain-cells = <1>; 191 #reset-cells = <1>; 192 reg = <0x1800000 0x60000>; 193 clocks = <&xo>, <&sleep_clk>; 194 clock-names = "xo", "sleep_clk"; 195 }; 196 197 prng: rng@22000 { 198 compatible = "qcom,prng"; 199 reg = <0x22000 0x140>; 200 clocks = <&gcc GCC_PRNG_AHB_CLK>; 201 clock-names = "core"; 202 status = "disabled"; 203 }; 204 205 tlmm: pinctrl@1000000 { 206 compatible = "qcom,ipq4019-pinctrl"; 207 reg = <0x01000000 0x300000>; 208 gpio-controller; 209 gpio-ranges = <&tlmm 0 0 100>; 210 #gpio-cells = <2>; 211 interrupt-controller; 212 #interrupt-cells = <2>; 213 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 214 }; 215 216 vqmmc: regulator@1948000 { 217 compatible = "qcom,vqmmc-ipq4019-regulator"; 218 reg = <0x01948000 0x4>; 219 regulator-name = "vqmmc"; 220 regulator-min-microvolt = <1500000>; 221 regulator-max-microvolt = <3000000>; 222 regulator-always-on; 223 status = "disabled"; 224 }; 225 226 sdhci: mmc@7824900 { 227 compatible = "qcom,sdhci-msm-v4"; 228 reg = <0x7824900 0x11c>, <0x7824000 0x800>; 229 reg-names = "hc", "core"; 230 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 231 interrupt-names = "hc_irq", "pwr_irq"; 232 bus-width = <8>; 233 clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, 234 <&gcc GCC_DCD_XO_CLK>; 235 clock-names = "iface", "core", "xo"; 236 status = "disabled"; 237 }; 238 239 blsp_dma: dma-controller@7884000 { 240 compatible = "qcom,bam-v1.7.0"; 241 reg = <0x07884000 0x23000>; 242 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 244 clock-names = "bam_clk"; 245 #dma-cells = <1>; 246 qcom,ee = <0>; 247 status = "disabled"; 248 }; 249 250 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ 251 compatible = "qcom,spi-qup-v2.2.1"; 252 reg = <0x78b5000 0x600>; 253 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 255 <&gcc GCC_BLSP1_AHB_CLK>; 256 clock-names = "core", "iface"; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 260 dma-names = "tx", "rx"; 261 status = "disabled"; 262 }; 263 264 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ 265 compatible = "qcom,spi-qup-v2.2.1"; 266 reg = <0x78b6000 0x600>; 267 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 269 <&gcc GCC_BLSP1_AHB_CLK>; 270 clock-names = "core", "iface"; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 274 dma-names = "tx", "rx"; 275 status = "disabled"; 276 }; 277 278 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ 279 compatible = "qcom,i2c-qup-v2.2.1"; 280 reg = <0x78b7000 0x600>; 281 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 283 <&gcc GCC_BLSP1_AHB_CLK>; 284 clock-names = "core", "iface"; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 288 dma-names = "tx", "rx"; 289 status = "disabled"; 290 }; 291 292 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ 293 compatible = "qcom,i2c-qup-v2.2.1"; 294 reg = <0x78b8000 0x600>; 295 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 297 <&gcc GCC_BLSP1_AHB_CLK>; 298 clock-names = "core", "iface"; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 302 dma-names = "tx", "rx"; 303 status = "disabled"; 304 }; 305 306 cryptobam: dma-controller@8e04000 { 307 compatible = "qcom,bam-v1.7.0"; 308 reg = <0x08e04000 0x20000>; 309 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 311 clock-names = "bam_clk"; 312 #dma-cells = <1>; 313 qcom,ee = <1>; 314 qcom,controlled-remotely; 315 status = "disabled"; 316 }; 317 318 crypto: crypto@8e3a000 { 319 compatible = "qcom,crypto-v5.1"; 320 reg = <0x08e3a000 0x6000>; 321 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 322 <&gcc GCC_CRYPTO_AXI_CLK>, 323 <&gcc GCC_CRYPTO_CLK>; 324 clock-names = "iface", "bus", "core"; 325 dmas = <&cryptobam 2>, <&cryptobam 3>; 326 dma-names = "rx", "tx"; 327 status = "disabled"; 328 }; 329 330 acc0: power-manager@b088000 { 331 compatible = "qcom,kpss-acc-v2"; 332 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; 333 }; 334 335 acc1: power-manager@b098000 { 336 compatible = "qcom,kpss-acc-v2"; 337 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; 338 }; 339 340 acc2: power-manager@b0a8000 { 341 compatible = "qcom,kpss-acc-v2"; 342 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; 343 }; 344 345 acc3: power-manager@b0b8000 { 346 compatible = "qcom,kpss-acc-v2"; 347 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; 348 }; 349 350 saw0: regulator@b089000 { 351 compatible = "qcom,saw2"; 352 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; 353 regulator; 354 }; 355 356 saw1: regulator@b099000 { 357 compatible = "qcom,saw2"; 358 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; 359 regulator; 360 }; 361 362 saw2: regulator@b0a9000 { 363 compatible = "qcom,saw2"; 364 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; 365 regulator; 366 }; 367 368 saw3: regulator@b0b9000 { 369 compatible = "qcom,saw2"; 370 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; 371 regulator; 372 }; 373 374 saw_l2: regulator@b012000 { 375 compatible = "qcom,saw2"; 376 reg = <0xb012000 0x1000>; 377 regulator; 378 }; 379 380 blsp1_uart1: serial@78af000 { 381 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 382 reg = <0x78af000 0x200>; 383 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 384 status = "disabled"; 385 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 386 <&gcc GCC_BLSP1_AHB_CLK>; 387 clock-names = "core", "iface"; 388 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 389 dma-names = "tx", "rx"; 390 }; 391 392 blsp1_uart2: serial@78b0000 { 393 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 394 reg = <0x78b0000 0x200>; 395 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 396 status = "disabled"; 397 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 398 <&gcc GCC_BLSP1_AHB_CLK>; 399 clock-names = "core", "iface"; 400 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 401 dma-names = "tx", "rx"; 402 }; 403 404 watchdog: watchdog@b017000 { 405 compatible = "qcom,kpss-wdt-ipq4019", "qcom,kpss-wdt"; 406 reg = <0xb017000 0x40>; 407 clocks = <&sleep_clk>; 408 timeout-sec = <10>; 409 status = "disabled"; 410 }; 411 412 restart@4ab000 { 413 compatible = "qcom,pshold"; 414 reg = <0x4ab000 0x4>; 415 }; 416 417 pcie0: pci@40000000 { 418 compatible = "qcom,pcie-ipq4019"; 419 reg = <0x40000000 0xf1d 420 0x40000f20 0xa8 421 0x80000 0x2000 422 0x40100000 0x1000>; 423 reg-names = "dbi", "elbi", "parf", "config"; 424 device_type = "pci"; 425 linux,pci-domain = <0>; 426 bus-range = <0x00 0xff>; 427 num-lanes = <1>; 428 #address-cells = <3>; 429 #size-cells = <2>; 430 431 ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>, 432 <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>; 433 434 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 435 interrupt-names = "msi"; 436 #interrupt-cells = <1>; 437 interrupt-map-mask = <0 0 0 0x7>; 438 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 439 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 440 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 441 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 442 clocks = <&gcc GCC_PCIE_AHB_CLK>, 443 <&gcc GCC_PCIE_AXI_M_CLK>, 444 <&gcc GCC_PCIE_AXI_S_CLK>; 445 clock-names = "aux", 446 "master_bus", 447 "slave_bus"; 448 449 resets = <&gcc PCIE_AXI_M_ARES>, 450 <&gcc PCIE_AXI_S_ARES>, 451 <&gcc PCIE_PIPE_ARES>, 452 <&gcc PCIE_AXI_M_VMIDMT_ARES>, 453 <&gcc PCIE_AXI_S_XPU_ARES>, 454 <&gcc PCIE_PARF_XPU_ARES>, 455 <&gcc PCIE_PHY_ARES>, 456 <&gcc PCIE_AXI_M_STICKY_ARES>, 457 <&gcc PCIE_PIPE_STICKY_ARES>, 458 <&gcc PCIE_PWR_ARES>, 459 <&gcc PCIE_AHB_ARES>, 460 <&gcc PCIE_PHY_AHB_ARES>; 461 reset-names = "axi_m", 462 "axi_s", 463 "pipe", 464 "axi_m_vmid", 465 "axi_s_xpu", 466 "parf", 467 "phy", 468 "axi_m_sticky", 469 "pipe_sticky", 470 "pwr", 471 "ahb", 472 "phy_ahb"; 473 474 status = "disabled"; 475 }; 476 477 qpic_bam: dma-controller@7984000 { 478 compatible = "qcom,bam-v1.7.0"; 479 reg = <0x7984000 0x1a000>; 480 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&gcc GCC_QPIC_CLK>; 482 clock-names = "bam_clk"; 483 #dma-cells = <1>; 484 qcom,ee = <0>; 485 status = "disabled"; 486 }; 487 488 nand: nand-controller@79b0000 { 489 compatible = "qcom,ipq4019-nand"; 490 reg = <0x79b0000 0x1000>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 clocks = <&gcc GCC_QPIC_CLK>, 494 <&gcc GCC_QPIC_AHB_CLK>; 495 clock-names = "core", "aon"; 496 497 dmas = <&qpic_bam 0>, 498 <&qpic_bam 1>, 499 <&qpic_bam 2>; 500 dma-names = "tx", "rx", "cmd"; 501 status = "disabled"; 502 503 nand@0 { 504 reg = <0>; 505 506 nand-ecc-strength = <4>; 507 nand-ecc-step-size = <512>; 508 nand-bus-width = <8>; 509 }; 510 }; 511 512 wifi0: wifi@a000000 { 513 compatible = "qcom,ipq4019-wifi"; 514 reg = <0xa000000 0x200000>; 515 resets = <&gcc WIFI0_CPU_INIT_RESET>, 516 <&gcc WIFI0_RADIO_SRIF_RESET>, 517 <&gcc WIFI0_RADIO_WARM_RESET>, 518 <&gcc WIFI0_RADIO_COLD_RESET>, 519 <&gcc WIFI0_CORE_WARM_RESET>, 520 <&gcc WIFI0_CORE_COLD_RESET>; 521 reset-names = "wifi_cpu_init", "wifi_radio_srif", 522 "wifi_radio_warm", "wifi_radio_cold", 523 "wifi_core_warm", "wifi_core_cold"; 524 clocks = <&gcc GCC_WCSS2G_CLK>, 525 <&gcc GCC_WCSS2G_REF_CLK>, 526 <&gcc GCC_WCSS2G_RTC_CLK>; 527 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 528 "wifi_wcss_rtc"; 529 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 530 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 531 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 532 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 533 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 534 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 535 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 536 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 537 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, 538 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 539 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 540 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 541 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 542 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 543 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 544 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 545 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 546 interrupt-names = "msi0", "msi1", "msi2", "msi3", 547 "msi4", "msi5", "msi6", "msi7", 548 "msi8", "msi9", "msi10", "msi11", 549 "msi12", "msi13", "msi14", "msi15", 550 "legacy"; 551 status = "disabled"; 552 }; 553 554 wifi1: wifi@a800000 { 555 compatible = "qcom,ipq4019-wifi"; 556 reg = <0xa800000 0x200000>; 557 resets = <&gcc WIFI1_CPU_INIT_RESET>, 558 <&gcc WIFI1_RADIO_SRIF_RESET>, 559 <&gcc WIFI1_RADIO_WARM_RESET>, 560 <&gcc WIFI1_RADIO_COLD_RESET>, 561 <&gcc WIFI1_CORE_WARM_RESET>, 562 <&gcc WIFI1_CORE_COLD_RESET>; 563 reset-names = "wifi_cpu_init", "wifi_radio_srif", 564 "wifi_radio_warm", "wifi_radio_cold", 565 "wifi_core_warm", "wifi_core_cold"; 566 clocks = <&gcc GCC_WCSS5G_CLK>, 567 <&gcc GCC_WCSS5G_REF_CLK>, 568 <&gcc GCC_WCSS5G_RTC_CLK>; 569 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 570 "wifi_wcss_rtc"; 571 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 572 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 573 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 574 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 575 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 576 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 577 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 578 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 579 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>, 580 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 581 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 582 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 583 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 584 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 585 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 586 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 587 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 588 interrupt-names = "msi0", "msi1", "msi2", "msi3", 589 "msi4", "msi5", "msi6", "msi7", 590 "msi8", "msi9", "msi10", "msi11", 591 "msi12", "msi13", "msi14", "msi15", 592 "legacy"; 593 status = "disabled"; 594 }; 595 596 mdio: mdio@90000 { 597 #address-cells = <1>; 598 #size-cells = <0>; 599 compatible = "qcom,ipq4019-mdio"; 600 reg = <0x90000 0x64>; 601 status = "disabled"; 602 603 ethphy0: ethernet-phy@0 { 604 reg = <0>; 605 }; 606 607 ethphy1: ethernet-phy@1 { 608 reg = <1>; 609 }; 610 611 ethphy2: ethernet-phy@2 { 612 reg = <2>; 613 }; 614 615 ethphy3: ethernet-phy@3 { 616 reg = <3>; 617 }; 618 619 ethphy4: ethernet-phy@4 { 620 reg = <4>; 621 }; 622 }; 623 624 usb3_ss_phy: ssphy@9a000 { 625 compatible = "qcom,usb-ss-ipq4019-phy"; 626 #phy-cells = <0>; 627 reg = <0x9a000 0x800>; 628 reg-names = "phy_base"; 629 resets = <&gcc USB3_UNIPHY_PHY_ARES>; 630 reset-names = "por_rst"; 631 status = "disabled"; 632 }; 633 634 usb3_hs_phy: hsphy@a6000 { 635 compatible = "qcom,usb-hs-ipq4019-phy"; 636 #phy-cells = <0>; 637 reg = <0xa6000 0x40>; 638 reg-names = "phy_base"; 639 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; 640 reset-names = "por_rst", "srif_rst"; 641 status = "disabled"; 642 }; 643 644 usb3: usb3@8af8800 { 645 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; 646 reg = <0x8af8800 0x100>; 647 #address-cells = <1>; 648 #size-cells = <1>; 649 clocks = <&gcc GCC_USB3_MASTER_CLK>, 650 <&gcc GCC_USB3_SLEEP_CLK>, 651 <&gcc GCC_USB3_MOCK_UTMI_CLK>; 652 clock-names = "core", "sleep", "mock_utmi"; 653 ranges; 654 status = "disabled"; 655 656 dwc3@8a00000 { 657 compatible = "snps,dwc3"; 658 reg = <0x8a00000 0xf8000>; 659 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 660 phys = <&usb3_hs_phy>, <&usb3_ss_phy>; 661 phy-names = "usb2-phy", "usb3-phy"; 662 dr_mode = "host"; 663 }; 664 }; 665 666 usb2_hs_phy: hsphy@a8000 { 667 compatible = "qcom,usb-hs-ipq4019-phy"; 668 #phy-cells = <0>; 669 reg = <0xa8000 0x40>; 670 reg-names = "phy_base"; 671 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; 672 reset-names = "por_rst", "srif_rst"; 673 status = "disabled"; 674 }; 675 676 usb2: usb2@60f8800 { 677 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; 678 reg = <0x60f8800 0x100>; 679 #address-cells = <1>; 680 #size-cells = <1>; 681 clocks = <&gcc GCC_USB2_MASTER_CLK>, 682 <&gcc GCC_USB2_SLEEP_CLK>, 683 <&gcc GCC_USB2_MOCK_UTMI_CLK>; 684 clock-names = "master", "sleep", "mock_utmi"; 685 ranges; 686 status = "disabled"; 687 688 dwc3@6000000 { 689 compatible = "snps,dwc3"; 690 reg = <0x6000000 0xf8000>; 691 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 692 phys = <&usb2_hs_phy>; 693 phy-names = "usb2-phy"; 694 dr_mode = "host"; 695 }; 696 }; 697 }; 698}; 699