1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/dts-v1/; 3*724ba675SRob Herring 4*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 5*724ba675SRob Herring#include <dt-bindings/clock/qcom,gcc-apq8084.h> 6*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h> 7*724ba675SRob Herring 8*724ba675SRob Herring/ { 9*724ba675SRob Herring #address-cells = <1>; 10*724ba675SRob Herring #size-cells = <1>; 11*724ba675SRob Herring model = "Qualcomm APQ 8084"; 12*724ba675SRob Herring compatible = "qcom,apq8084"; 13*724ba675SRob Herring interrupt-parent = <&intc>; 14*724ba675SRob Herring 15*724ba675SRob Herring reserved-memory { 16*724ba675SRob Herring #address-cells = <1>; 17*724ba675SRob Herring #size-cells = <1>; 18*724ba675SRob Herring ranges; 19*724ba675SRob Herring 20*724ba675SRob Herring smem_mem: smem_region@fa00000 { 21*724ba675SRob Herring reg = <0xfa00000 0x200000>; 22*724ba675SRob Herring no-map; 23*724ba675SRob Herring }; 24*724ba675SRob Herring }; 25*724ba675SRob Herring 26*724ba675SRob Herring cpus { 27*724ba675SRob Herring #address-cells = <1>; 28*724ba675SRob Herring #size-cells = <0>; 29*724ba675SRob Herring 30*724ba675SRob Herring cpu@0 { 31*724ba675SRob Herring device_type = "cpu"; 32*724ba675SRob Herring compatible = "qcom,krait"; 33*724ba675SRob Herring reg = <0>; 34*724ba675SRob Herring enable-method = "qcom,kpss-acc-v2"; 35*724ba675SRob Herring next-level-cache = <&L2>; 36*724ba675SRob Herring qcom,acc = <&acc0>; 37*724ba675SRob Herring qcom,saw = <&saw0>; 38*724ba675SRob Herring cpu-idle-states = <&CPU_SPC>; 39*724ba675SRob Herring }; 40*724ba675SRob Herring 41*724ba675SRob Herring cpu@1 { 42*724ba675SRob Herring device_type = "cpu"; 43*724ba675SRob Herring compatible = "qcom,krait"; 44*724ba675SRob Herring reg = <1>; 45*724ba675SRob Herring enable-method = "qcom,kpss-acc-v2"; 46*724ba675SRob Herring next-level-cache = <&L2>; 47*724ba675SRob Herring qcom,acc = <&acc1>; 48*724ba675SRob Herring qcom,saw = <&saw1>; 49*724ba675SRob Herring cpu-idle-states = <&CPU_SPC>; 50*724ba675SRob Herring }; 51*724ba675SRob Herring 52*724ba675SRob Herring cpu@2 { 53*724ba675SRob Herring device_type = "cpu"; 54*724ba675SRob Herring compatible = "qcom,krait"; 55*724ba675SRob Herring reg = <2>; 56*724ba675SRob Herring enable-method = "qcom,kpss-acc-v2"; 57*724ba675SRob Herring next-level-cache = <&L2>; 58*724ba675SRob Herring qcom,acc = <&acc2>; 59*724ba675SRob Herring qcom,saw = <&saw2>; 60*724ba675SRob Herring cpu-idle-states = <&CPU_SPC>; 61*724ba675SRob Herring }; 62*724ba675SRob Herring 63*724ba675SRob Herring cpu@3 { 64*724ba675SRob Herring device_type = "cpu"; 65*724ba675SRob Herring compatible = "qcom,krait"; 66*724ba675SRob Herring reg = <3>; 67*724ba675SRob Herring enable-method = "qcom,kpss-acc-v2"; 68*724ba675SRob Herring next-level-cache = <&L2>; 69*724ba675SRob Herring qcom,acc = <&acc3>; 70*724ba675SRob Herring qcom,saw = <&saw3>; 71*724ba675SRob Herring cpu-idle-states = <&CPU_SPC>; 72*724ba675SRob Herring }; 73*724ba675SRob Herring 74*724ba675SRob Herring L2: l2-cache { 75*724ba675SRob Herring compatible = "cache"; 76*724ba675SRob Herring cache-level = <2>; 776c1561fbSLinus Torvalds cache-unified; 78*724ba675SRob Herring qcom,saw = <&saw_l2>; 79*724ba675SRob Herring }; 80*724ba675SRob Herring 81*724ba675SRob Herring idle-states { 82*724ba675SRob Herring CPU_SPC: spc { 83*724ba675SRob Herring compatible = "qcom,idle-state-spc", 84*724ba675SRob Herring "arm,idle-state"; 85*724ba675SRob Herring entry-latency-us = <150>; 86*724ba675SRob Herring exit-latency-us = <200>; 87*724ba675SRob Herring min-residency-us = <2000>; 88*724ba675SRob Herring }; 89*724ba675SRob Herring }; 90*724ba675SRob Herring }; 91*724ba675SRob Herring 92*724ba675SRob Herring memory { 93*724ba675SRob Herring device_type = "memory"; 94*724ba675SRob Herring reg = <0x0 0x0>; 95*724ba675SRob Herring }; 96*724ba675SRob Herring 97*724ba675SRob Herring firmware { 98*724ba675SRob Herring scm { 99*724ba675SRob Herring compatible = "qcom,scm-apq8084", "qcom,scm"; 100*724ba675SRob Herring clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 101*724ba675SRob Herring clock-names = "core", "bus", "iface"; 102*724ba675SRob Herring }; 103*724ba675SRob Herring }; 104*724ba675SRob Herring 105*724ba675SRob Herring thermal-zones { 106*724ba675SRob Herring cpu0-thermal { 107*724ba675SRob Herring polling-delay-passive = <250>; 108*724ba675SRob Herring polling-delay = <1000>; 109*724ba675SRob Herring 110*724ba675SRob Herring thermal-sensors = <&tsens 5>; 111*724ba675SRob Herring 112*724ba675SRob Herring trips { 113*724ba675SRob Herring cpu_alert0: trip0 { 114*724ba675SRob Herring temperature = <75000>; 115*724ba675SRob Herring hysteresis = <2000>; 116*724ba675SRob Herring type = "passive"; 117*724ba675SRob Herring }; 118*724ba675SRob Herring cpu_crit0: trip1 { 119*724ba675SRob Herring temperature = <110000>; 120*724ba675SRob Herring hysteresis = <2000>; 121*724ba675SRob Herring type = "critical"; 122*724ba675SRob Herring }; 123*724ba675SRob Herring }; 124*724ba675SRob Herring }; 125*724ba675SRob Herring 126*724ba675SRob Herring cpu1-thermal { 127*724ba675SRob Herring polling-delay-passive = <250>; 128*724ba675SRob Herring polling-delay = <1000>; 129*724ba675SRob Herring 130*724ba675SRob Herring thermal-sensors = <&tsens 6>; 131*724ba675SRob Herring 132*724ba675SRob Herring trips { 133*724ba675SRob Herring cpu_alert1: trip0 { 134*724ba675SRob Herring temperature = <75000>; 135*724ba675SRob Herring hysteresis = <2000>; 136*724ba675SRob Herring type = "passive"; 137*724ba675SRob Herring }; 138*724ba675SRob Herring cpu_crit1: trip1 { 139*724ba675SRob Herring temperature = <110000>; 140*724ba675SRob Herring hysteresis = <2000>; 141*724ba675SRob Herring type = "critical"; 142*724ba675SRob Herring }; 143*724ba675SRob Herring }; 144*724ba675SRob Herring }; 145*724ba675SRob Herring 146*724ba675SRob Herring cpu2-thermal { 147*724ba675SRob Herring polling-delay-passive = <250>; 148*724ba675SRob Herring polling-delay = <1000>; 149*724ba675SRob Herring 150*724ba675SRob Herring thermal-sensors = <&tsens 7>; 151*724ba675SRob Herring 152*724ba675SRob Herring trips { 153*724ba675SRob Herring cpu_alert2: trip0 { 154*724ba675SRob Herring temperature = <75000>; 155*724ba675SRob Herring hysteresis = <2000>; 156*724ba675SRob Herring type = "passive"; 157*724ba675SRob Herring }; 158*724ba675SRob Herring cpu_crit2: trip1 { 159*724ba675SRob Herring temperature = <110000>; 160*724ba675SRob Herring hysteresis = <2000>; 161*724ba675SRob Herring type = "critical"; 162*724ba675SRob Herring }; 163*724ba675SRob Herring }; 164*724ba675SRob Herring }; 165*724ba675SRob Herring 166*724ba675SRob Herring cpu3-thermal { 167*724ba675SRob Herring polling-delay-passive = <250>; 168*724ba675SRob Herring polling-delay = <1000>; 169*724ba675SRob Herring 170*724ba675SRob Herring thermal-sensors = <&tsens 8>; 171*724ba675SRob Herring 172*724ba675SRob Herring trips { 173*724ba675SRob Herring cpu_alert3: trip0 { 174*724ba675SRob Herring temperature = <75000>; 175*724ba675SRob Herring hysteresis = <2000>; 176*724ba675SRob Herring type = "passive"; 177*724ba675SRob Herring }; 178*724ba675SRob Herring cpu_crit3: trip1 { 179*724ba675SRob Herring temperature = <110000>; 180*724ba675SRob Herring hysteresis = <2000>; 181*724ba675SRob Herring type = "critical"; 182*724ba675SRob Herring }; 183*724ba675SRob Herring }; 184*724ba675SRob Herring }; 185*724ba675SRob Herring }; 186*724ba675SRob Herring 187*724ba675SRob Herring cpu-pmu { 188*724ba675SRob Herring compatible = "qcom,krait-pmu"; 189*724ba675SRob Herring interrupts = <GIC_PPI 7 0xf04>; 190*724ba675SRob Herring }; 191*724ba675SRob Herring 192*724ba675SRob Herring clocks { 193*724ba675SRob Herring xo_board: xo_board { 194*724ba675SRob Herring compatible = "fixed-clock"; 195*724ba675SRob Herring #clock-cells = <0>; 196*724ba675SRob Herring clock-frequency = <19200000>; 197*724ba675SRob Herring }; 198*724ba675SRob Herring 199*724ba675SRob Herring sleep_clk: sleep_clk { 200*724ba675SRob Herring compatible = "fixed-clock"; 201*724ba675SRob Herring #clock-cells = <0>; 202*724ba675SRob Herring clock-frequency = <32768>; 203*724ba675SRob Herring }; 204*724ba675SRob Herring }; 205*724ba675SRob Herring 206*724ba675SRob Herring timer { 207*724ba675SRob Herring compatible = "arm,armv7-timer"; 208*724ba675SRob Herring interrupts = <GIC_PPI 2 0xf08>, 209*724ba675SRob Herring <GIC_PPI 3 0xf08>, 210*724ba675SRob Herring <GIC_PPI 4 0xf08>, 211*724ba675SRob Herring <GIC_PPI 1 0xf08>; 212*724ba675SRob Herring clock-frequency = <19200000>; 213*724ba675SRob Herring }; 214*724ba675SRob Herring 215*724ba675SRob Herring smem { 216*724ba675SRob Herring compatible = "qcom,smem"; 217*724ba675SRob Herring 218*724ba675SRob Herring qcom,rpm-msg-ram = <&rpm_msg_ram>; 219*724ba675SRob Herring memory-region = <&smem_mem>; 220*724ba675SRob Herring 221*724ba675SRob Herring hwlocks = <&tcsr_mutex 3>; 222*724ba675SRob Herring }; 223*724ba675SRob Herring 224*724ba675SRob Herring soc: soc { 225*724ba675SRob Herring #address-cells = <1>; 226*724ba675SRob Herring #size-cells = <1>; 227*724ba675SRob Herring ranges; 228*724ba675SRob Herring compatible = "simple-bus"; 229*724ba675SRob Herring 230*724ba675SRob Herring intc: interrupt-controller@f9000000 { 231*724ba675SRob Herring compatible = "qcom,msm-qgic2"; 232*724ba675SRob Herring interrupt-controller; 233*724ba675SRob Herring #interrupt-cells = <3>; 234*724ba675SRob Herring reg = <0xf9000000 0x1000>, 235*724ba675SRob Herring <0xf9002000 0x1000>; 236*724ba675SRob Herring }; 237*724ba675SRob Herring 238*724ba675SRob Herring apcs: syscon@f9011000 { 239*724ba675SRob Herring compatible = "syscon"; 240*724ba675SRob Herring reg = <0xf9011000 0x1000>; 241*724ba675SRob Herring }; 242*724ba675SRob Herring 243*724ba675SRob Herring sram@fc190000 { 244*724ba675SRob Herring compatible = "qcom,apq8084-rpm-stats"; 245*724ba675SRob Herring reg = <0xfc190000 0x10000>; 246*724ba675SRob Herring }; 247*724ba675SRob Herring 248*724ba675SRob Herring qfprom: qfprom@fc4bc000 { 249*724ba675SRob Herring compatible = "qcom,apq8084-qfprom", "qcom,qfprom"; 250*724ba675SRob Herring reg = <0xfc4bc000 0x1000>; 251*724ba675SRob Herring #address-cells = <1>; 252*724ba675SRob Herring #size-cells = <1>; 253*724ba675SRob Herring 254*724ba675SRob Herring tsens_base1: base1@d0 { 255*724ba675SRob Herring reg = <0xd0 0x1>; 256*724ba675SRob Herring bits = <0 8>; 257*724ba675SRob Herring }; 258*724ba675SRob Herring 259*724ba675SRob Herring tsens_s0_p1: s0-p1@d1 { 260*724ba675SRob Herring reg = <0xd1 0x1>; 261*724ba675SRob Herring bits = <0 6>; 262*724ba675SRob Herring }; 263*724ba675SRob Herring 264*724ba675SRob Herring tsens_s1_p1: s1-p1@d2 { 265*724ba675SRob Herring reg = <0xd1 0x2>; 266*724ba675SRob Herring bits = <6 6>; 267*724ba675SRob Herring }; 268*724ba675SRob Herring 269*724ba675SRob Herring tsens_s2_p1: s2-p1@d2 { 270*724ba675SRob Herring reg = <0xd2 0x2>; 271*724ba675SRob Herring bits = <4 6>; 272*724ba675SRob Herring }; 273*724ba675SRob Herring 274*724ba675SRob Herring tsens_s3_p1: s3-p1@d3 { 275*724ba675SRob Herring reg = <0xd3 0x1>; 276*724ba675SRob Herring bits = <2 6>; 277*724ba675SRob Herring }; 278*724ba675SRob Herring 279*724ba675SRob Herring tsens_s4_p1: s4-p1@d4 { 280*724ba675SRob Herring reg = <0xd4 0x1>; 281*724ba675SRob Herring bits = <0 6>; 282*724ba675SRob Herring }; 283*724ba675SRob Herring 284*724ba675SRob Herring tsens_s5_p1: s5-p1@d4 { 285*724ba675SRob Herring reg = <0xd4 0x2>; 286*724ba675SRob Herring bits = <6 6>; 287*724ba675SRob Herring }; 288*724ba675SRob Herring 289*724ba675SRob Herring tsens_s6_p1: s6-p1@d5 { 290*724ba675SRob Herring reg = <0xd5 0x2>; 291*724ba675SRob Herring bits = <4 6>; 292*724ba675SRob Herring }; 293*724ba675SRob Herring 294*724ba675SRob Herring tsens_s7_p1: s7-p1@d6 { 295*724ba675SRob Herring reg = <0xd6 0x1>; 296*724ba675SRob Herring bits = <2 6>; 297*724ba675SRob Herring }; 298*724ba675SRob Herring 299*724ba675SRob Herring tsens_s8_p1: s8-p1@d7 { 300*724ba675SRob Herring reg = <0xd7 0x1>; 301*724ba675SRob Herring bits = <0 6>; 302*724ba675SRob Herring }; 303*724ba675SRob Herring 304*724ba675SRob Herring tsens_mode: mode@d7 { 305*724ba675SRob Herring reg = <0xd7 0x1>; 306*724ba675SRob Herring bits = <6 2>; 307*724ba675SRob Herring }; 308*724ba675SRob Herring 309*724ba675SRob Herring tsens_s9_p1: s9-p1@d8 { 310*724ba675SRob Herring reg = <0xd8 0x1>; 311*724ba675SRob Herring bits = <0 6>; 312*724ba675SRob Herring }; 313*724ba675SRob Herring 314*724ba675SRob Herring tsens_s10_p1: s10_p1@d8 { 315*724ba675SRob Herring reg = <0xd8 0x2>; 316*724ba675SRob Herring bits = <6 6>; 317*724ba675SRob Herring }; 318*724ba675SRob Herring 319*724ba675SRob Herring tsens_base2: base2@d9 { 320*724ba675SRob Herring reg = <0xd9 0x2>; 321*724ba675SRob Herring bits = <4 8>; 322*724ba675SRob Herring }; 323*724ba675SRob Herring 324*724ba675SRob Herring tsens_s0_p2: s0-p2@da { 325*724ba675SRob Herring reg = <0xda 0x2>; 326*724ba675SRob Herring bits = <4 6>; 327*724ba675SRob Herring }; 328*724ba675SRob Herring 329*724ba675SRob Herring tsens_s1_p2: s1-p2@db { 330*724ba675SRob Herring reg = <0xdb 0x1>; 331*724ba675SRob Herring bits = <2 6>; 332*724ba675SRob Herring }; 333*724ba675SRob Herring 334*724ba675SRob Herring tsens_s2_p2: s2-p2@dc { 335*724ba675SRob Herring reg = <0xdc 0x1>; 336*724ba675SRob Herring bits = <0 6>; 337*724ba675SRob Herring }; 338*724ba675SRob Herring 339*724ba675SRob Herring tsens_s3_p2: s3-p2@dc { 340*724ba675SRob Herring reg = <0xdc 0x2>; 341*724ba675SRob Herring bits = <6 6>; 342*724ba675SRob Herring }; 343*724ba675SRob Herring 344*724ba675SRob Herring tsens_s4_p2: s4-p2@dd { 345*724ba675SRob Herring reg = <0xdd 0x2>; 346*724ba675SRob Herring bits = <4 6>; 347*724ba675SRob Herring }; 348*724ba675SRob Herring 349*724ba675SRob Herring tsens_s5_p2: s5-p2@de { 350*724ba675SRob Herring reg = <0xde 0x2>; 351*724ba675SRob Herring bits = <2 6>; 352*724ba675SRob Herring }; 353*724ba675SRob Herring 354*724ba675SRob Herring tsens_s6_p2: s6-p2@df { 355*724ba675SRob Herring reg = <0xdf 0x1>; 356*724ba675SRob Herring bits = <0 6>; 357*724ba675SRob Herring }; 358*724ba675SRob Herring 359*724ba675SRob Herring tsens_s7_p2: s7-p2@e0 { 360*724ba675SRob Herring reg = <0xe0 0x1>; 361*724ba675SRob Herring bits = <0 6>; 362*724ba675SRob Herring }; 363*724ba675SRob Herring 364*724ba675SRob Herring tsens_s8_p2: s8-p2@e0 { 365*724ba675SRob Herring reg = <0xe0 0x2>; 366*724ba675SRob Herring bits = <6 6>; 367*724ba675SRob Herring }; 368*724ba675SRob Herring 369*724ba675SRob Herring tsens_s9_p2: s9-p2@e1 { 370*724ba675SRob Herring reg = <0xe1 0x2>; 371*724ba675SRob Herring bits = <4 6>; 372*724ba675SRob Herring }; 373*724ba675SRob Herring 374*724ba675SRob Herring tsens_s10_p2: s10_p2@e2 { 375*724ba675SRob Herring reg = <0xe2 0x2>; 376*724ba675SRob Herring bits = <2 6>; 377*724ba675SRob Herring }; 378*724ba675SRob Herring 379*724ba675SRob Herring tsens_s5_p2_backup: s5-p2_backup@e3 { 380*724ba675SRob Herring reg = <0xe3 0x2>; 381*724ba675SRob Herring bits = <0 6>; 382*724ba675SRob Herring }; 383*724ba675SRob Herring 384*724ba675SRob Herring tsens_mode_backup: mode_backup@e3 { 385*724ba675SRob Herring reg = <0xe3 0x1>; 386*724ba675SRob Herring bits = <6 2>; 387*724ba675SRob Herring }; 388*724ba675SRob Herring 389*724ba675SRob Herring tsens_s6_p2_backup: s6-p2_backup@e4 { 390*724ba675SRob Herring reg = <0xe4 0x1>; 391*724ba675SRob Herring bits = <0 6>; 392*724ba675SRob Herring }; 393*724ba675SRob Herring 394*724ba675SRob Herring tsens_s7_p2_backup: s7-p2_backup@e4 { 395*724ba675SRob Herring reg = <0xe4 0x2>; 396*724ba675SRob Herring bits = <6 6>; 397*724ba675SRob Herring }; 398*724ba675SRob Herring 399*724ba675SRob Herring tsens_s8_p2_backup: s8-p2_backup@e5 { 400*724ba675SRob Herring reg = <0xe5 0x2>; 401*724ba675SRob Herring bits = <4 6>; 402*724ba675SRob Herring }; 403*724ba675SRob Herring 404*724ba675SRob Herring tsens_s9_p2_backup: s9-p2_backup@e6 { 405*724ba675SRob Herring reg = <0xe6 0x2>; 406*724ba675SRob Herring bits = <2 6>; 407*724ba675SRob Herring }; 408*724ba675SRob Herring 409*724ba675SRob Herring tsens_s10_p2_backup: s10_p2_backup@e7 { 410*724ba675SRob Herring reg = <0xe7 0x1>; 411*724ba675SRob Herring bits = <0 6>; 412*724ba675SRob Herring }; 413*724ba675SRob Herring 414*724ba675SRob Herring tsens_base1_backup: base1_backup@440 { 415*724ba675SRob Herring reg = <0x440 0x1>; 416*724ba675SRob Herring bits = <0 8>; 417*724ba675SRob Herring }; 418*724ba675SRob Herring 419*724ba675SRob Herring tsens_s0_p1_backup: s0-p1_backup@441 { 420*724ba675SRob Herring reg = <0x441 0x1>; 421*724ba675SRob Herring bits = <0 6>; 422*724ba675SRob Herring }; 423*724ba675SRob Herring 424*724ba675SRob Herring tsens_s1_p1_backup: s1-p1_backup@442 { 425*724ba675SRob Herring reg = <0x441 0x2>; 426*724ba675SRob Herring bits = <6 6>; 427*724ba675SRob Herring }; 428*724ba675SRob Herring 429*724ba675SRob Herring tsens_s2_p1_backup: s2-p1_backup@442 { 430*724ba675SRob Herring reg = <0x442 0x2>; 431*724ba675SRob Herring bits = <4 6>; 432*724ba675SRob Herring }; 433*724ba675SRob Herring 434*724ba675SRob Herring tsens_s3_p1_backup: s3-p1_backup@443 { 435*724ba675SRob Herring reg = <0x443 0x1>; 436*724ba675SRob Herring bits = <2 6>; 437*724ba675SRob Herring }; 438*724ba675SRob Herring 439*724ba675SRob Herring tsens_s4_p1_backup: s4-p1_backup@444 { 440*724ba675SRob Herring reg = <0x444 0x1>; 441*724ba675SRob Herring bits = <0 6>; 442*724ba675SRob Herring }; 443*724ba675SRob Herring 444*724ba675SRob Herring tsens_s5_p1_backup: s5-p1_backup@444 { 445*724ba675SRob Herring reg = <0x444 0x2>; 446*724ba675SRob Herring bits = <6 6>; 447*724ba675SRob Herring }; 448*724ba675SRob Herring 449*724ba675SRob Herring tsens_s6_p1_backup: s6-p1_backup@445 { 450*724ba675SRob Herring reg = <0x445 0x2>; 451*724ba675SRob Herring bits = <4 6>; 452*724ba675SRob Herring }; 453*724ba675SRob Herring 454*724ba675SRob Herring tsens_s7_p1_backup: s7-p1_backup@446 { 455*724ba675SRob Herring reg = <0x446 0x1>; 456*724ba675SRob Herring bits = <2 6>; 457*724ba675SRob Herring }; 458*724ba675SRob Herring 459*724ba675SRob Herring tsens_use_backup: use_backup@447 { 460*724ba675SRob Herring reg = <0x447 0x1>; 461*724ba675SRob Herring bits = <5 3>; 462*724ba675SRob Herring }; 463*724ba675SRob Herring 464*724ba675SRob Herring tsens_s8_p1_backup: s8-p1_backup@448 { 465*724ba675SRob Herring reg = <0x448 0x1>; 466*724ba675SRob Herring bits = <0 6>; 467*724ba675SRob Herring }; 468*724ba675SRob Herring 469*724ba675SRob Herring tsens_s9_p1_backup: s9-p1_backup@448 { 470*724ba675SRob Herring reg = <0x448 0x2>; 471*724ba675SRob Herring bits = <6 6>; 472*724ba675SRob Herring }; 473*724ba675SRob Herring 474*724ba675SRob Herring tsens_s10_p1_backup: s10_p1_backup@449 { 475*724ba675SRob Herring reg = <0x449 0x2>; 476*724ba675SRob Herring bits = <4 6>; 477*724ba675SRob Herring }; 478*724ba675SRob Herring 479*724ba675SRob Herring tsens_base2_backup: base2_backup@44a { 480*724ba675SRob Herring reg = <0x44a 0x2>; 481*724ba675SRob Herring bits = <2 8>; 482*724ba675SRob Herring }; 483*724ba675SRob Herring 484*724ba675SRob Herring tsens_s0_p2_backup: s0-p2_backup@44b { 485*724ba675SRob Herring reg = <0x44b 0x3>; 486*724ba675SRob Herring bits = <2 6>; 487*724ba675SRob Herring }; 488*724ba675SRob Herring 489*724ba675SRob Herring tsens_s1_p2_backup: s1-p2_backup@44c { 490*724ba675SRob Herring reg = <0x44c 0x1>; 491*724ba675SRob Herring bits = <0 6>; 492*724ba675SRob Herring }; 493*724ba675SRob Herring 494*724ba675SRob Herring tsens_s2_p2_backup: s2-p2_backup@44c { 495*724ba675SRob Herring reg = <0x44c 0x2>; 496*724ba675SRob Herring bits = <6 6>; 497*724ba675SRob Herring }; 498*724ba675SRob Herring 499*724ba675SRob Herring tsens_s3_p2_backup: s3-p2_backup@44d { 500*724ba675SRob Herring reg = <0x44d 0x2>; 501*724ba675SRob Herring bits = <4 6>; 502*724ba675SRob Herring }; 503*724ba675SRob Herring 504*724ba675SRob Herring tsens_s4_p2_backup: s4-p2_backup@44e { 505*724ba675SRob Herring reg = <0x44e 0x1>; 506*724ba675SRob Herring bits = <2 6>; 507*724ba675SRob Herring }; 508*724ba675SRob Herring }; 509*724ba675SRob Herring 510*724ba675SRob Herring tsens: thermal-sensor@fc4a9000 { 511*724ba675SRob Herring compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; 512*724ba675SRob Herring reg = <0xfc4a9000 0x1000>, /* TM */ 513*724ba675SRob Herring <0xfc4a8000 0x1000>; /* SROT */ 514*724ba675SRob Herring nvmem-cells = <&tsens_mode>, 515*724ba675SRob Herring <&tsens_base1>, <&tsens_base2>, 516*724ba675SRob Herring <&tsens_use_backup>, 517*724ba675SRob Herring <&tsens_mode_backup>, 518*724ba675SRob Herring <&tsens_base1_backup>, <&tsens_base2_backup>, 519*724ba675SRob Herring <&tsens_s0_p1>, <&tsens_s0_p2>, 520*724ba675SRob Herring <&tsens_s1_p1>, <&tsens_s1_p2>, 521*724ba675SRob Herring <&tsens_s2_p1>, <&tsens_s2_p2>, 522*724ba675SRob Herring <&tsens_s3_p1>, <&tsens_s3_p2>, 523*724ba675SRob Herring <&tsens_s4_p1>, <&tsens_s4_p2>, 524*724ba675SRob Herring <&tsens_s5_p1>, <&tsens_s5_p2>, 525*724ba675SRob Herring <&tsens_s6_p1>, <&tsens_s6_p2>, 526*724ba675SRob Herring <&tsens_s7_p1>, <&tsens_s7_p2>, 527*724ba675SRob Herring <&tsens_s8_p1>, <&tsens_s8_p2>, 528*724ba675SRob Herring <&tsens_s9_p1>, <&tsens_s9_p2>, 529*724ba675SRob Herring <&tsens_s10_p1>, <&tsens_s10_p2>, 530*724ba675SRob Herring <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, 531*724ba675SRob Herring <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, 532*724ba675SRob Herring <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, 533*724ba675SRob Herring <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, 534*724ba675SRob Herring <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, 535*724ba675SRob Herring <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, 536*724ba675SRob Herring <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, 537*724ba675SRob Herring <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, 538*724ba675SRob Herring <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, 539*724ba675SRob Herring <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, 540*724ba675SRob Herring <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; 541*724ba675SRob Herring nvmem-cell-names = "mode", 542*724ba675SRob Herring "base1", "base2", 543*724ba675SRob Herring "use_backup", 544*724ba675SRob Herring "mode_backup", 545*724ba675SRob Herring "base1_backup", "base2_backup", 546*724ba675SRob Herring "s0_p1", "s0_p2", 547*724ba675SRob Herring "s1_p1", "s1_p2", 548*724ba675SRob Herring "s2_p1", "s2_p2", 549*724ba675SRob Herring "s3_p1", "s3_p2", 550*724ba675SRob Herring "s4_p1", "s4_p2", 551*724ba675SRob Herring "s5_p1", "s5_p2", 552*724ba675SRob Herring "s6_p1", "s6_p2", 553*724ba675SRob Herring "s7_p1", "s7_p2", 554*724ba675SRob Herring "s8_p1", "s8_p2", 555*724ba675SRob Herring "s9_p1", "s9_p2", 556*724ba675SRob Herring "s10_p1", "s10_p2", 557*724ba675SRob Herring "s0_p1_backup", "s0_p2_backup", 558*724ba675SRob Herring "s1_p1_backup", "s1_p2_backup", 559*724ba675SRob Herring "s2_p1_backup", "s2_p2_backup", 560*724ba675SRob Herring "s3_p1_backup", "s3_p2_backup", 561*724ba675SRob Herring "s4_p1_backup", "s4_p2_backup", 562*724ba675SRob Herring "s5_p1_backup", "s5_p2_backup", 563*724ba675SRob Herring "s6_p1_backup", "s6_p2_backup", 564*724ba675SRob Herring "s7_p1_backup", "s7_p2_backup", 565*724ba675SRob Herring "s8_p1_backup", "s8_p2_backup", 566*724ba675SRob Herring "s9_p1_backup", "s9_p2_backup", 567*724ba675SRob Herring "s10_p1_backup", "s10_p2_backup"; 568*724ba675SRob Herring #qcom,sensors = <11>; 569*724ba675SRob Herring interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 570*724ba675SRob Herring interrupt-names = "uplow"; 571*724ba675SRob Herring #thermal-sensor-cells = <1>; 572*724ba675SRob Herring }; 573*724ba675SRob Herring timer@f9020000 { 574*724ba675SRob Herring #address-cells = <1>; 575*724ba675SRob Herring #size-cells = <1>; 576*724ba675SRob Herring ranges; 577*724ba675SRob Herring compatible = "arm,armv7-timer-mem"; 578*724ba675SRob Herring reg = <0xf9020000 0x1000>; 579*724ba675SRob Herring clock-frequency = <19200000>; 580*724ba675SRob Herring 581*724ba675SRob Herring frame@f9021000 { 582*724ba675SRob Herring frame-number = <0>; 583*724ba675SRob Herring interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 584*724ba675SRob Herring <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 585*724ba675SRob Herring reg = <0xf9021000 0x1000>, 586*724ba675SRob Herring <0xf9022000 0x1000>; 587*724ba675SRob Herring }; 588*724ba675SRob Herring 589*724ba675SRob Herring frame@f9023000 { 590*724ba675SRob Herring frame-number = <1>; 591*724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 592*724ba675SRob Herring reg = <0xf9023000 0x1000>; 593*724ba675SRob Herring status = "disabled"; 594*724ba675SRob Herring }; 595*724ba675SRob Herring 596*724ba675SRob Herring frame@f9024000 { 597*724ba675SRob Herring frame-number = <2>; 598*724ba675SRob Herring interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 599*724ba675SRob Herring reg = <0xf9024000 0x1000>; 600*724ba675SRob Herring status = "disabled"; 601*724ba675SRob Herring }; 602*724ba675SRob Herring 603*724ba675SRob Herring frame@f9025000 { 604*724ba675SRob Herring frame-number = <3>; 605*724ba675SRob Herring interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 606*724ba675SRob Herring reg = <0xf9025000 0x1000>; 607*724ba675SRob Herring status = "disabled"; 608*724ba675SRob Herring }; 609*724ba675SRob Herring 610*724ba675SRob Herring frame@f9026000 { 611*724ba675SRob Herring frame-number = <4>; 612*724ba675SRob Herring interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 613*724ba675SRob Herring reg = <0xf9026000 0x1000>; 614*724ba675SRob Herring status = "disabled"; 615*724ba675SRob Herring }; 616*724ba675SRob Herring 617*724ba675SRob Herring frame@f9027000 { 618*724ba675SRob Herring frame-number = <5>; 619*724ba675SRob Herring interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 620*724ba675SRob Herring reg = <0xf9027000 0x1000>; 621*724ba675SRob Herring status = "disabled"; 622*724ba675SRob Herring }; 623*724ba675SRob Herring 624*724ba675SRob Herring frame@f9028000 { 625*724ba675SRob Herring frame-number = <6>; 626*724ba675SRob Herring interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 627*724ba675SRob Herring reg = <0xf9028000 0x1000>; 628*724ba675SRob Herring status = "disabled"; 629*724ba675SRob Herring }; 630*724ba675SRob Herring }; 631*724ba675SRob Herring 632*724ba675SRob Herring saw0: power-controller@f9089000 { 633*724ba675SRob Herring compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; 634*724ba675SRob Herring reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; 635*724ba675SRob Herring }; 636*724ba675SRob Herring 637*724ba675SRob Herring saw1: power-controller@f9099000 { 638*724ba675SRob Herring compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; 639*724ba675SRob Herring reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; 640*724ba675SRob Herring }; 641*724ba675SRob Herring 642*724ba675SRob Herring saw2: power-controller@f90a9000 { 643*724ba675SRob Herring compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; 644*724ba675SRob Herring reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; 645*724ba675SRob Herring }; 646*724ba675SRob Herring 647*724ba675SRob Herring saw3: power-controller@f90b9000 { 648*724ba675SRob Herring compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; 649*724ba675SRob Herring reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; 650*724ba675SRob Herring }; 651*724ba675SRob Herring 652*724ba675SRob Herring saw_l2: power-controller@f9012000 { 653*724ba675SRob Herring compatible = "qcom,saw2"; 654*724ba675SRob Herring reg = <0xf9012000 0x1000>; 655*724ba675SRob Herring regulator; 656*724ba675SRob Herring }; 657*724ba675SRob Herring 658*724ba675SRob Herring acc0: power-manager@f9088000 { 659*724ba675SRob Herring compatible = "qcom,kpss-acc-v2"; 660*724ba675SRob Herring reg = <0xf9088000 0x1000>, 661*724ba675SRob Herring <0xf9008000 0x1000>; 662*724ba675SRob Herring }; 663*724ba675SRob Herring 664*724ba675SRob Herring acc1: power-manager@f9098000 { 665*724ba675SRob Herring compatible = "qcom,kpss-acc-v2"; 666*724ba675SRob Herring reg = <0xf9098000 0x1000>, 667*724ba675SRob Herring <0xf9008000 0x1000>; 668*724ba675SRob Herring }; 669*724ba675SRob Herring 670*724ba675SRob Herring acc2: power-manager@f90a8000 { 671*724ba675SRob Herring compatible = "qcom,kpss-acc-v2"; 672*724ba675SRob Herring reg = <0xf90a8000 0x1000>, 673*724ba675SRob Herring <0xf9008000 0x1000>; 674*724ba675SRob Herring }; 675*724ba675SRob Herring 676*724ba675SRob Herring acc3: power-manager@f90b8000 { 677*724ba675SRob Herring compatible = "qcom,kpss-acc-v2"; 678*724ba675SRob Herring reg = <0xf90b8000 0x1000>, 679*724ba675SRob Herring <0xf9008000 0x1000>; 680*724ba675SRob Herring }; 681*724ba675SRob Herring 682*724ba675SRob Herring restart@fc4ab000 { 683*724ba675SRob Herring compatible = "qcom,pshold"; 684*724ba675SRob Herring reg = <0xfc4ab000 0x4>; 685*724ba675SRob Herring }; 686*724ba675SRob Herring 687*724ba675SRob Herring gcc: clock-controller@fc400000 { 688*724ba675SRob Herring compatible = "qcom,gcc-apq8084"; 689*724ba675SRob Herring #clock-cells = <1>; 690*724ba675SRob Herring #reset-cells = <1>; 691*724ba675SRob Herring #power-domain-cells = <1>; 692*724ba675SRob Herring reg = <0xfc400000 0x4000>; 693*724ba675SRob Herring clocks = <&xo_board>, 694*724ba675SRob Herring <&sleep_clk>, 695*724ba675SRob Herring <0>, /* ufs */ 696*724ba675SRob Herring <0>, 697*724ba675SRob Herring <0>, 698*724ba675SRob Herring <0>, 699*724ba675SRob Herring <0>, /* sata */ 700*724ba675SRob Herring <0>, 701*724ba675SRob Herring <0>; /* pcie */ 702*724ba675SRob Herring clock-names = "xo", 703*724ba675SRob Herring "sleep_clk", 704*724ba675SRob Herring "ufs_rx_symbol_0_clk_src", 705*724ba675SRob Herring "ufs_rx_symbol_1_clk_src", 706*724ba675SRob Herring "ufs_tx_symbol_0_clk_src", 707*724ba675SRob Herring "ufs_tx_symbol_1_clk_src", 708*724ba675SRob Herring "sata_asic0_clk", 709*724ba675SRob Herring "sata_rx_clk", 710*724ba675SRob Herring "pcie_pipe"; 711*724ba675SRob Herring }; 712*724ba675SRob Herring 713*724ba675SRob Herring tcsr_mutex: hwlock@fd484000 { 714*724ba675SRob Herring compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex"; 715*724ba675SRob Herring reg = <0xfd484000 0x1000>; 716*724ba675SRob Herring #hwlock-cells = <1>; 717*724ba675SRob Herring }; 718*724ba675SRob Herring 719*724ba675SRob Herring rpm_msg_ram: sram@fc428000 { 720*724ba675SRob Herring compatible = "qcom,rpm-msg-ram"; 721*724ba675SRob Herring reg = <0xfc428000 0x4000>; 722*724ba675SRob Herring }; 723*724ba675SRob Herring 724*724ba675SRob Herring tlmm: pinctrl@fd510000 { 725*724ba675SRob Herring compatible = "qcom,apq8084-pinctrl"; 726*724ba675SRob Herring reg = <0xfd510000 0x4000>; 727*724ba675SRob Herring gpio-controller; 728*724ba675SRob Herring gpio-ranges = <&tlmm 0 0 147>; 729*724ba675SRob Herring #gpio-cells = <2>; 730*724ba675SRob Herring interrupt-controller; 731*724ba675SRob Herring #interrupt-cells = <2>; 732*724ba675SRob Herring interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 733*724ba675SRob Herring }; 734*724ba675SRob Herring 735*724ba675SRob Herring blsp2_uart2: serial@f995e000 { 736*724ba675SRob Herring compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 737*724ba675SRob Herring reg = <0xf995e000 0x1000>; 738*724ba675SRob Herring interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 739*724ba675SRob Herring clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 740*724ba675SRob Herring clock-names = "core", "iface"; 741*724ba675SRob Herring status = "disabled"; 742*724ba675SRob Herring }; 743*724ba675SRob Herring 744*724ba675SRob Herring sdhc_1: mmc@f9824900 { 745*724ba675SRob Herring compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; 746*724ba675SRob Herring reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 747*724ba675SRob Herring reg-names = "hc", "core"; 748*724ba675SRob Herring interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 749*724ba675SRob Herring interrupt-names = "hc_irq", "pwr_irq"; 750*724ba675SRob Herring clocks = <&gcc GCC_SDCC1_AHB_CLK>, 751*724ba675SRob Herring <&gcc GCC_SDCC1_APPS_CLK>, 752*724ba675SRob Herring <&xo_board>; 753*724ba675SRob Herring clock-names = "iface", "core", "xo"; 754*724ba675SRob Herring status = "disabled"; 755*724ba675SRob Herring }; 756*724ba675SRob Herring 757*724ba675SRob Herring sdhc_2: mmc@f98a4900 { 758*724ba675SRob Herring compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; 759*724ba675SRob Herring reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 760*724ba675SRob Herring reg-names = "hc", "core"; 761*724ba675SRob Herring interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 762*724ba675SRob Herring interrupt-names = "hc_irq", "pwr_irq"; 763*724ba675SRob Herring clocks = <&gcc GCC_SDCC2_AHB_CLK>, 764*724ba675SRob Herring <&gcc GCC_SDCC2_APPS_CLK>, 765*724ba675SRob Herring <&xo_board>; 766*724ba675SRob Herring clock-names = "iface", "core", "xo"; 767*724ba675SRob Herring status = "disabled"; 768*724ba675SRob Herring }; 769*724ba675SRob Herring 770*724ba675SRob Herring spmi_bus: spmi@fc4cf000 { 771*724ba675SRob Herring compatible = "qcom,spmi-pmic-arb"; 772*724ba675SRob Herring reg-names = "core", "intr", "cnfg"; 773*724ba675SRob Herring reg = <0xfc4cf000 0x1000>, 774*724ba675SRob Herring <0xfc4cb000 0x1000>, 775*724ba675SRob Herring <0xfc4ca000 0x1000>; 776*724ba675SRob Herring interrupt-names = "periph_irq"; 777*724ba675SRob Herring interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 778*724ba675SRob Herring qcom,ee = <0>; 779*724ba675SRob Herring qcom,channel = <0>; 780*724ba675SRob Herring #address-cells = <2>; 781*724ba675SRob Herring #size-cells = <0>; 782*724ba675SRob Herring interrupt-controller; 783*724ba675SRob Herring #interrupt-cells = <4>; 784*724ba675SRob Herring }; 785*724ba675SRob Herring }; 786*724ba675SRob Herring 787*724ba675SRob Herring smd { 788*724ba675SRob Herring compatible = "qcom,smd"; 789*724ba675SRob Herring 790*724ba675SRob Herring rpm { 791*724ba675SRob Herring interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 792*724ba675SRob Herring qcom,ipc = <&apcs 8 0>; 793*724ba675SRob Herring qcom,smd-edge = <15>; 794*724ba675SRob Herring 795*724ba675SRob Herring rpm-requests { 796*724ba675SRob Herring compatible = "qcom,rpm-apq8084"; 797*724ba675SRob Herring qcom,smd-channels = "rpm_requests"; 798*724ba675SRob Herring 799*724ba675SRob Herring regulators-0 { 800*724ba675SRob Herring compatible = "qcom,rpm-pma8084-regulators"; 801*724ba675SRob Herring 802*724ba675SRob Herring pma8084_s1: s1 {}; 803*724ba675SRob Herring pma8084_s2: s2 {}; 804*724ba675SRob Herring pma8084_s3: s3 {}; 805*724ba675SRob Herring pma8084_s4: s4 {}; 806*724ba675SRob Herring pma8084_s5: s5 {}; 807*724ba675SRob Herring pma8084_s6: s6 {}; 808*724ba675SRob Herring pma8084_s7: s7 {}; 809*724ba675SRob Herring pma8084_s8: s8 {}; 810*724ba675SRob Herring pma8084_s9: s9 {}; 811*724ba675SRob Herring pma8084_s10: s10 {}; 812*724ba675SRob Herring pma8084_s11: s11 {}; 813*724ba675SRob Herring pma8084_s12: s12 {}; 814*724ba675SRob Herring 815*724ba675SRob Herring pma8084_l1: l1 {}; 816*724ba675SRob Herring pma8084_l2: l2 {}; 817*724ba675SRob Herring pma8084_l3: l3 {}; 818*724ba675SRob Herring pma8084_l4: l4 {}; 819*724ba675SRob Herring pma8084_l5: l5 {}; 820*724ba675SRob Herring pma8084_l6: l6 {}; 821*724ba675SRob Herring pma8084_l7: l7 {}; 822*724ba675SRob Herring pma8084_l8: l8 {}; 823*724ba675SRob Herring pma8084_l9: l9 {}; 824*724ba675SRob Herring pma8084_l10: l10 {}; 825*724ba675SRob Herring pma8084_l11: l11 {}; 826*724ba675SRob Herring pma8084_l12: l12 {}; 827*724ba675SRob Herring pma8084_l13: l13 {}; 828*724ba675SRob Herring pma8084_l14: l14 {}; 829*724ba675SRob Herring pma8084_l15: l15 {}; 830*724ba675SRob Herring pma8084_l16: l16 {}; 831*724ba675SRob Herring pma8084_l17: l17 {}; 832*724ba675SRob Herring pma8084_l18: l18 {}; 833*724ba675SRob Herring pma8084_l19: l19 {}; 834*724ba675SRob Herring pma8084_l20: l20 {}; 835*724ba675SRob Herring pma8084_l21: l21 {}; 836*724ba675SRob Herring pma8084_l22: l22 {}; 837*724ba675SRob Herring pma8084_l23: l23 {}; 838*724ba675SRob Herring pma8084_l24: l24 {}; 839*724ba675SRob Herring pma8084_l25: l25 {}; 840*724ba675SRob Herring pma8084_l26: l26 {}; 841*724ba675SRob Herring pma8084_l27: l27 {}; 842*724ba675SRob Herring 843*724ba675SRob Herring pma8084_lvs1: lvs1 {}; 844*724ba675SRob Herring pma8084_lvs2: lvs2 {}; 845*724ba675SRob Herring pma8084_lvs3: lvs3 {}; 846*724ba675SRob Herring pma8084_lvs4: lvs4 {}; 847*724ba675SRob Herring 848*724ba675SRob Herring pma8084_5vs1: 5vs1 {}; 849*724ba675SRob Herring }; 850*724ba675SRob Herring }; 851*724ba675SRob Herring }; 852*724ba675SRob Herring }; 853*724ba675SRob Herring}; 854