1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/clock/qcom,gcc-msm8960.h>
5#include <dt-bindings/clock/qcom,lcc-msm8960.h>
6#include <dt-bindings/reset/qcom,gcc-msm8960.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/soc/qcom,gsbi.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12/ {
13	#address-cells = <1>;
14	#size-cells = <1>;
15	model = "Qualcomm APQ8064";
16	compatible = "qcom,apq8064";
17	interrupt-parent = <&intc>;
18
19	reserved-memory {
20		#address-cells = <1>;
21		#size-cells = <1>;
22		ranges;
23
24		smem_region: smem@80000000 {
25			reg = <0x80000000 0x200000>;
26			no-map;
27		};
28
29		wcnss_mem: wcnss@8f000000 {
30			reg = <0x8f000000 0x700000>;
31			no-map;
32		};
33	};
34
35	cpus {
36		#address-cells = <1>;
37		#size-cells = <0>;
38
39		CPU0: cpu@0 {
40			compatible = "qcom,krait";
41			enable-method = "qcom,kpss-acc-v1";
42			device_type = "cpu";
43			reg = <0>;
44			next-level-cache = <&L2>;
45			qcom,acc = <&acc0>;
46			qcom,saw = <&saw0>;
47			cpu-idle-states = <&CPU_SPC>;
48		};
49
50		CPU1: cpu@1 {
51			compatible = "qcom,krait";
52			enable-method = "qcom,kpss-acc-v1";
53			device_type = "cpu";
54			reg = <1>;
55			next-level-cache = <&L2>;
56			qcom,acc = <&acc1>;
57			qcom,saw = <&saw1>;
58			cpu-idle-states = <&CPU_SPC>;
59		};
60
61		CPU2: cpu@2 {
62			compatible = "qcom,krait";
63			enable-method = "qcom,kpss-acc-v1";
64			device_type = "cpu";
65			reg = <2>;
66			next-level-cache = <&L2>;
67			qcom,acc = <&acc2>;
68			qcom,saw = <&saw2>;
69			cpu-idle-states = <&CPU_SPC>;
70		};
71
72		CPU3: cpu@3 {
73			compatible = "qcom,krait";
74			enable-method = "qcom,kpss-acc-v1";
75			device_type = "cpu";
76			reg = <3>;
77			next-level-cache = <&L2>;
78			qcom,acc = <&acc3>;
79			qcom,saw = <&saw3>;
80			cpu-idle-states = <&CPU_SPC>;
81		};
82
83		L2: l2-cache {
84			compatible = "cache";
85			cache-level = <2>;
86			cache-unified;
87		};
88
89		idle-states {
90			CPU_SPC: spc {
91				compatible = "qcom,idle-state-spc",
92						"arm,idle-state";
93				entry-latency-us = <400>;
94				exit-latency-us = <900>;
95				min-residency-us = <3000>;
96			};
97		};
98	};
99
100	memory@0 {
101		device_type = "memory";
102		reg = <0x0 0x0>;
103	};
104
105	thermal-zones {
106		cpu0-thermal {
107			polling-delay-passive = <250>;
108			polling-delay = <1000>;
109
110			thermal-sensors = <&tsens 7>;
111			coefficients = <1199 0>;
112
113			trips {
114				cpu_alert0: trip0 {
115					temperature = <75000>;
116					hysteresis = <2000>;
117					type = "passive";
118				};
119				cpu_crit0: trip1 {
120					temperature = <110000>;
121					hysteresis = <2000>;
122					type = "critical";
123				};
124			};
125		};
126
127		cpu1-thermal {
128			polling-delay-passive = <250>;
129			polling-delay = <1000>;
130
131			thermal-sensors = <&tsens 8>;
132			coefficients = <1132 0>;
133
134			trips {
135				cpu_alert1: trip0 {
136					temperature = <75000>;
137					hysteresis = <2000>;
138					type = "passive";
139				};
140				cpu_crit1: trip1 {
141					temperature = <110000>;
142					hysteresis = <2000>;
143					type = "critical";
144				};
145			};
146		};
147
148		cpu2-thermal {
149			polling-delay-passive = <250>;
150			polling-delay = <1000>;
151
152			thermal-sensors = <&tsens 9>;
153			coefficients = <1199 0>;
154
155			trips {
156				cpu_alert2: trip0 {
157					temperature = <75000>;
158					hysteresis = <2000>;
159					type = "passive";
160				};
161				cpu_crit2: trip1 {
162					temperature = <110000>;
163					hysteresis = <2000>;
164					type = "critical";
165				};
166			};
167		};
168
169		cpu3-thermal {
170			polling-delay-passive = <250>;
171			polling-delay = <1000>;
172
173			thermal-sensors = <&tsens 10>;
174			coefficients = <1132 0>;
175
176			trips {
177				cpu_alert3: trip0 {
178					temperature = <75000>;
179					hysteresis = <2000>;
180					type = "passive";
181				};
182				cpu_crit3: trip1 {
183					temperature = <110000>;
184					hysteresis = <2000>;
185					type = "critical";
186				};
187			};
188		};
189	};
190
191	cpu-pmu {
192		compatible = "qcom,krait-pmu";
193		interrupts = <1 10 0x304>;
194	};
195
196	clocks {
197		cxo_board: cxo_board {
198			compatible = "fixed-clock";
199			#clock-cells = <0>;
200			clock-frequency = <19200000>;
201		};
202
203		pxo_board: pxo_board {
204			compatible = "fixed-clock";
205			#clock-cells = <0>;
206			clock-frequency = <27000000>;
207		};
208
209		sleep_clk: sleep_clk {
210			compatible = "fixed-clock";
211			#clock-cells = <0>;
212			clock-frequency = <32768>;
213		};
214	};
215
216	sfpb_mutex: hwmutex {
217		compatible = "qcom,sfpb-mutex";
218		syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
219		#hwlock-cells = <1>;
220	};
221
222	smem {
223		compatible = "qcom,smem";
224		memory-region = <&smem_region>;
225
226		hwlocks = <&sfpb_mutex 3>;
227	};
228
229	smsm {
230		compatible = "qcom,smsm";
231
232		#address-cells = <1>;
233		#size-cells = <0>;
234
235		qcom,ipc-1 = <&l2cc 8 4>;
236		qcom,ipc-2 = <&l2cc 8 14>;
237		qcom,ipc-3 = <&l2cc 8 23>;
238		qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
239
240		apps_smsm: apps@0 {
241			reg = <0>;
242			#qcom,smem-state-cells = <1>;
243		};
244
245		modem_smsm: modem@1 {
246			reg = <1>;
247			interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
248
249			interrupt-controller;
250			#interrupt-cells = <2>;
251		};
252
253		q6_smsm: q6@2 {
254			reg = <2>;
255			interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
256
257			interrupt-controller;
258			#interrupt-cells = <2>;
259		};
260
261		wcnss_smsm: wcnss@3 {
262			reg = <3>;
263			interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
264
265			interrupt-controller;
266			#interrupt-cells = <2>;
267		};
268
269		dsps_smsm: dsps@4 {
270			reg = <4>;
271			interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
272
273			interrupt-controller;
274			#interrupt-cells = <2>;
275		};
276	};
277
278	firmware {
279		scm {
280			compatible = "qcom,scm-apq8064", "qcom,scm";
281
282			clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
283			clock-names = "core";
284		};
285	};
286
287
288	/*
289	 * These channels from the ADC are simply hardware monitors.
290	 * That is why the ADC is referred to as "HKADC" - HouseKeeping
291	 * ADC.
292	 */
293	iio-hwmon {
294		compatible = "iio-hwmon";
295		io-channels = <&xoadc 0x00 0x01>, /* Battery */
296			    <&xoadc 0x00 0x02>, /* DC in (charger) */
297			    <&xoadc 0x00 0x04>, /* VPH the main system voltage */
298			    <&xoadc 0x00 0x0b>, /* Die temperature */
299			    <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
300			    <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
301			    <&xoadc 0x00 0x0e>; /* Charger temperature */
302	};
303
304	soc: soc {
305		#address-cells = <1>;
306		#size-cells = <1>;
307		ranges;
308		compatible = "simple-bus";
309
310		tlmm_pinmux: pinctrl@800000 {
311			compatible = "qcom,apq8064-pinctrl";
312			reg = <0x800000 0x4000>;
313
314			gpio-controller;
315			gpio-ranges = <&tlmm_pinmux 0 0 90>;
316			#gpio-cells = <2>;
317			interrupt-controller;
318			#interrupt-cells = <2>;
319			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
320
321			pinctrl-names = "default";
322			pinctrl-0 = <&ps_hold>;
323		};
324
325		sfpb_wrapper_mutex: syscon@1200000 {
326			compatible = "syscon";
327			reg = <0x01200000 0x8000>;
328		};
329
330		intc: interrupt-controller@2000000 {
331			compatible = "qcom,msm-qgic2";
332			interrupt-controller;
333			#interrupt-cells = <3>;
334			reg = <0x02000000 0x1000>,
335			      <0x02002000 0x1000>;
336		};
337
338		timer@200a000 {
339			compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
340				     "qcom,msm-timer";
341			interrupts = <1 1 0x301>,
342				     <1 2 0x301>,
343				     <1 3 0x301>;
344			reg = <0x0200a000 0x100>;
345			clock-frequency = <27000000>;
346			cpu-offset = <0x80000>;
347		};
348
349		acc0: clock-controller@2088000 {
350			compatible = "qcom,kpss-acc-v1";
351			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
352			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
353			clock-names = "pll8_vote", "pxo";
354			clock-output-names = "acpu0_aux";
355			#clock-cells = <0>;
356		};
357
358		acc1: clock-controller@2098000 {
359			compatible = "qcom,kpss-acc-v1";
360			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
361			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
362			clock-names = "pll8_vote", "pxo";
363			clock-output-names = "acpu1_aux";
364			#clock-cells = <0>;
365		};
366
367		acc2: clock-controller@20a8000 {
368			compatible = "qcom,kpss-acc-v1";
369			reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
370			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
371			clock-names = "pll8_vote", "pxo";
372			clock-output-names = "acpu2_aux";
373			#clock-cells = <0>;
374		};
375
376		acc3: clock-controller@20b8000 {
377			compatible = "qcom,kpss-acc-v1";
378			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
379			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
380			clock-names = "pll8_vote", "pxo";
381			clock-output-names = "acpu3_aux";
382			#clock-cells = <0>;
383		};
384
385		saw0: power-controller@2089000 {
386			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
387			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
388			regulator;
389		};
390
391		saw1: power-controller@2099000 {
392			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
393			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
394			regulator;
395		};
396
397		saw2: power-controller@20a9000 {
398			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
399			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
400			regulator;
401		};
402
403		saw3: power-controller@20b9000 {
404			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
405			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
406			regulator;
407		};
408
409		sps_sic_non_secure: sps-sic-non-secure@12100000 {
410			compatible = "syscon";
411			reg = <0x12100000 0x10000>;
412		};
413
414		gsbi1: gsbi@12440000 {
415			status = "disabled";
416			compatible = "qcom,gsbi-v1.0.0";
417			cell-index = <1>;
418			reg = <0x12440000 0x100>;
419			clocks = <&gcc GSBI1_H_CLK>;
420			clock-names = "iface";
421			#address-cells = <1>;
422			#size-cells = <1>;
423			ranges;
424
425			syscon-tcsr = <&tcsr>;
426
427			gsbi1_serial: serial@12450000 {
428				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
429				reg = <0x12450000 0x100>,
430				      <0x12400000 0x03>;
431				interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
432				clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
433				clock-names = "core", "iface";
434				status = "disabled";
435			};
436
437			gsbi1_i2c: i2c@12460000 {
438				compatible = "qcom,i2c-qup-v1.1.1";
439				pinctrl-0 = <&i2c1_pins>;
440				pinctrl-1 = <&i2c1_pins_sleep>;
441				pinctrl-names = "default", "sleep";
442				reg = <0x12460000 0x1000>;
443				interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
444				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
445				clock-names = "core", "iface";
446				#address-cells = <1>;
447				#size-cells = <0>;
448				status = "disabled";
449			};
450
451		};
452
453		gsbi2: gsbi@12480000 {
454			status = "disabled";
455			compatible = "qcom,gsbi-v1.0.0";
456			cell-index = <2>;
457			reg = <0x12480000 0x100>;
458			clocks = <&gcc GSBI2_H_CLK>;
459			clock-names = "iface";
460			#address-cells = <1>;
461			#size-cells = <1>;
462			ranges;
463
464			syscon-tcsr = <&tcsr>;
465
466			gsbi2_i2c: i2c@124a0000 {
467				compatible = "qcom,i2c-qup-v1.1.1";
468				reg = <0x124a0000 0x1000>;
469				pinctrl-0 = <&i2c2_pins>;
470				pinctrl-1 = <&i2c2_pins_sleep>;
471				pinctrl-names = "default", "sleep";
472				interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
473				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
474				clock-names = "core", "iface";
475				#address-cells = <1>;
476				#size-cells = <0>;
477				status = "disabled";
478			};
479		};
480
481		gsbi3: gsbi@16200000 {
482			status = "disabled";
483			compatible = "qcom,gsbi-v1.0.0";
484			cell-index = <3>;
485			reg = <0x16200000 0x100>;
486			clocks = <&gcc GSBI3_H_CLK>;
487			clock-names = "iface";
488			#address-cells = <1>;
489			#size-cells = <1>;
490			ranges;
491			gsbi3_i2c: i2c@16280000 {
492				compatible = "qcom,i2c-qup-v1.1.1";
493				pinctrl-0 = <&i2c3_pins>;
494				pinctrl-1 = <&i2c3_pins_sleep>;
495				pinctrl-names = "default", "sleep";
496				reg = <0x16280000 0x1000>;
497				interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
498				clocks = <&gcc GSBI3_QUP_CLK>,
499					 <&gcc GSBI3_H_CLK>;
500				clock-names = "core", "iface";
501				#address-cells = <1>;
502				#size-cells = <0>;
503				status = "disabled";
504			};
505		};
506
507		gsbi4: gsbi@16300000 {
508			status = "disabled";
509			compatible = "qcom,gsbi-v1.0.0";
510			cell-index = <4>;
511			reg = <0x16300000 0x03>;
512			clocks = <&gcc GSBI4_H_CLK>;
513			clock-names = "iface";
514			#address-cells = <1>;
515			#size-cells = <1>;
516			ranges;
517
518			gsbi4_serial: serial@16340000 {
519				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
520				reg = <0x16340000 0x100>,
521				      <0x16300000 0x3>;
522				interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
523				pinctrl-0 = <&gsbi4_uart_pin_a>;
524				pinctrl-names = "default";
525				clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
526				clock-names = "core", "iface";
527				status = "disabled";
528			};
529
530			gsbi4_i2c: i2c@16380000 {
531				compatible = "qcom,i2c-qup-v1.1.1";
532				pinctrl-0 = <&i2c4_pins>;
533				pinctrl-1 = <&i2c4_pins_sleep>;
534				pinctrl-names = "default", "sleep";
535				reg = <0x16380000 0x1000>;
536				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
537				clocks = <&gcc GSBI4_QUP_CLK>,
538					 <&gcc GSBI4_H_CLK>;
539				clock-names = "core", "iface";
540				status = "disabled";
541			};
542		};
543
544		gsbi5: gsbi@1a200000 {
545			status = "disabled";
546			compatible = "qcom,gsbi-v1.0.0";
547			cell-index = <5>;
548			reg = <0x1a200000 0x03>;
549			clocks = <&gcc GSBI5_H_CLK>;
550			clock-names = "iface";
551			#address-cells = <1>;
552			#size-cells = <1>;
553			ranges;
554
555			gsbi5_serial: serial@1a240000 {
556				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
557				reg = <0x1a240000 0x100>,
558				      <0x1a200000 0x03>;
559				interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
560				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
561				clock-names = "core", "iface";
562				status = "disabled";
563			};
564
565			gsbi5_spi: spi@1a280000 {
566				compatible = "qcom,spi-qup-v1.1.1";
567				reg = <0x1a280000 0x1000>;
568				interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
569				pinctrl-0 = <&spi5_default>;
570				pinctrl-1 = <&spi5_sleep>;
571				pinctrl-names = "default", "sleep";
572				clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
573				clock-names = "core", "iface";
574				status = "disabled";
575				#address-cells = <1>;
576				#size-cells = <0>;
577			};
578		};
579
580		gsbi6: gsbi@16500000 {
581			status = "disabled";
582			compatible = "qcom,gsbi-v1.0.0";
583			cell-index = <6>;
584			reg = <0x16500000 0x03>;
585			clocks = <&gcc GSBI6_H_CLK>;
586			clock-names = "iface";
587			#address-cells = <1>;
588			#size-cells = <1>;
589			ranges;
590
591			gsbi6_serial: serial@16540000 {
592				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
593				reg = <0x16540000 0x100>,
594				      <0x16500000 0x03>;
595				interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
596				clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
597				clock-names = "core", "iface";
598				status = "disabled";
599			};
600
601			gsbi6_i2c: i2c@16580000 {
602				compatible = "qcom,i2c-qup-v1.1.1";
603				pinctrl-0 = <&i2c6_pins>;
604				pinctrl-1 = <&i2c6_pins_sleep>;
605				pinctrl-names = "default", "sleep";
606				reg = <0x16580000 0x1000>;
607				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
608				clocks = <&gcc GSBI6_QUP_CLK>,
609					 <&gcc GSBI6_H_CLK>;
610				clock-names = "core", "iface";
611				status = "disabled";
612			};
613		};
614
615		gsbi7: gsbi@16600000 {
616			status = "disabled";
617			compatible = "qcom,gsbi-v1.0.0";
618			cell-index = <7>;
619			reg = <0x16600000 0x100>;
620			clocks = <&gcc GSBI7_H_CLK>;
621			clock-names = "iface";
622			#address-cells = <1>;
623			#size-cells = <1>;
624			ranges;
625			syscon-tcsr = <&tcsr>;
626
627			gsbi7_serial: serial@16640000 {
628				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
629				reg = <0x16640000 0x1000>,
630				      <0x16600000 0x1000>;
631				interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
632				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
633				clock-names = "core", "iface";
634				status = "disabled";
635			};
636
637			gsbi7_i2c: i2c@16680000 {
638				compatible = "qcom,i2c-qup-v1.1.1";
639				pinctrl-0 = <&i2c7_pins>;
640				pinctrl-1 = <&i2c7_pins_sleep>;
641				pinctrl-names = "default", "sleep";
642				reg = <0x16680000 0x1000>;
643				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
644				clocks = <&gcc GSBI7_QUP_CLK>,
645					 <&gcc GSBI7_H_CLK>;
646				clock-names = "core", "iface";
647				status = "disabled";
648			};
649		};
650
651		rng@1a500000 {
652			compatible = "qcom,prng";
653			reg = <0x1a500000 0x200>;
654			clocks = <&gcc PRNG_CLK>;
655			clock-names = "core";
656		};
657
658		ssbi@c00000 {
659			compatible = "qcom,ssbi";
660			reg = <0x00c00000 0x1000>;
661			qcom,controller-type = "pmic-arbiter";
662
663			pm8821: pmic {
664				compatible = "qcom,pm8821";
665				interrupt-parent = <&tlmm_pinmux>;
666				interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
667				#interrupt-cells = <2>;
668				interrupt-controller;
669				#address-cells = <1>;
670				#size-cells = <0>;
671
672				pm8821_mpps: mpps@50 {
673					compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
674					reg = <0x50>;
675					interrupt-controller;
676					#interrupt-cells = <2>;
677					gpio-controller;
678					#gpio-cells = <2>;
679					gpio-ranges = <&pm8821_mpps 0 0 4>;
680				};
681			};
682		};
683
684		ssbi@500000 {
685			compatible = "qcom,ssbi";
686			reg = <0x00500000 0x1000>;
687			qcom,controller-type = "pmic-arbiter";
688
689			pmicintc: pmic {
690				compatible = "qcom,pm8921";
691				interrupt-parent = <&tlmm_pinmux>;
692				interrupts = <74 8>;
693				#interrupt-cells = <2>;
694				interrupt-controller;
695				#address-cells = <1>;
696				#size-cells = <0>;
697
698				pm8921_gpio: gpio@150 {
699
700					compatible = "qcom,pm8921-gpio",
701						     "qcom,ssbi-gpio";
702					reg = <0x150>;
703					interrupt-controller;
704					#interrupt-cells = <2>;
705					gpio-controller;
706					gpio-ranges = <&pm8921_gpio 0 0 44>;
707					#gpio-cells = <2>;
708
709				};
710
711				pm8921_mpps: mpps@50 {
712					compatible = "qcom,pm8921-mpp",
713						     "qcom,ssbi-mpp";
714					reg = <0x50>;
715					gpio-controller;
716					#gpio-cells = <2>;
717					gpio-ranges = <&pm8921_mpps 0 0 12>;
718					interrupt-controller;
719					#interrupt-cells = <2>;
720				};
721
722				rtc@11d {
723					compatible = "qcom,pm8921-rtc";
724					interrupt-parent = <&pmicintc>;
725					interrupts = <39 1>;
726					reg = <0x11d>;
727					allow-set-time;
728				};
729
730				pwrkey@1c {
731					compatible = "qcom,pm8921-pwrkey";
732					reg = <0x1c>;
733					interrupt-parent = <&pmicintc>;
734					interrupts = <50 1>, <51 1>;
735					debounce = <15625>;
736					pull-up;
737				};
738
739				xoadc: xoadc@197 {
740					compatible = "qcom,pm8921-adc";
741					reg = <197>;
742					interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
743					#address-cells = <2>;
744					#size-cells = <0>;
745					#io-channel-cells = <2>;
746
747					vcoin: adc-channel@0 {
748						reg = <0x00 0x00>;
749					};
750					vbat: adc-channel@1 {
751						reg = <0x00 0x01>;
752					};
753					dcin: adc-channel@2 {
754						reg = <0x00 0x02>;
755					};
756					vph_pwr: adc-channel@4 {
757						reg = <0x00 0x04>;
758					};
759					batt_therm: adc-channel@8 {
760						reg = <0x00 0x08>;
761					};
762					batt_id: adc-channel@9 {
763						reg = <0x00 0x09>;
764					};
765					usb_vbus: adc-channel@a {
766						reg = <0x00 0x0a>;
767					};
768					die_temp: adc-channel@b {
769						reg = <0x00 0x0b>;
770					};
771					ref_625mv: adc-channel@c {
772						reg = <0x00 0x0c>;
773					};
774					ref_1250mv: adc-channel@d {
775						reg = <0x00 0x0d>;
776					};
777					chg_temp: adc-channel@e {
778						reg = <0x00 0x0e>;
779					};
780					ref_muxoff: adc-channel@f {
781						reg = <0x00 0x0f>;
782					};
783				};
784			};
785		};
786
787		qfprom: qfprom@700000 {
788			compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
789			reg = <0x00700000 0x1000>;
790			#address-cells = <1>;
791			#size-cells = <1>;
792			ranges;
793			tsens_calib: calib@404 {
794				reg = <0x404 0x10>;
795			};
796			tsens_backup: backup_calib@414 {
797				reg = <0x414 0x10>;
798			};
799		};
800
801		gcc: clock-controller@900000 {
802			compatible = "qcom,gcc-apq8064", "syscon";
803			reg = <0x00900000 0x4000>;
804			#clock-cells = <1>;
805			#power-domain-cells = <1>;
806			#reset-cells = <1>;
807			clocks = <&cxo_board>,
808				 <&pxo_board>,
809				 <&lcc PLL4>;
810			clock-names = "cxo", "pxo", "pll4";
811
812			tsens: thermal-sensor {
813				compatible = "qcom,msm8960-tsens";
814
815				nvmem-cells = <&tsens_calib>, <&tsens_backup>;
816				nvmem-cell-names = "calib", "calib_backup";
817				interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
818				interrupt-names = "uplow";
819
820				#qcom,sensors = <11>;
821				#thermal-sensor-cells = <1>;
822			};
823		};
824
825		lcc: clock-controller@28000000 {
826			compatible = "qcom,lcc-apq8064";
827			reg = <0x28000000 0x1000>;
828			#clock-cells = <1>;
829			#reset-cells = <1>;
830			clocks = <&pxo_board>,
831				 <&gcc PLL4_VOTE>,
832				 <0>,
833				 <0>, <0>,
834				 <0>, <0>,
835				 <0>;
836			clock-names = "pxo",
837				      "pll4_vote",
838				      "mi2s_codec_clk",
839				      "codec_i2s_mic_codec_clk",
840				      "spare_i2s_mic_codec_clk",
841				      "codec_i2s_spkr_codec_clk",
842				      "spare_i2s_spkr_codec_clk",
843				      "pcm_codec_clk";
844		};
845
846		mmcc: clock-controller@4000000 {
847			compatible = "qcom,mmcc-apq8064";
848			reg = <0x4000000 0x1000>;
849			#clock-cells = <1>;
850			#power-domain-cells = <1>;
851			#reset-cells = <1>;
852			clocks = <&pxo_board>,
853				 <&gcc PLL3>,
854				 <&gcc PLL8_VOTE>,
855				 <&dsi0_phy 1>,
856				 <&dsi0_phy 0>,
857				 <&dsi1_phy 1>,
858				 <&dsi1_phy 0>,
859				 <&hdmi_phy>;
860			clock-names = "pxo",
861				      "pll3",
862				      "pll8_vote",
863				      "dsi1pll",
864				      "dsi1pllbyte",
865				      "dsi2pll",
866				      "dsi2pllbyte",
867				      "hdmipll";
868		};
869
870		l2cc: clock-controller@2011000 {
871			compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon";
872			reg = <0x2011000 0x1000>;
873			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
874			clock-names = "pll8_vote", "pxo";
875			#clock-cells = <0>;
876		};
877
878		rpm: rpm@108000 {
879			compatible = "qcom,rpm-apq8064";
880			reg = <0x108000 0x1000>;
881			qcom,ipc = <&l2cc 0x8 2>;
882
883			interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
884				     <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
885				     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
886			interrupt-names = "ack", "err", "wakeup";
887
888			rpmcc: clock-controller {
889				compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
890				#clock-cells = <1>;
891				clocks = <&pxo_board>, <&cxo_board>;
892				clock-names = "pxo", "cxo";
893			};
894
895			regulators {
896				compatible = "qcom,rpm-pm8921-regulators";
897
898				pm8921_s1: s1 {};
899				pm8921_s2: s2 {};
900				pm8921_s3: s3 {};
901				pm8921_s4: s4 {};
902				pm8921_s7: s7 {};
903				pm8921_s8: s8 {};
904
905				pm8921_l1: l1 {};
906				pm8921_l2: l2 {};
907				pm8921_l3: l3 {};
908				pm8921_l4: l4 {};
909				pm8921_l5: l5 {};
910				pm8921_l6: l6 {};
911				pm8921_l7: l7 {};
912				pm8921_l8: l8 {};
913				pm8921_l9: l9 {};
914				pm8921_l10: l10 {};
915				pm8921_l11: l11 {};
916				pm8921_l12: l12 {};
917				pm8921_l14: l14 {};
918				pm8921_l15: l15 {};
919				pm8921_l16: l16 {};
920				pm8921_l17: l17 {};
921				pm8921_l18: l18 {};
922				pm8921_l21: l21 {};
923				pm8921_l22: l22 {};
924				pm8921_l23: l23 {};
925				pm8921_l24: l24 {};
926				pm8921_l25: l25 {};
927				pm8921_l26: l26 {};
928				pm8921_l27: l27 {};
929				pm8921_l28: l28 {};
930				pm8921_l29: l29 {};
931
932				pm8921_lvs1: lvs1 {};
933				pm8921_lvs2: lvs2 {};
934				pm8921_lvs3: lvs3 {};
935				pm8921_lvs4: lvs4 {};
936				pm8921_lvs5: lvs5 {};
937				pm8921_lvs6: lvs6 {};
938				pm8921_lvs7: lvs7 {};
939
940				pm8921_usb_switch: usb-switch {};
941
942				pm8921_hdmi_switch: hdmi-switch {
943					bias-pull-down;
944				};
945
946				pm8921_ncp: ncp {};
947			};
948		};
949
950		usb1: usb@12500000 {
951			compatible = "qcom,ci-hdrc";
952			reg = <0x12500000 0x200>,
953			      <0x12500200 0x200>;
954			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
955			clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
956			clock-names = "core", "iface";
957			assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
958			assigned-clock-rates = <60000000>;
959			resets = <&gcc USB_HS1_RESET>;
960			reset-names = "core";
961			phy_type = "ulpi";
962			ahb-burst-config = <0>;
963			phys = <&usb_hs1_phy>;
964			phy-names = "usb-phy";
965			status = "disabled";
966			#reset-cells = <1>;
967
968			ulpi {
969				usb_hs1_phy: phy {
970					compatible = "qcom,usb-hs-phy-apq8064",
971						     "qcom,usb-hs-phy";
972					clocks = <&sleep_clk>, <&cxo_board>;
973					clock-names = "sleep", "ref";
974					resets = <&usb1 0>;
975					reset-names = "por";
976					#phy-cells = <0>;
977				};
978			};
979		};
980
981		usb3: usb@12520000 {
982			compatible = "qcom,ci-hdrc";
983			reg = <0x12520000 0x200>,
984			      <0x12520200 0x200>;
985			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
986			clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
987			clock-names = "core", "iface";
988			assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
989			assigned-clock-rates = <60000000>;
990			resets = <&gcc USB_HS3_RESET>;
991			reset-names = "core";
992			phy_type = "ulpi";
993			ahb-burst-config = <0>;
994			phys = <&usb_hs3_phy>;
995			phy-names = "usb-phy";
996			status = "disabled";
997			#reset-cells = <1>;
998
999			ulpi {
1000				usb_hs3_phy: phy {
1001					compatible = "qcom,usb-hs-phy-apq8064",
1002						     "qcom,usb-hs-phy";
1003					#phy-cells = <0>;
1004					clocks = <&sleep_clk>, <&cxo_board>;
1005					clock-names = "sleep", "ref";
1006					resets = <&usb3 0>;
1007					reset-names = "por";
1008				};
1009			};
1010		};
1011
1012		usb4: usb@12530000 {
1013			compatible = "qcom,ci-hdrc";
1014			reg = <0x12530000 0x200>,
1015			      <0x12530200 0x200>;
1016			interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
1017			clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
1018			clock-names = "core", "iface";
1019			assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1020			assigned-clock-rates = <60000000>;
1021			resets = <&gcc USB_HS4_RESET>;
1022			reset-names = "core";
1023			phy_type = "ulpi";
1024			ahb-burst-config = <0>;
1025			phys = <&usb_hs4_phy>;
1026			phy-names = "usb-phy";
1027			status = "disabled";
1028			#reset-cells = <1>;
1029
1030			ulpi {
1031				usb_hs4_phy: phy {
1032					compatible = "qcom,usb-hs-phy-apq8064",
1033						     "qcom,usb-hs-phy";
1034					#phy-cells = <0>;
1035					clocks = <&sleep_clk>, <&cxo_board>;
1036					clock-names = "sleep", "ref";
1037					resets = <&usb4 0>;
1038					reset-names = "por";
1039				};
1040			};
1041		};
1042
1043		sata_phy0: phy@1b400000 {
1044			compatible = "qcom,apq8064-sata-phy";
1045			status = "disabled";
1046			reg = <0x1b400000 0x200>;
1047			reg-names = "phy_mem";
1048			clocks = <&gcc SATA_PHY_CFG_CLK>;
1049			clock-names = "cfg";
1050			#phy-cells = <0>;
1051		};
1052
1053		sata0: sata@29000000 {
1054			compatible = "qcom,apq8064-ahci", "generic-ahci";
1055			status	 = "disabled";
1056			reg	 = <0x29000000 0x180>;
1057			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1058
1059			clocks = <&gcc SFAB_SATA_S_H_CLK>,
1060				 <&gcc SATA_H_CLK>,
1061				 <&gcc SATA_A_CLK>,
1062				 <&gcc SATA_RXOOB_CLK>,
1063				 <&gcc SATA_PMALIVE_CLK>;
1064			clock-names = "slave_iface",
1065				      "iface",
1066				      "bus",
1067				      "rxoob",
1068				      "core_pmalive";
1069
1070			assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1071					  <&gcc SATA_PMALIVE_CLK>;
1072			assigned-clock-rates = <100000000>, <100000000>;
1073
1074			phys = <&sata_phy0>;
1075			phy-names = "sata-phy";
1076			ports-implemented = <0x1>;
1077		};
1078
1079		sdcc3: mmc@12180000 {
1080			compatible = "arm,pl18x", "arm,primecell";
1081			arm,primecell-periphid = <0x00051180>;
1082			status = "disabled";
1083			reg = <0x12180000 0x2000>;
1084			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1085			clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1086			clock-names = "mclk", "apb_pclk";
1087			bus-width = <4>;
1088			cap-sd-highspeed;
1089			cap-mmc-highspeed;
1090			max-frequency = <192000000>;
1091			no-1-8-v;
1092			dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1093			dma-names = "tx", "rx";
1094		};
1095
1096		sdcc3bam: dma-controller@12182000 {
1097			compatible = "qcom,bam-v1.3.0";
1098			reg = <0x12182000 0x8000>;
1099			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
1100			clocks = <&gcc SDC3_H_CLK>;
1101			clock-names = "bam_clk";
1102			#dma-cells = <1>;
1103			qcom,ee = <0>;
1104		};
1105
1106		sdcc4: mmc@121c0000 {
1107			compatible = "arm,pl18x", "arm,primecell";
1108			arm,primecell-periphid = <0x00051180>;
1109			status = "disabled";
1110			reg = <0x121c0000 0x2000>;
1111			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1112			clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1113			clock-names = "mclk", "apb_pclk";
1114			bus-width = <4>;
1115			cap-sd-highspeed;
1116			cap-mmc-highspeed;
1117			max-frequency = <48000000>;
1118			dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1119			dma-names = "tx", "rx";
1120			pinctrl-names = "default";
1121			pinctrl-0 = <&sdc4_gpios>;
1122		};
1123
1124		sdcc4bam: dma-controller@121c2000 {
1125			compatible = "qcom,bam-v1.3.0";
1126			reg = <0x121c2000 0x8000>;
1127			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
1128			clocks = <&gcc SDC4_H_CLK>;
1129			clock-names = "bam_clk";
1130			#dma-cells = <1>;
1131			qcom,ee = <0>;
1132		};
1133
1134		sdcc1: mmc@12400000 {
1135			status = "disabled";
1136			compatible = "arm,pl18x", "arm,primecell";
1137			pinctrl-names = "default";
1138			pinctrl-0 = <&sdcc1_pins>;
1139			arm,primecell-periphid = <0x00051180>;
1140			reg = <0x12400000 0x2000>;
1141			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1142			clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1143			clock-names = "mclk", "apb_pclk";
1144			bus-width = <8>;
1145			max-frequency = <96000000>;
1146			non-removable;
1147			cap-sd-highspeed;
1148			cap-mmc-highspeed;
1149			dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1150			dma-names = "tx", "rx";
1151		};
1152
1153		sdcc1bam: dma-controller@12402000 {
1154			compatible = "qcom,bam-v1.3.0";
1155			reg = <0x12402000 0x8000>;
1156			interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1157			clocks = <&gcc SDC1_H_CLK>;
1158			clock-names = "bam_clk";
1159			#dma-cells = <1>;
1160			qcom,ee = <0>;
1161		};
1162
1163		tcsr: syscon@1a400000 {
1164			compatible = "qcom,tcsr-apq8064", "syscon";
1165			reg = <0x1a400000 0x100>;
1166		};
1167
1168		gpu: adreno-3xx@4300000 {
1169			compatible = "qcom,adreno-320.2", "qcom,adreno";
1170			reg = <0x04300000 0x20000>;
1171			reg-names = "kgsl_3d0_reg_memory";
1172			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1173			interrupt-names = "kgsl_3d0_irq";
1174			clock-names =
1175			    "core",
1176			    "iface",
1177			    "mem",
1178			    "mem_iface";
1179			clocks =
1180			    <&mmcc GFX3D_CLK>,
1181			    <&mmcc GFX3D_AHB_CLK>,
1182			    <&mmcc GFX3D_AXI_CLK>,
1183			    <&mmcc MMSS_IMEM_AHB_CLK>;
1184
1185			iommus = <&gfx3d 0
1186				  &gfx3d 1
1187				  &gfx3d 2
1188				  &gfx3d 3
1189				  &gfx3d 4
1190				  &gfx3d 5
1191				  &gfx3d 6
1192				  &gfx3d 7
1193				  &gfx3d 8
1194				  &gfx3d 9
1195				  &gfx3d 10
1196				  &gfx3d 11
1197				  &gfx3d 12
1198				  &gfx3d 13
1199				  &gfx3d 14
1200				  &gfx3d 15
1201				  &gfx3d 16
1202				  &gfx3d 17
1203				  &gfx3d 18
1204				  &gfx3d 19
1205				  &gfx3d 20
1206				  &gfx3d 21
1207				  &gfx3d 22
1208				  &gfx3d 23
1209				  &gfx3d 24
1210				  &gfx3d 25
1211				  &gfx3d 26
1212				  &gfx3d 27
1213				  &gfx3d 28
1214				  &gfx3d 29
1215				  &gfx3d 30
1216				  &gfx3d 31
1217				  &gfx3d1 0
1218				  &gfx3d1 1
1219				  &gfx3d1 2
1220				  &gfx3d1 3
1221				  &gfx3d1 4
1222				  &gfx3d1 5
1223				  &gfx3d1 6
1224				  &gfx3d1 7
1225				  &gfx3d1 8
1226				  &gfx3d1 9
1227				  &gfx3d1 10
1228				  &gfx3d1 11
1229				  &gfx3d1 12
1230				  &gfx3d1 13
1231				  &gfx3d1 14
1232				  &gfx3d1 15
1233				  &gfx3d1 16
1234				  &gfx3d1 17
1235				  &gfx3d1 18
1236				  &gfx3d1 19
1237				  &gfx3d1 20
1238				  &gfx3d1 21
1239				  &gfx3d1 22
1240				  &gfx3d1 23
1241				  &gfx3d1 24
1242				  &gfx3d1 25
1243				  &gfx3d1 26
1244				  &gfx3d1 27
1245				  &gfx3d1 28
1246				  &gfx3d1 29
1247				  &gfx3d1 30
1248				  &gfx3d1 31>;
1249
1250			operating-points-v2 = <&gpu_opp_table>;
1251
1252			gpu_opp_table: opp-table {
1253				compatible = "operating-points-v2";
1254
1255				opp-450000000 {
1256					opp-hz = /bits/ 64 <450000000>;
1257				};
1258
1259				opp-27000000 {
1260					opp-hz = /bits/ 64 <27000000>;
1261				};
1262			};
1263		};
1264
1265		mmss_sfpb: syscon@5700000 {
1266			compatible = "syscon";
1267			reg = <0x5700000 0x70>;
1268		};
1269
1270		dsi0: dsi@4700000 {
1271			compatible = "qcom,apq8064-dsi-ctrl",
1272				     "qcom,mdss-dsi-ctrl";
1273			label = "MDSS DSI CTRL->0";
1274			#address-cells = <1>;
1275			#size-cells = <0>;
1276			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1277			reg = <0x04700000 0x200>;
1278			reg-names = "dsi_ctrl";
1279
1280			clocks = <&mmcc DSI_M_AHB_CLK>,
1281				<&mmcc DSI_S_AHB_CLK>,
1282				<&mmcc AMP_AHB_CLK>,
1283				<&mmcc DSI_CLK>,
1284				<&mmcc DSI1_BYTE_CLK>,
1285				<&mmcc DSI_PIXEL_CLK>,
1286				<&mmcc DSI1_ESC_CLK>;
1287			clock-names = "iface", "bus", "core_mmss",
1288					"src", "byte", "pixel",
1289					"core";
1290
1291			assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1292					<&mmcc DSI1_ESC_SRC>,
1293					<&mmcc DSI_SRC>,
1294					<&mmcc DSI_PIXEL_SRC>;
1295			assigned-clock-parents = <&dsi0_phy 0>,
1296						<&dsi0_phy 0>,
1297						<&dsi0_phy 1>,
1298						<&dsi0_phy 1>;
1299			syscon-sfpb = <&mmss_sfpb>;
1300			phys = <&dsi0_phy>;
1301			status = "disabled";
1302
1303			ports {
1304				#address-cells = <1>;
1305				#size-cells = <0>;
1306
1307				port@0 {
1308					reg = <0>;
1309					dsi0_in: endpoint {
1310					};
1311				};
1312
1313				port@1 {
1314					reg = <1>;
1315					dsi0_out: endpoint {
1316					};
1317				};
1318			};
1319		};
1320
1321
1322		dsi0_phy: phy@4700200 {
1323			compatible = "qcom,dsi-phy-28nm-8960";
1324			#clock-cells = <1>;
1325			#phy-cells = <0>;
1326
1327			reg = <0x04700200 0x100>,
1328				<0x04700300 0x200>,
1329				<0x04700500 0x5c>;
1330			reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1331			clock-names = "iface", "ref";
1332			clocks = <&mmcc DSI_M_AHB_CLK>,
1333				 <&pxo_board>;
1334			status = "disabled";
1335		};
1336
1337		dsi1: dsi@5800000 {
1338			compatible = "qcom,mdss-dsi-ctrl";
1339			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1340			reg = <0x05800000 0x200>;
1341			reg-names = "dsi_ctrl";
1342
1343			clocks = <&mmcc DSI2_M_AHB_CLK>,
1344				 <&mmcc DSI2_S_AHB_CLK>,
1345				 <&mmcc AMP_AHB_CLK>,
1346				 <&mmcc DSI2_CLK>,
1347				 <&mmcc DSI2_BYTE_CLK>,
1348				 <&mmcc DSI2_PIXEL_CLK>,
1349				 <&mmcc DSI2_ESC_CLK>;
1350			clock-names = "iface",
1351				      "bus",
1352				      "core_mmss",
1353				      "src",
1354				      "byte",
1355				      "pixel",
1356				      "core";
1357
1358			assigned-clocks = <&mmcc DSI2_BYTE_SRC>,
1359					  <&mmcc DSI2_ESC_SRC>,
1360					  <&mmcc DSI2_SRC>,
1361					  <&mmcc DSI2_PIXEL_SRC>;
1362			assigned-clock-parents = <&dsi1_phy 0>,
1363						 <&dsi1_phy 0>,
1364						 <&dsi1_phy 1>,
1365						 <&dsi1_phy 1>;
1366
1367			syscon-sfpb = <&mmss_sfpb>;
1368			phys = <&dsi1_phy>;
1369
1370			#address-cells = <1>;
1371			#size-cells = <0>;
1372
1373			status = "disabled";
1374
1375			ports {
1376				#address-cells = <1>;
1377				#size-cells = <0>;
1378
1379				port@0 {
1380					reg = <0>;
1381					dsi1_in: endpoint {
1382					};
1383				};
1384
1385				port@1 {
1386					reg = <1>;
1387					dsi1_out: endpoint {
1388					};
1389				};
1390			};
1391		};
1392
1393
1394		dsi1_phy: dsi-phy@5800200 {
1395			compatible = "qcom,dsi-phy-28nm-8960";
1396			reg = <0x05800200 0x100>,
1397			      <0x05800300 0x200>,
1398			      <0x05800500 0x5c>;
1399			reg-names = "dsi_pll",
1400				    "dsi_phy",
1401				    "dsi_phy_regulator";
1402			clock-names = "iface",
1403				      "ref";
1404			clocks = <&mmcc DSI2_M_AHB_CLK>,
1405				 <&pxo_board>;
1406			#clock-cells = <1>;
1407			#phy-cells = <0>;
1408
1409			status = "disabled";
1410		};
1411
1412		mdp_port0: iommu@7500000 {
1413			compatible = "qcom,apq8064-iommu";
1414			#iommu-cells = <1>;
1415			clock-names =
1416			    "smmu_pclk",
1417			    "iommu_clk";
1418			clocks =
1419			    <&mmcc SMMU_AHB_CLK>,
1420			    <&mmcc MDP_AXI_CLK>;
1421			reg = <0x07500000 0x100000>;
1422			interrupts =
1423			    <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1424			    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1425			qcom,ncb = <2>;
1426		};
1427
1428		mdp_port1: iommu@7600000 {
1429			compatible = "qcom,apq8064-iommu";
1430			#iommu-cells = <1>;
1431			clock-names =
1432			    "smmu_pclk",
1433			    "iommu_clk";
1434			clocks =
1435			    <&mmcc SMMU_AHB_CLK>,
1436			    <&mmcc MDP_AXI_CLK>;
1437			reg = <0x07600000 0x100000>;
1438			interrupts =
1439			    <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1440			    <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1441			qcom,ncb = <2>;
1442		};
1443
1444		gfx3d: iommu@7c00000 {
1445			compatible = "qcom,apq8064-iommu";
1446			#iommu-cells = <1>;
1447			clock-names =
1448			    "smmu_pclk",
1449			    "iommu_clk";
1450			clocks =
1451			    <&mmcc SMMU_AHB_CLK>,
1452			    <&mmcc GFX3D_AXI_CLK>;
1453			reg = <0x07c00000 0x100000>;
1454			interrupts =
1455			    <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1456			    <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1457			qcom,ncb = <3>;
1458		};
1459
1460		gfx3d1: iommu@7d00000 {
1461			compatible = "qcom,apq8064-iommu";
1462			#iommu-cells = <1>;
1463			clock-names =
1464			    "smmu_pclk",
1465			    "iommu_clk";
1466			clocks =
1467			    <&mmcc SMMU_AHB_CLK>,
1468			    <&mmcc GFX3D_AXI_CLK>;
1469			reg = <0x07d00000 0x100000>;
1470			interrupts =
1471			    <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1472			    <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1473			qcom,ncb = <3>;
1474		};
1475
1476		pcie: pci@1b500000 {
1477			compatible = "qcom,pcie-apq8064";
1478			reg = <0x1b500000 0x1000>,
1479			      <0x1b502000 0x80>,
1480			      <0x1b600000 0x100>,
1481			      <0x0ff00000 0x100000>;
1482			reg-names = "dbi", "elbi", "parf", "config";
1483			device_type = "pci";
1484			linux,pci-domain = <0>;
1485			bus-range = <0x00 0xff>;
1486			num-lanes = <1>;
1487			#address-cells = <3>;
1488			#size-cells = <2>;
1489			ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */
1490				 <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */
1491			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1492			interrupt-names = "msi";
1493			#interrupt-cells = <1>;
1494			interrupt-map-mask = <0 0 0 0x7>;
1495			interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1496					<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1497					<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1498					<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1499			clocks = <&gcc PCIE_A_CLK>,
1500				 <&gcc PCIE_H_CLK>,
1501				 <&gcc PCIE_PHY_REF_CLK>;
1502			clock-names = "core", "iface", "phy";
1503			resets = <&gcc PCIE_ACLK_RESET>,
1504				 <&gcc PCIE_HCLK_RESET>,
1505				 <&gcc PCIE_POR_RESET>,
1506				 <&gcc PCIE_PCI_RESET>,
1507				 <&gcc PCIE_PHY_RESET>;
1508			reset-names = "axi", "ahb", "por", "pci", "phy";
1509			status = "disabled";
1510		};
1511
1512		hdmi: hdmi-tx@4a00000 {
1513			compatible = "qcom,hdmi-tx-8960";
1514			pinctrl-names = "default";
1515			pinctrl-0 = <&hdmi_pinctrl>;
1516			reg = <0x04a00000 0x2f0>;
1517			reg-names = "core_physical";
1518			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1519			clocks = <&mmcc HDMI_APP_CLK>,
1520				 <&mmcc HDMI_M_AHB_CLK>,
1521				 <&mmcc HDMI_S_AHB_CLK>;
1522			clock-names = "core",
1523				      "master_iface",
1524				      "slave_iface";
1525
1526			phys = <&hdmi_phy>;
1527
1528			status = "disabled";
1529
1530			ports {
1531				#address-cells = <1>;
1532				#size-cells = <0>;
1533
1534				port@0 {
1535					reg = <0>;
1536					hdmi_in: endpoint {
1537					};
1538				};
1539
1540				port@1 {
1541					reg = <1>;
1542					hdmi_out: endpoint {
1543					};
1544				};
1545			};
1546		};
1547
1548		hdmi_phy: phy@4a00400 {
1549			compatible = "qcom,hdmi-phy-8960";
1550			reg = <0x4a00400 0x60>,
1551			      <0x4a00500 0x100>;
1552			reg-names = "hdmi_phy",
1553				    "hdmi_pll";
1554
1555			clocks = <&mmcc HDMI_S_AHB_CLK>;
1556			clock-names = "slave_iface";
1557			#phy-cells = <0>;
1558			#clock-cells = <0>;
1559
1560			status = "disabled";
1561		};
1562
1563		mdp: display-controller@5100000 {
1564			compatible = "qcom,mdp4";
1565			reg = <0x05100000 0xf0000>;
1566			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1567			clocks = <&mmcc MDP_CLK>,
1568				 <&mmcc MDP_AHB_CLK>,
1569				 <&mmcc MDP_AXI_CLK>,
1570				 <&mmcc MDP_LUT_CLK>,
1571				 <&mmcc HDMI_TV_CLK>,
1572				 <&mmcc MDP_TV_CLK>;
1573			clock-names = "core_clk",
1574				      "iface_clk",
1575				      "bus_clk",
1576				      "lut_clk",
1577				      "hdmi_clk",
1578				      "tv_clk";
1579
1580			iommus = <&mdp_port0 0
1581				  &mdp_port0 2
1582				  &mdp_port1 0
1583				  &mdp_port1 2>;
1584
1585			ports {
1586				#address-cells = <1>;
1587				#size-cells = <0>;
1588
1589				port@0 {
1590					reg = <0>;
1591					mdp_lvds_out: endpoint {
1592					};
1593				};
1594
1595				port@1 {
1596					reg = <1>;
1597					mdp_dsi1_out: endpoint {
1598					};
1599				};
1600
1601				port@2 {
1602					reg = <2>;
1603					mdp_dsi2_out: endpoint {
1604					};
1605				};
1606
1607				port@3 {
1608					reg = <3>;
1609					mdp_dtv_out: endpoint {
1610					};
1611				};
1612			};
1613		};
1614
1615		riva: riva-pil@3200800 {
1616			compatible = "qcom,riva-pil";
1617
1618			reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1619			reg-names = "ccu", "dxe", "pmu";
1620
1621			interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1622					      <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1623			interrupt-names = "wdog", "fatal";
1624
1625			memory-region = <&wcnss_mem>;
1626
1627			vddcx-supply = <&pm8921_s3>;
1628			vddmx-supply = <&pm8921_l24>;
1629			vddpx-supply = <&pm8921_s4>;
1630
1631			status = "disabled";
1632
1633			iris {
1634				compatible = "qcom,wcn3660";
1635
1636				clocks = <&cxo_board>;
1637				clock-names = "xo";
1638
1639				vddxo-supply = <&pm8921_l4>;
1640				vddrfa-supply = <&pm8921_s2>;
1641				vddpa-supply = <&pm8921_l10>;
1642				vdddig-supply = <&pm8921_lvs2>;
1643			};
1644
1645			smd-edge {
1646				interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1647
1648				qcom,ipc = <&l2cc 8 25>;
1649				qcom,smd-edge = <6>;
1650
1651				label = "riva";
1652
1653				wcnss {
1654					compatible = "qcom,wcnss";
1655					qcom,smd-channels = "WCNSS_CTRL";
1656
1657					qcom,mmio = <&riva>;
1658
1659					bluetooth {
1660						compatible = "qcom,wcnss-bt";
1661					};
1662
1663					wifi {
1664						compatible = "qcom,wcnss-wlan";
1665
1666						interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1667							     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1668						interrupt-names = "tx", "rx";
1669
1670						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1671						qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1672					};
1673				};
1674			};
1675		};
1676
1677		etb@1a01000 {
1678			compatible = "arm,coresight-etb10", "arm,primecell";
1679			reg = <0x1a01000 0x1000>;
1680
1681			clocks = <&rpmcc RPM_QDSS_CLK>;
1682			clock-names = "apb_pclk";
1683
1684			in-ports {
1685				port {
1686					etb_in: endpoint {
1687						remote-endpoint = <&replicator_out0>;
1688					};
1689				};
1690			};
1691		};
1692
1693		tpiu@1a03000 {
1694			compatible = "arm,coresight-tpiu", "arm,primecell";
1695			reg = <0x1a03000 0x1000>;
1696
1697			clocks = <&rpmcc RPM_QDSS_CLK>;
1698			clock-names = "apb_pclk";
1699
1700			in-ports {
1701				port {
1702					tpiu_in: endpoint {
1703						remote-endpoint = <&replicator_out1>;
1704					};
1705				};
1706			};
1707		};
1708
1709		replicator {
1710			compatible = "arm,coresight-static-replicator";
1711
1712			clocks = <&rpmcc RPM_QDSS_CLK>;
1713			clock-names = "apb_pclk";
1714
1715			out-ports {
1716				#address-cells = <1>;
1717				#size-cells = <0>;
1718
1719				port@0 {
1720					reg = <0>;
1721					replicator_out0: endpoint {
1722						remote-endpoint = <&etb_in>;
1723					};
1724				};
1725				port@1 {
1726					reg = <1>;
1727					replicator_out1: endpoint {
1728						remote-endpoint = <&tpiu_in>;
1729					};
1730				};
1731			};
1732
1733			in-ports {
1734				port {
1735					replicator_in: endpoint {
1736						remote-endpoint = <&funnel_out>;
1737					};
1738				};
1739			};
1740		};
1741
1742		funnel@1a04000 {
1743			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1744			reg = <0x1a04000 0x1000>;
1745
1746			clocks = <&rpmcc RPM_QDSS_CLK>;
1747			clock-names = "apb_pclk";
1748
1749			in-ports {
1750				#address-cells = <1>;
1751				#size-cells = <0>;
1752
1753				/*
1754				 * Not described input ports:
1755				 * 2 - connected to STM component
1756				 * 3 - not-connected
1757				 * 6 - not-connected
1758				 * 7 - not-connected
1759				 */
1760				port@0 {
1761					reg = <0>;
1762					funnel_in0: endpoint {
1763						remote-endpoint = <&etm0_out>;
1764					};
1765				};
1766				port@1 {
1767					reg = <1>;
1768					funnel_in1: endpoint {
1769						remote-endpoint = <&etm1_out>;
1770					};
1771				};
1772				port@4 {
1773					reg = <4>;
1774					funnel_in4: endpoint {
1775						remote-endpoint = <&etm2_out>;
1776					};
1777				};
1778				port@5 {
1779					reg = <5>;
1780					funnel_in5: endpoint {
1781						remote-endpoint = <&etm3_out>;
1782					};
1783				};
1784			};
1785
1786			out-ports {
1787				port {
1788					funnel_out: endpoint {
1789						remote-endpoint = <&replicator_in>;
1790					};
1791				};
1792			};
1793		};
1794
1795		etm@1a1c000 {
1796			compatible = "arm,coresight-etm3x", "arm,primecell";
1797			reg = <0x1a1c000 0x1000>;
1798
1799			clocks = <&rpmcc RPM_QDSS_CLK>;
1800			clock-names = "apb_pclk";
1801
1802			cpu = <&CPU0>;
1803
1804			out-ports {
1805				port {
1806					etm0_out: endpoint {
1807						remote-endpoint = <&funnel_in0>;
1808					};
1809				};
1810			};
1811		};
1812
1813		etm@1a1d000 {
1814			compatible = "arm,coresight-etm3x", "arm,primecell";
1815			reg = <0x1a1d000 0x1000>;
1816
1817			clocks = <&rpmcc RPM_QDSS_CLK>;
1818			clock-names = "apb_pclk";
1819
1820			cpu = <&CPU1>;
1821
1822			out-ports {
1823				port {
1824					etm1_out: endpoint {
1825						remote-endpoint = <&funnel_in1>;
1826					};
1827				};
1828			};
1829		};
1830
1831		etm@1a1e000 {
1832			compatible = "arm,coresight-etm3x", "arm,primecell";
1833			reg = <0x1a1e000 0x1000>;
1834
1835			clocks = <&rpmcc RPM_QDSS_CLK>;
1836			clock-names = "apb_pclk";
1837
1838			cpu = <&CPU2>;
1839
1840			out-ports {
1841				port {
1842					etm2_out: endpoint {
1843						remote-endpoint = <&funnel_in4>;
1844					};
1845				};
1846			};
1847		};
1848
1849		etm@1a1f000 {
1850			compatible = "arm,coresight-etm3x", "arm,primecell";
1851			reg = <0x1a1f000 0x1000>;
1852
1853			clocks = <&rpmcc RPM_QDSS_CLK>;
1854			clock-names = "apb_pclk";
1855
1856			cpu = <&CPU3>;
1857
1858			out-ports {
1859				port {
1860					etm3_out: endpoint {
1861						remote-endpoint = <&funnel_in5>;
1862					};
1863				};
1864			};
1865		};
1866	};
1867};
1868#include "qcom-apq8064-pins.dtsi"
1869