xref: /openbmc/linux/arch/arm/boot/dts/nxp/mxs/imx28.dtsi (revision c4c3c32d) 
1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2012 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/gpio/gpio.h>
6#include "imx28-pinfunc.h"
7
8/ {
9	#address-cells = <1>;
10	#size-cells = <1>;
11
12	interrupt-parent = <&icoll>;
13	/*
14	 * The decompressor and also some bootloaders rely on a
15	 * pre-existing /chosen node to be available to insert the
16	 * command line and merge other ATAGS info.
17	 */
18	chosen {};
19
20	aliases {
21		ethernet0 = &mac0;
22		ethernet1 = &mac1;
23		gpio0 = &gpio0;
24		gpio1 = &gpio1;
25		gpio2 = &gpio2;
26		gpio3 = &gpio3;
27		gpio4 = &gpio4;
28		saif0 = &saif0;
29		saif1 = &saif1;
30		serial0 = &auart0;
31		serial1 = &auart1;
32		serial2 = &auart2;
33		serial3 = &auart3;
34		serial4 = &auart4;
35		spi0 = &ssp1;
36		spi1 = &ssp2;
37		usbphy0 = &usbphy0;
38		usbphy1 = &usbphy1;
39	};
40
41	cpus {
42		#address-cells = <1>;
43		#size-cells = <0>;
44
45		cpu@0 {
46			compatible = "arm,arm926ej-s";
47			device_type = "cpu";
48			reg = <0>;
49		};
50	};
51
52	apb@80000000 {
53		compatible = "simple-bus";
54		#address-cells = <1>;
55		#size-cells = <1>;
56		reg = <0x80000000 0x80000>;
57		ranges;
58
59		apbh@80000000 {
60			compatible = "simple-bus";
61			#address-cells = <1>;
62			#size-cells = <1>;
63			reg = <0x80000000 0x3c900>;
64			ranges;
65
66			icoll: interrupt-controller@80000000 {
67				compatible = "fsl,imx28-icoll", "fsl,icoll";
68				interrupt-controller;
69				#interrupt-cells = <1>;
70				reg = <0x80000000 0x2000>;
71			};
72
73			hsadc: hsadc@80002000 {
74				reg = <0x80002000 0x2000>;
75				interrupts = <13>;
76				dmas = <&dma_apbh 12>;
77				dma-names = "rx";
78				status = "disabled";
79			};
80
81			dma_apbh: dma-controller@80004000 {
82				compatible = "fsl,imx28-dma-apbh";
83				reg = <0x80004000 0x2000>;
84				interrupts = <82 83 84 85
85					      88 88 88 88
86					      88 88 88 88
87					      87 86 0 0>;
88				#dma-cells = <1>;
89				dma-channels = <16>;
90				clocks = <&clks 25>;
91			};
92
93			perfmon: perfmon@80006000 {
94				reg = <0x80006000 0x800>;
95				interrupts = <27>;
96				status = "disabled";
97			};
98
99			gpmi: nand-controller@8000c000 {
100				compatible = "fsl,imx28-gpmi-nand";
101				#address-cells = <1>;
102				#size-cells = <1>;
103				reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
104				reg-names = "gpmi-nand", "bch";
105				interrupts = <41>;
106				interrupt-names = "bch";
107				clocks = <&clks 50>;
108				clock-names = "gpmi_io";
109				assigned-clocks = <&clks 13>;
110				assigned-clock-parents = <&clks 10>;
111				dmas = <&dma_apbh 4>;
112				dma-names = "rx-tx";
113				status = "disabled";
114			};
115
116			ssp0: spi@80010000 {
117				#address-cells = <1>;
118				#size-cells = <0>;
119				reg = <0x80010000 0x2000>;
120				interrupts = <96>;
121				clocks = <&clks 46>;
122				dmas = <&dma_apbh 0>;
123				dma-names = "rx-tx";
124				status = "disabled";
125			};
126
127			ssp1: spi@80012000 {
128				#address-cells = <1>;
129				#size-cells = <0>;
130				reg = <0x80012000 0x2000>;
131				interrupts = <97>;
132				clocks = <&clks 47>;
133				dmas = <&dma_apbh 1>;
134				dma-names = "rx-tx";
135				status = "disabled";
136			};
137
138			ssp2: spi@80014000 {
139				#address-cells = <1>;
140				#size-cells = <0>;
141				reg = <0x80014000 0x2000>;
142				interrupts = <98>;
143				clocks = <&clks 48>;
144				dmas = <&dma_apbh 2>;
145				dma-names = "rx-tx";
146				status = "disabled";
147			};
148
149			ssp3: spi@80016000 {
150				#address-cells = <1>;
151				#size-cells = <0>;
152				reg = <0x80016000 0x2000>;
153				interrupts = <99>;
154				clocks = <&clks 49>;
155				dmas = <&dma_apbh 3>;
156				dma-names = "rx-tx";
157				status = "disabled";
158			};
159
160			pinctrl: pinctrl@80018000 {
161				#address-cells = <1>;
162				#size-cells = <0>;
163				compatible = "fsl,imx28-pinctrl", "simple-bus";
164				reg = <0x80018000 0x2000>;
165
166				gpio0: gpio@0 {
167					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
168					reg = <0>;
169					interrupts = <127>;
170					gpio-controller;
171					#gpio-cells = <2>;
172					interrupt-controller;
173					#interrupt-cells = <2>;
174				};
175
176				gpio1: gpio@1 {
177					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
178					reg = <1>;
179					interrupts = <126>;
180					gpio-controller;
181					#gpio-cells = <2>;
182					interrupt-controller;
183					#interrupt-cells = <2>;
184				};
185
186				gpio2: gpio@2 {
187					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
188					reg = <2>;
189					interrupts = <125>;
190					gpio-controller;
191					#gpio-cells = <2>;
192					interrupt-controller;
193					#interrupt-cells = <2>;
194				};
195
196				gpio3: gpio@3 {
197					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
198					reg = <3>;
199					interrupts = <124>;
200					gpio-controller;
201					#gpio-cells = <2>;
202					interrupt-controller;
203					#interrupt-cells = <2>;
204				};
205
206				gpio4: gpio@4 {
207					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
208					reg = <4>;
209					interrupts = <123>;
210					gpio-controller;
211					#gpio-cells = <2>;
212					interrupt-controller;
213					#interrupt-cells = <2>;
214				};
215
216				duart_pins_a: duart@0 {
217					reg = <0>;
218					fsl,pinmux-ids = <
219						MX28_PAD_PWM0__DUART_RX
220						MX28_PAD_PWM1__DUART_TX
221					>;
222					fsl,drive-strength = <MXS_DRIVE_4mA>;
223					fsl,voltage = <MXS_VOLTAGE_HIGH>;
224					fsl,pull-up = <MXS_PULL_DISABLE>;
225				};
226
227				duart_pins_b: duart@1 {
228					reg = <1>;
229					fsl,pinmux-ids = <
230						MX28_PAD_AUART0_CTS__DUART_RX
231						MX28_PAD_AUART0_RTS__DUART_TX
232					>;
233					fsl,drive-strength = <MXS_DRIVE_4mA>;
234					fsl,voltage = <MXS_VOLTAGE_HIGH>;
235					fsl,pull-up = <MXS_PULL_DISABLE>;
236				};
237
238				duart_4pins_a: duart-4pins@0 {
239					reg = <0>;
240					fsl,pinmux-ids = <
241						MX28_PAD_AUART0_CTS__DUART_RX
242						MX28_PAD_AUART0_RTS__DUART_TX
243						MX28_PAD_AUART0_RX__DUART_CTS
244						MX28_PAD_AUART0_TX__DUART_RTS
245					>;
246					fsl,drive-strength = <MXS_DRIVE_4mA>;
247					fsl,voltage = <MXS_VOLTAGE_HIGH>;
248					fsl,pull-up = <MXS_PULL_DISABLE>;
249				};
250
251				gpmi_pins_a: gpmi-nand@0 {
252					reg = <0>;
253					fsl,pinmux-ids = <
254						MX28_PAD_GPMI_D00__GPMI_D0
255						MX28_PAD_GPMI_D01__GPMI_D1
256						MX28_PAD_GPMI_D02__GPMI_D2
257						MX28_PAD_GPMI_D03__GPMI_D3
258						MX28_PAD_GPMI_D04__GPMI_D4
259						MX28_PAD_GPMI_D05__GPMI_D5
260						MX28_PAD_GPMI_D06__GPMI_D6
261						MX28_PAD_GPMI_D07__GPMI_D7
262						MX28_PAD_GPMI_CE0N__GPMI_CE0N
263						MX28_PAD_GPMI_RDY0__GPMI_READY0
264						MX28_PAD_GPMI_RDN__GPMI_RDN
265						MX28_PAD_GPMI_WRN__GPMI_WRN
266						MX28_PAD_GPMI_ALE__GPMI_ALE
267						MX28_PAD_GPMI_CLE__GPMI_CLE
268						MX28_PAD_GPMI_RESETN__GPMI_RESETN
269					>;
270					fsl,drive-strength = <MXS_DRIVE_4mA>;
271					fsl,voltage = <MXS_VOLTAGE_HIGH>;
272					fsl,pull-up = <MXS_PULL_DISABLE>;
273				};
274
275				gpmi_status_cfg: gpmi-status-cfg@0 {
276					reg = <0>;
277					fsl,pinmux-ids = <
278						MX28_PAD_GPMI_RDN__GPMI_RDN
279						MX28_PAD_GPMI_WRN__GPMI_WRN
280						MX28_PAD_GPMI_RESETN__GPMI_RESETN
281					>;
282					fsl,drive-strength = <MXS_DRIVE_12mA>;
283				};
284
285				auart0_pins_a: auart0@0 {
286					reg = <0>;
287					fsl,pinmux-ids = <
288						MX28_PAD_AUART0_RX__AUART0_RX
289						MX28_PAD_AUART0_TX__AUART0_TX
290						MX28_PAD_AUART0_CTS__AUART0_CTS
291						MX28_PAD_AUART0_RTS__AUART0_RTS
292					>;
293					fsl,drive-strength = <MXS_DRIVE_4mA>;
294					fsl,voltage = <MXS_VOLTAGE_HIGH>;
295					fsl,pull-up = <MXS_PULL_DISABLE>;
296				};
297
298				auart0_2pins_a: auart0-2pins@0 {
299					reg = <0>;
300					fsl,pinmux-ids = <
301						MX28_PAD_AUART0_RX__AUART0_RX
302						MX28_PAD_AUART0_TX__AUART0_TX
303					>;
304					fsl,drive-strength = <MXS_DRIVE_4mA>;
305					fsl,voltage = <MXS_VOLTAGE_HIGH>;
306					fsl,pull-up = <MXS_PULL_DISABLE>;
307				};
308
309				auart1_pins_a: auart1@0 {
310					reg = <0>;
311					fsl,pinmux-ids = <
312						MX28_PAD_AUART1_RX__AUART1_RX
313						MX28_PAD_AUART1_TX__AUART1_TX
314						MX28_PAD_AUART1_CTS__AUART1_CTS
315						MX28_PAD_AUART1_RTS__AUART1_RTS
316					>;
317					fsl,drive-strength = <MXS_DRIVE_4mA>;
318					fsl,voltage = <MXS_VOLTAGE_HIGH>;
319					fsl,pull-up = <MXS_PULL_DISABLE>;
320				};
321
322				auart1_2pins_a: auart1-2pins@0 {
323					reg = <0>;
324					fsl,pinmux-ids = <
325						MX28_PAD_AUART1_RX__AUART1_RX
326						MX28_PAD_AUART1_TX__AUART1_TX
327					>;
328					fsl,drive-strength = <MXS_DRIVE_4mA>;
329					fsl,voltage = <MXS_VOLTAGE_HIGH>;
330					fsl,pull-up = <MXS_PULL_DISABLE>;
331				};
332
333				auart2_2pins_a: auart2-2pins@0 {
334					reg = <0>;
335					fsl,pinmux-ids = <
336						MX28_PAD_SSP2_SCK__AUART2_RX
337						MX28_PAD_SSP2_MOSI__AUART2_TX
338					>;
339					fsl,drive-strength = <MXS_DRIVE_4mA>;
340					fsl,voltage = <MXS_VOLTAGE_HIGH>;
341					fsl,pull-up = <MXS_PULL_DISABLE>;
342				};
343
344				auart2_2pins_b: auart2-2pins@1 {
345					reg = <1>;
346					fsl,pinmux-ids = <
347						MX28_PAD_AUART2_RX__AUART2_RX
348						MX28_PAD_AUART2_TX__AUART2_TX
349					>;
350					fsl,drive-strength = <MXS_DRIVE_4mA>;
351					fsl,voltage = <MXS_VOLTAGE_HIGH>;
352					fsl,pull-up = <MXS_PULL_DISABLE>;
353				};
354
355				auart2_pins_a: auart2-pins@0 {
356					reg = <0>;
357					fsl,pinmux-ids = <
358						MX28_PAD_AUART2_RX__AUART2_RX
359						MX28_PAD_AUART2_TX__AUART2_TX
360						MX28_PAD_AUART2_CTS__AUART2_CTS
361						MX28_PAD_AUART2_RTS__AUART2_RTS
362					>;
363					fsl,drive-strength = <MXS_DRIVE_4mA>;
364					fsl,voltage = <MXS_VOLTAGE_HIGH>;
365					fsl,pull-up = <MXS_PULL_DISABLE>;
366				};
367
368				auart3_pins_a: auart3@0 {
369					reg = <0>;
370					fsl,pinmux-ids = <
371						MX28_PAD_AUART3_RX__AUART3_RX
372						MX28_PAD_AUART3_TX__AUART3_TX
373						MX28_PAD_AUART3_CTS__AUART3_CTS
374						MX28_PAD_AUART3_RTS__AUART3_RTS
375					>;
376					fsl,drive-strength = <MXS_DRIVE_4mA>;
377					fsl,voltage = <MXS_VOLTAGE_HIGH>;
378					fsl,pull-up = <MXS_PULL_DISABLE>;
379				};
380
381				auart3_2pins_a: auart3-2pins@0 {
382					reg = <0>;
383					fsl,pinmux-ids = <
384						MX28_PAD_SSP2_MISO__AUART3_RX
385						MX28_PAD_SSP2_SS0__AUART3_TX
386					>;
387					fsl,drive-strength = <MXS_DRIVE_4mA>;
388					fsl,voltage = <MXS_VOLTAGE_HIGH>;
389					fsl,pull-up = <MXS_PULL_DISABLE>;
390				};
391
392				auart3_2pins_b: auart3-2pins@1 {
393					reg = <1>;
394					fsl,pinmux-ids = <
395						MX28_PAD_AUART3_RX__AUART3_RX
396						MX28_PAD_AUART3_TX__AUART3_TX
397					>;
398					fsl,drive-strength = <MXS_DRIVE_4mA>;
399					fsl,voltage = <MXS_VOLTAGE_HIGH>;
400					fsl,pull-up = <MXS_PULL_DISABLE>;
401				};
402
403				auart4_2pins_a: auart4@0 {
404					reg = <0>;
405					fsl,pinmux-ids = <
406						MX28_PAD_SSP3_SCK__AUART4_TX
407						MX28_PAD_SSP3_MOSI__AUART4_RX
408					>;
409					fsl,drive-strength = <MXS_DRIVE_4mA>;
410					fsl,voltage = <MXS_VOLTAGE_HIGH>;
411					fsl,pull-up = <MXS_PULL_DISABLE>;
412				};
413
414				auart4_2pins_b: auart4@1 {
415					reg = <1>;
416					fsl,pinmux-ids = <
417						MX28_PAD_AUART0_CTS__AUART4_RX
418						MX28_PAD_AUART0_RTS__AUART4_TX
419					>;
420					fsl,drive-strength = <MXS_DRIVE_4mA>;
421					fsl,voltage = <MXS_VOLTAGE_HIGH>;
422					fsl,pull-up = <MXS_PULL_DISABLE>;
423				};
424
425				mac0_pins_a: mac0@0 {
426					reg = <0>;
427					fsl,pinmux-ids = <
428						MX28_PAD_ENET0_MDC__ENET0_MDC
429						MX28_PAD_ENET0_MDIO__ENET0_MDIO
430						MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
431						MX28_PAD_ENET0_RXD0__ENET0_RXD0
432						MX28_PAD_ENET0_RXD1__ENET0_RXD1
433						MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
434						MX28_PAD_ENET0_TXD0__ENET0_TXD0
435						MX28_PAD_ENET0_TXD1__ENET0_TXD1
436						MX28_PAD_ENET_CLK__CLKCTRL_ENET
437					>;
438					fsl,drive-strength = <MXS_DRIVE_8mA>;
439					fsl,voltage = <MXS_VOLTAGE_HIGH>;
440					fsl,pull-up = <MXS_PULL_ENABLE>;
441				};
442
443				mac0_pins_b: mac0@1 {
444					reg = <1>;
445					fsl,pinmux-ids = <
446						MX28_PAD_ENET0_MDC__ENET0_MDC
447						MX28_PAD_ENET0_MDIO__ENET0_MDIO
448						MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
449						MX28_PAD_ENET0_RXD0__ENET0_RXD0
450						MX28_PAD_ENET0_RXD1__ENET0_RXD1
451						MX28_PAD_ENET0_RXD2__ENET0_RXD2
452						MX28_PAD_ENET0_RXD3__ENET0_RXD3
453						MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
454						MX28_PAD_ENET0_TXD0__ENET0_TXD0
455						MX28_PAD_ENET0_TXD1__ENET0_TXD1
456						MX28_PAD_ENET0_TXD2__ENET0_TXD2
457						MX28_PAD_ENET0_TXD3__ENET0_TXD3
458						MX28_PAD_ENET_CLK__CLKCTRL_ENET
459						MX28_PAD_ENET0_COL__ENET0_COL
460						MX28_PAD_ENET0_CRS__ENET0_CRS
461						MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
462						MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
463						>;
464					fsl,drive-strength = <MXS_DRIVE_8mA>;
465					fsl,voltage = <MXS_VOLTAGE_HIGH>;
466					fsl,pull-up = <MXS_PULL_ENABLE>;
467				};
468
469				mac1_pins_a: mac1@0 {
470					reg = <0>;
471					fsl,pinmux-ids = <
472						MX28_PAD_ENET0_CRS__ENET1_RX_EN
473						MX28_PAD_ENET0_RXD2__ENET1_RXD0
474						MX28_PAD_ENET0_RXD3__ENET1_RXD1
475						MX28_PAD_ENET0_COL__ENET1_TX_EN
476						MX28_PAD_ENET0_TXD2__ENET1_TXD0
477						MX28_PAD_ENET0_TXD3__ENET1_TXD1
478					>;
479					fsl,drive-strength = <MXS_DRIVE_8mA>;
480					fsl,voltage = <MXS_VOLTAGE_HIGH>;
481					fsl,pull-up = <MXS_PULL_ENABLE>;
482				};
483
484				mmc0_8bit_pins_a: mmc0-8bit@0 {
485					reg = <0>;
486					fsl,pinmux-ids = <
487						MX28_PAD_SSP0_DATA0__SSP0_D0
488						MX28_PAD_SSP0_DATA1__SSP0_D1
489						MX28_PAD_SSP0_DATA2__SSP0_D2
490						MX28_PAD_SSP0_DATA3__SSP0_D3
491						MX28_PAD_SSP0_DATA4__SSP0_D4
492						MX28_PAD_SSP0_DATA5__SSP0_D5
493						MX28_PAD_SSP0_DATA6__SSP0_D6
494						MX28_PAD_SSP0_DATA7__SSP0_D7
495						MX28_PAD_SSP0_CMD__SSP0_CMD
496						MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
497						MX28_PAD_SSP0_SCK__SSP0_SCK
498					>;
499					fsl,drive-strength = <MXS_DRIVE_8mA>;
500					fsl,voltage = <MXS_VOLTAGE_HIGH>;
501					fsl,pull-up = <MXS_PULL_ENABLE>;
502				};
503
504				mmc0_4bit_pins_a: mmc0-4bit@0 {
505					reg = <0>;
506					fsl,pinmux-ids = <
507						MX28_PAD_SSP0_DATA0__SSP0_D0
508						MX28_PAD_SSP0_DATA1__SSP0_D1
509						MX28_PAD_SSP0_DATA2__SSP0_D2
510						MX28_PAD_SSP0_DATA3__SSP0_D3
511						MX28_PAD_SSP0_CMD__SSP0_CMD
512						MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
513						MX28_PAD_SSP0_SCK__SSP0_SCK
514					>;
515					fsl,drive-strength = <MXS_DRIVE_8mA>;
516					fsl,voltage = <MXS_VOLTAGE_HIGH>;
517					fsl,pull-up = <MXS_PULL_ENABLE>;
518				};
519
520				mmc0_cd_cfg: mmc0-cd-cfg@0 {
521					reg = <0>;
522					fsl,pinmux-ids = <
523						MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
524					>;
525					fsl,pull-up = <MXS_PULL_DISABLE>;
526				};
527
528				mmc0_sck_cfg: mmc0-sck-cfg@0 {
529					reg = <0>;
530					fsl,pinmux-ids = <
531						MX28_PAD_SSP0_SCK__SSP0_SCK
532					>;
533					fsl,drive-strength = <MXS_DRIVE_12mA>;
534					fsl,pull-up = <MXS_PULL_DISABLE>;
535				};
536
537				mmc1_4bit_pins_a: mmc1-4bit@0 {
538					reg = <0>;
539					fsl,pinmux-ids = <
540						MX28_PAD_GPMI_D00__SSP1_D0
541						MX28_PAD_GPMI_D01__SSP1_D1
542						MX28_PAD_GPMI_D02__SSP1_D2
543						MX28_PAD_GPMI_D03__SSP1_D3
544						MX28_PAD_GPMI_RDY1__SSP1_CMD
545						MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
546						MX28_PAD_GPMI_WRN__SSP1_SCK
547					>;
548					fsl,drive-strength = <MXS_DRIVE_8mA>;
549					fsl,voltage = <MXS_VOLTAGE_HIGH>;
550					fsl,pull-up = <MXS_PULL_ENABLE>;
551				};
552
553				mmc1_cd_cfg: mmc1-cd-cfg@0 {
554					reg = <0>;
555					fsl,pinmux-ids = <
556						MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
557					>;
558					fsl,pull-up = <MXS_PULL_DISABLE>;
559				};
560
561				mmc1_sck_cfg: mmc1-sck-cfg@0 {
562					reg = <0>;
563					fsl,pinmux-ids = <
564						MX28_PAD_GPMI_WRN__SSP1_SCK
565					>;
566					fsl,drive-strength = <MXS_DRIVE_12mA>;
567					fsl,pull-up = <MXS_PULL_DISABLE>;
568				};
569
570
571				mmc2_4bit_pins_a: mmc2-4bit@0 {
572					reg = <0>;
573					fsl,pinmux-ids = <
574						MX28_PAD_SSP0_DATA4__SSP2_D0
575						MX28_PAD_SSP1_SCK__SSP2_D1
576						MX28_PAD_SSP1_CMD__SSP2_D2
577						MX28_PAD_SSP0_DATA5__SSP2_D3
578						MX28_PAD_SSP0_DATA6__SSP2_CMD
579						MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
580						MX28_PAD_SSP0_DATA7__SSP2_SCK
581					>;
582					fsl,drive-strength = <MXS_DRIVE_8mA>;
583					fsl,voltage = <MXS_VOLTAGE_HIGH>;
584					fsl,pull-up = <MXS_PULL_ENABLE>;
585				};
586
587				mmc2_4bit_pins_b: mmc2-4bit@1 {
588					reg = <1>;
589					fsl,pinmux-ids = <
590						MX28_PAD_SSP2_SCK__SSP2_SCK
591						MX28_PAD_SSP2_MOSI__SSP2_CMD
592						MX28_PAD_SSP2_MISO__SSP2_D0
593						MX28_PAD_SSP2_SS0__SSP2_D3
594						MX28_PAD_SSP2_SS1__SSP2_D1
595						MX28_PAD_SSP2_SS2__SSP2_D2
596						MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
597					>;
598					fsl,drive-strength = <MXS_DRIVE_8mA>;
599					fsl,voltage = <MXS_VOLTAGE_HIGH>;
600					fsl,pull-up = <MXS_PULL_ENABLE>;
601				};
602
603				mmc2_cd_cfg: mmc2-cd-cfg@0 {
604					reg = <0>;
605					fsl,pinmux-ids = <
606						MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
607					>;
608					fsl,pull-up = <MXS_PULL_DISABLE>;
609				};
610
611				mmc2_sck_cfg_a: mmc2-sck-cfg@0 {
612					reg = <0>;
613					fsl,pinmux-ids = <
614						MX28_PAD_SSP0_DATA7__SSP2_SCK
615					>;
616					fsl,drive-strength = <MXS_DRIVE_12mA>;
617					fsl,pull-up = <MXS_PULL_DISABLE>;
618				};
619
620				mmc2_sck_cfg_b: mmc2-sck-cfg@1 {
621					reg = <1>;
622					fsl,pinmux-ids = <
623						MX28_PAD_SSP2_SCK__SSP2_SCK
624					>;
625					fsl,drive-strength = <MXS_DRIVE_12mA>;
626					fsl,pull-up = <MXS_PULL_DISABLE>;
627				};
628
629				i2c0_pins_a: i2c0@0 {
630					reg = <0>;
631					fsl,pinmux-ids = <
632						MX28_PAD_I2C0_SCL__I2C0_SCL
633						MX28_PAD_I2C0_SDA__I2C0_SDA
634					>;
635					fsl,drive-strength = <MXS_DRIVE_8mA>;
636					fsl,voltage = <MXS_VOLTAGE_HIGH>;
637					fsl,pull-up = <MXS_PULL_ENABLE>;
638				};
639
640				i2c0_pins_b: i2c0@1 {
641					reg = <1>;
642					fsl,pinmux-ids = <
643						MX28_PAD_AUART0_RX__I2C0_SCL
644						MX28_PAD_AUART0_TX__I2C0_SDA
645					>;
646					fsl,drive-strength = <MXS_DRIVE_8mA>;
647					fsl,voltage = <MXS_VOLTAGE_HIGH>;
648					fsl,pull-up = <MXS_PULL_ENABLE>;
649				};
650
651				i2c1_pins_a: i2c1@0 {
652					reg = <0>;
653					fsl,pinmux-ids = <
654						MX28_PAD_PWM0__I2C1_SCL
655						MX28_PAD_PWM1__I2C1_SDA
656					>;
657					fsl,drive-strength = <MXS_DRIVE_8mA>;
658					fsl,voltage = <MXS_VOLTAGE_HIGH>;
659					fsl,pull-up = <MXS_PULL_ENABLE>;
660				};
661
662				i2c1_pins_b: i2c1@1 {
663					reg = <1>;
664					fsl,pinmux-ids = <
665						MX28_PAD_AUART2_CTS__I2C1_SCL
666						MX28_PAD_AUART2_RTS__I2C1_SDA
667					>;
668					fsl,drive-strength = <MXS_DRIVE_8mA>;
669					fsl,voltage = <MXS_VOLTAGE_HIGH>;
670					fsl,pull-up = <MXS_PULL_ENABLE>;
671				};
672
673				saif0_pins_a: saif0@0 {
674					reg = <0>;
675					fsl,pinmux-ids = <
676						MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
677						MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
678						MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
679						MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
680					>;
681					fsl,drive-strength = <MXS_DRIVE_12mA>;
682					fsl,voltage = <MXS_VOLTAGE_HIGH>;
683					fsl,pull-up = <MXS_PULL_ENABLE>;
684				};
685
686				saif0_pins_b: saif0@1 {
687					reg = <1>;
688					fsl,pinmux-ids = <
689						MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
690						MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
691						MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
692					>;
693					fsl,drive-strength = <MXS_DRIVE_12mA>;
694					fsl,voltage = <MXS_VOLTAGE_HIGH>;
695					fsl,pull-up = <MXS_PULL_ENABLE>;
696				};
697
698				saif1_pins_a: saif1@0 {
699					reg = <0>;
700					fsl,pinmux-ids = <
701						MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
702					>;
703					fsl,drive-strength = <MXS_DRIVE_12mA>;
704					fsl,voltage = <MXS_VOLTAGE_HIGH>;
705					fsl,pull-up = <MXS_PULL_ENABLE>;
706				};
707
708				pwm0_pins_a: pwm0@0 {
709					reg = <0>;
710					fsl,pinmux-ids = <
711						MX28_PAD_PWM0__PWM_0
712					>;
713					fsl,drive-strength = <MXS_DRIVE_4mA>;
714					fsl,voltage = <MXS_VOLTAGE_HIGH>;
715					fsl,pull-up = <MXS_PULL_DISABLE>;
716				};
717
718				pwm2_pins_a: pwm2@0 {
719					reg = <0>;
720					fsl,pinmux-ids = <
721						MX28_PAD_PWM2__PWM_2
722					>;
723					fsl,drive-strength = <MXS_DRIVE_4mA>;
724					fsl,voltage = <MXS_VOLTAGE_HIGH>;
725					fsl,pull-up = <MXS_PULL_DISABLE>;
726				};
727
728				pwm3_pins_a: pwm3@0 {
729					reg = <0>;
730					fsl,pinmux-ids = <
731						MX28_PAD_PWM3__PWM_3
732					>;
733					fsl,drive-strength = <MXS_DRIVE_4mA>;
734					fsl,voltage = <MXS_VOLTAGE_HIGH>;
735					fsl,pull-up = <MXS_PULL_DISABLE>;
736				};
737
738				pwm3_pins_b: pwm3@1 {
739					reg = <1>;
740					fsl,pinmux-ids = <
741						MX28_PAD_SAIF0_MCLK__PWM_3
742					>;
743					fsl,drive-strength = <MXS_DRIVE_4mA>;
744					fsl,voltage = <MXS_VOLTAGE_HIGH>;
745					fsl,pull-up = <MXS_PULL_DISABLE>;
746				};
747
748				pwm4_pins_a: pwm4@0 {
749					reg = <0>;
750					fsl,pinmux-ids = <
751						MX28_PAD_PWM4__PWM_4
752					>;
753					fsl,drive-strength = <MXS_DRIVE_4mA>;
754					fsl,voltage = <MXS_VOLTAGE_HIGH>;
755					fsl,pull-up = <MXS_PULL_DISABLE>;
756				};
757
758				lcdif_24bit_pins_a: lcdif-24bit@0 {
759					reg = <0>;
760					fsl,pinmux-ids = <
761						MX28_PAD_LCD_D00__LCD_D0
762						MX28_PAD_LCD_D01__LCD_D1
763						MX28_PAD_LCD_D02__LCD_D2
764						MX28_PAD_LCD_D03__LCD_D3
765						MX28_PAD_LCD_D04__LCD_D4
766						MX28_PAD_LCD_D05__LCD_D5
767						MX28_PAD_LCD_D06__LCD_D6
768						MX28_PAD_LCD_D07__LCD_D7
769						MX28_PAD_LCD_D08__LCD_D8
770						MX28_PAD_LCD_D09__LCD_D9
771						MX28_PAD_LCD_D10__LCD_D10
772						MX28_PAD_LCD_D11__LCD_D11
773						MX28_PAD_LCD_D12__LCD_D12
774						MX28_PAD_LCD_D13__LCD_D13
775						MX28_PAD_LCD_D14__LCD_D14
776						MX28_PAD_LCD_D15__LCD_D15
777						MX28_PAD_LCD_D16__LCD_D16
778						MX28_PAD_LCD_D17__LCD_D17
779						MX28_PAD_LCD_D18__LCD_D18
780						MX28_PAD_LCD_D19__LCD_D19
781						MX28_PAD_LCD_D20__LCD_D20
782						MX28_PAD_LCD_D21__LCD_D21
783						MX28_PAD_LCD_D22__LCD_D22
784						MX28_PAD_LCD_D23__LCD_D23
785					>;
786					fsl,drive-strength = <MXS_DRIVE_4mA>;
787					fsl,voltage = <MXS_VOLTAGE_HIGH>;
788					fsl,pull-up = <MXS_PULL_DISABLE>;
789				};
790
791				lcdif_18bit_pins_a: lcdif-18bit@0 {
792					reg = <0>;
793					fsl,pinmux-ids = <
794						MX28_PAD_LCD_D00__LCD_D0
795						MX28_PAD_LCD_D01__LCD_D1
796						MX28_PAD_LCD_D02__LCD_D2
797						MX28_PAD_LCD_D03__LCD_D3
798						MX28_PAD_LCD_D04__LCD_D4
799						MX28_PAD_LCD_D05__LCD_D5
800						MX28_PAD_LCD_D06__LCD_D6
801						MX28_PAD_LCD_D07__LCD_D7
802						MX28_PAD_LCD_D08__LCD_D8
803						MX28_PAD_LCD_D09__LCD_D9
804						MX28_PAD_LCD_D10__LCD_D10
805						MX28_PAD_LCD_D11__LCD_D11
806						MX28_PAD_LCD_D12__LCD_D12
807						MX28_PAD_LCD_D13__LCD_D13
808						MX28_PAD_LCD_D14__LCD_D14
809						MX28_PAD_LCD_D15__LCD_D15
810						MX28_PAD_LCD_D16__LCD_D16
811						MX28_PAD_LCD_D17__LCD_D17
812					>;
813					fsl,drive-strength = <MXS_DRIVE_4mA>;
814					fsl,voltage = <MXS_VOLTAGE_HIGH>;
815					fsl,pull-up = <MXS_PULL_DISABLE>;
816				};
817
818				lcdif_16bit_pins_a: lcdif-16bit@0 {
819					reg = <0>;
820					fsl,pinmux-ids = <
821						MX28_PAD_LCD_D00__LCD_D0
822						MX28_PAD_LCD_D01__LCD_D1
823						MX28_PAD_LCD_D02__LCD_D2
824						MX28_PAD_LCD_D03__LCD_D3
825						MX28_PAD_LCD_D04__LCD_D4
826						MX28_PAD_LCD_D05__LCD_D5
827						MX28_PAD_LCD_D06__LCD_D6
828						MX28_PAD_LCD_D07__LCD_D7
829						MX28_PAD_LCD_D08__LCD_D8
830						MX28_PAD_LCD_D09__LCD_D9
831						MX28_PAD_LCD_D10__LCD_D10
832						MX28_PAD_LCD_D11__LCD_D11
833						MX28_PAD_LCD_D12__LCD_D12
834						MX28_PAD_LCD_D13__LCD_D13
835						MX28_PAD_LCD_D14__LCD_D14
836						MX28_PAD_LCD_D15__LCD_D15
837					>;
838					fsl,drive-strength = <MXS_DRIVE_4mA>;
839					fsl,voltage = <MXS_VOLTAGE_HIGH>;
840					fsl,pull-up = <MXS_PULL_DISABLE>;
841				};
842
843				lcdif_sync_pins_a: lcdif-sync@0 {
844					reg = <0>;
845					fsl,pinmux-ids = <
846						MX28_PAD_LCD_RS__LCD_DOTCLK
847						MX28_PAD_LCD_CS__LCD_ENABLE
848						MX28_PAD_LCD_RD_E__LCD_VSYNC
849						MX28_PAD_LCD_WR_RWN__LCD_HSYNC
850					>;
851					fsl,drive-strength = <MXS_DRIVE_4mA>;
852					fsl,voltage = <MXS_VOLTAGE_HIGH>;
853					fsl,pull-up = <MXS_PULL_DISABLE>;
854				};
855
856				can0_pins_a: can0@0 {
857					reg = <0>;
858					fsl,pinmux-ids = <
859						MX28_PAD_GPMI_RDY2__CAN0_TX
860						MX28_PAD_GPMI_RDY3__CAN0_RX
861					>;
862					fsl,drive-strength = <MXS_DRIVE_4mA>;
863					fsl,voltage = <MXS_VOLTAGE_HIGH>;
864					fsl,pull-up = <MXS_PULL_DISABLE>;
865				};
866
867				can1_pins_a: can1@0 {
868					reg = <0>;
869					fsl,pinmux-ids = <
870						MX28_PAD_GPMI_CE2N__CAN1_TX
871						MX28_PAD_GPMI_CE3N__CAN1_RX
872					>;
873					fsl,drive-strength = <MXS_DRIVE_4mA>;
874					fsl,voltage = <MXS_VOLTAGE_HIGH>;
875					fsl,pull-up = <MXS_PULL_DISABLE>;
876				};
877
878				spi2_pins_a: spi2@0 {
879					reg = <0>;
880					fsl,pinmux-ids = <
881						MX28_PAD_SSP2_SCK__SSP2_SCK
882						MX28_PAD_SSP2_MOSI__SSP2_CMD
883						MX28_PAD_SSP2_MISO__SSP2_D0
884						MX28_PAD_SSP2_SS0__SSP2_D3
885					>;
886					fsl,drive-strength = <MXS_DRIVE_8mA>;
887					fsl,voltage = <MXS_VOLTAGE_HIGH>;
888					fsl,pull-up = <MXS_PULL_ENABLE>;
889				};
890
891				spi3_pins_a: spi3@0 {
892					reg = <0>;
893					fsl,pinmux-ids = <
894						MX28_PAD_AUART2_RX__SSP3_D4
895						MX28_PAD_AUART2_TX__SSP3_D5
896						MX28_PAD_SSP3_SCK__SSP3_SCK
897						MX28_PAD_SSP3_MOSI__SSP3_CMD
898						MX28_PAD_SSP3_MISO__SSP3_D0
899						MX28_PAD_SSP3_SS0__SSP3_D3
900					>;
901					fsl,drive-strength = <MXS_DRIVE_8mA>;
902					fsl,voltage = <MXS_VOLTAGE_HIGH>;
903					fsl,pull-up = <MXS_PULL_DISABLE>;
904				};
905
906				spi3_pins_b: spi3@1 {
907					reg = <1>;
908					fsl,pinmux-ids = <
909						MX28_PAD_SSP3_SCK__SSP3_SCK
910						MX28_PAD_SSP3_MOSI__SSP3_CMD
911						MX28_PAD_SSP3_MISO__SSP3_D0
912						MX28_PAD_SSP3_SS0__SSP3_D3
913					>;
914					fsl,drive-strength = <MXS_DRIVE_8mA>;
915					fsl,voltage = <MXS_VOLTAGE_HIGH>;
916					fsl,pull-up = <MXS_PULL_ENABLE>;
917				};
918
919				usb0_pins_a: usb0@0 {
920					reg = <0>;
921					fsl,pinmux-ids = <
922						MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
923					>;
924					fsl,drive-strength = <MXS_DRIVE_12mA>;
925					fsl,voltage = <MXS_VOLTAGE_HIGH>;
926					fsl,pull-up = <MXS_PULL_DISABLE>;
927				};
928
929				usb0_pins_b: usb0@1 {
930					reg = <1>;
931					fsl,pinmux-ids = <
932						MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
933					>;
934					fsl,drive-strength = <MXS_DRIVE_12mA>;
935					fsl,voltage = <MXS_VOLTAGE_HIGH>;
936					fsl,pull-up = <MXS_PULL_DISABLE>;
937				};
938
939				usb1_pins_a: usb1@0 {
940					reg = <0>;
941					fsl,pinmux-ids = <
942						MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
943					>;
944					fsl,drive-strength = <MXS_DRIVE_12mA>;
945					fsl,voltage = <MXS_VOLTAGE_HIGH>;
946					fsl,pull-up = <MXS_PULL_DISABLE>;
947				};
948
949				usb1_pins_b: usb1@1 {
950					reg = <1>;
951					fsl,pinmux-ids = <
952						MX28_PAD_PWM2__USB1_OVERCURRENT
953					>;
954					fsl,drive-strength = <MXS_DRIVE_12mA>;
955					fsl,voltage = <MXS_VOLTAGE_HIGH>;
956					fsl,pull-up = <MXS_PULL_DISABLE>;
957				};
958
959				usb0_id_pins_a: usb0id@0 {
960					reg = <0>;
961					fsl,pinmux-ids = <
962						MX28_PAD_AUART1_RTS__USB0_ID
963					>;
964					fsl,drive-strength = <MXS_DRIVE_12mA>;
965					fsl,voltage = <MXS_VOLTAGE_HIGH>;
966					fsl,pull-up = <MXS_PULL_ENABLE>;
967				};
968
969				usb0_id_pins_b: usb0id1@0 {
970					reg = <0>;
971					fsl,pinmux-ids = <
972						MX28_PAD_PWM2__USB0_ID
973					>;
974					fsl,drive-strength = <MXS_DRIVE_12mA>;
975					fsl,voltage = <MXS_VOLTAGE_HIGH>;
976					fsl,pull-up = <MXS_PULL_ENABLE>;
977				};
978
979			};
980
981			digctl: digctl@8001c000 {
982				compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
983				reg = <0x8001c000 0x2000>;
984				interrupts = <89>;
985				status = "disabled";
986			};
987
988			etm: etm@80022000 {
989				reg = <0x80022000 0x2000>;
990				status = "disabled";
991			};
992
993			dma_apbx: dma-apbx@80024000 {
994				compatible = "fsl,imx28-dma-apbx";
995				reg = <0x80024000 0x2000>;
996				interrupts = <78 79 66 0
997					      80 81 68 69
998					      70 71 72 73
999					      74 75 76 77>;
1000				#dma-cells = <1>;
1001				dma-channels = <16>;
1002				clocks = <&clks 26>;
1003			};
1004
1005			dcp: crypto@80028000 {
1006				compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
1007				reg = <0x80028000 0x2000>;
1008				interrupts = <52 53 54>;
1009				status = "okay";
1010			};
1011
1012			pxp: pxp@8002a000 {
1013				reg = <0x8002a000 0x2000>;
1014				interrupts = <39>;
1015				status = "disabled";
1016			};
1017
1018			ocotp: efuse@8002c000 {
1019				compatible = "fsl,imx28-ocotp", "fsl,ocotp";
1020				#address-cells = <1>;
1021				#size-cells = <1>;
1022				reg = <0x8002c000 0x2000>;
1023				clocks = <&clks 25>;
1024			};
1025
1026			axi-ahb@8002e000 {
1027				reg = <0x8002e000 0x2000>;
1028				status = "disabled";
1029			};
1030
1031			lcdif: lcdif@80030000 {
1032				compatible = "fsl,imx28-lcdif";
1033				reg = <0x80030000 0x2000>;
1034				interrupts = <38>;
1035				clocks = <&clks 55>;
1036				dmas = <&dma_apbh 13>;
1037				dma-names = "rx";
1038				status = "disabled";
1039			};
1040
1041			can0: can@80032000 {
1042				compatible = "fsl,imx28-flexcan";
1043				reg = <0x80032000 0x2000>;
1044				interrupts = <8>;
1045				clocks = <&clks 58>, <&clks 58>;
1046				clock-names = "ipg", "per";
1047				status = "disabled";
1048			};
1049
1050			can1: can@80034000 {
1051				compatible = "fsl,imx28-flexcan";
1052				reg = <0x80034000 0x2000>;
1053				interrupts = <9>;
1054				clocks = <&clks 59>, <&clks 59>;
1055				clock-names = "ipg", "per";
1056				status = "disabled";
1057			};
1058
1059			simdbg: simdbg@8003c000 {
1060				reg = <0x8003c000 0x200>;
1061				status = "disabled";
1062			};
1063
1064			simgpmisel: simgpmisel@8003c200 {
1065				reg = <0x8003c200 0x100>;
1066				status = "disabled";
1067			};
1068
1069			simsspsel: simsspsel@8003c300 {
1070				reg = <0x8003c300 0x100>;
1071				status = "disabled";
1072			};
1073
1074			simmemsel: simmemsel@8003c400 {
1075				reg = <0x8003c400 0x100>;
1076				status = "disabled";
1077			};
1078
1079			gpiomon: gpiomon@8003c500 {
1080				reg = <0x8003c500 0x100>;
1081				status = "disabled";
1082			};
1083
1084			simenet: simenet@8003c700 {
1085				reg = <0x8003c700 0x100>;
1086				status = "disabled";
1087			};
1088
1089			armjtag: armjtag@8003c800 {
1090				reg = <0x8003c800 0x100>;
1091				status = "disabled";
1092			};
1093		};
1094
1095		apbx@80040000 {
1096			compatible = "simple-bus";
1097			#address-cells = <1>;
1098			#size-cells = <1>;
1099			reg = <0x80040000 0x40000>;
1100			ranges;
1101
1102			clks: clkctrl@80040000 {
1103				compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
1104				reg = <0x80040000 0x2000>;
1105				#clock-cells = <1>;
1106			};
1107
1108			saif0: saif@80042000 {
1109				#sound-dai-cells = <0>;
1110				compatible = "fsl,imx28-saif";
1111				reg = <0x80042000 0x2000>;
1112				interrupts = <59>;
1113				#clock-cells = <0>;
1114				clocks = <&clks 53>;
1115				dmas = <&dma_apbx 4>;
1116				dma-names = "rx-tx";
1117				status = "disabled";
1118			};
1119
1120			power: power@80044000 {
1121				reg = <0x80044000 0x2000>;
1122				status = "disabled";
1123			};
1124
1125			saif1: saif@80046000 {
1126				#sound-dai-cells = <0>;
1127				compatible = "fsl,imx28-saif";
1128				reg = <0x80046000 0x2000>;
1129				interrupts = <58>;
1130				clocks = <&clks 54>;
1131				dmas = <&dma_apbx 5>;
1132				dma-names = "rx-tx";
1133				status = "disabled";
1134			};
1135
1136			lradc: lradc@80050000 {
1137				compatible = "fsl,imx28-lradc";
1138				reg = <0x80050000 0x2000>;
1139				interrupts = <10 14 15 16 17 18 19
1140						20 21 22 23 24 25>;
1141				status = "disabled";
1142				clocks = <&clks 41>;
1143				#io-channel-cells = <1>;
1144			};
1145
1146			spdif: spdif@80054000 {
1147				reg = <0x80054000 0x2000>;
1148				interrupts = <45>;
1149				dmas = <&dma_apbx 2>;
1150				dma-names = "tx";
1151				status = "disabled";
1152			};
1153
1154			mxs_rtc: rtc@80056000 {
1155				compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
1156				reg = <0x80056000 0x2000>;
1157				interrupts = <29>;
1158			};
1159
1160			i2c0: i2c@80058000 {
1161				#address-cells = <1>;
1162				#size-cells = <0>;
1163				compatible = "fsl,imx28-i2c";
1164				reg = <0x80058000 0x2000>;
1165				interrupts = <111>;
1166				clock-frequency = <100000>;
1167				dmas = <&dma_apbx 6>;
1168				dma-names = "rx-tx";
1169				status = "disabled";
1170			};
1171
1172			i2c1: i2c@8005a000 {
1173				#address-cells = <1>;
1174				#size-cells = <0>;
1175				compatible = "fsl,imx28-i2c";
1176				reg = <0x8005a000 0x2000>;
1177				interrupts = <110>;
1178				clock-frequency = <100000>;
1179				dmas = <&dma_apbx 7>;
1180				dma-names = "rx-tx";
1181				status = "disabled";
1182			};
1183
1184			pwm: pwm@80064000 {
1185				compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
1186				reg = <0x80064000 0x2000>;
1187				clocks = <&clks 44>;
1188				#pwm-cells = <2>;
1189				fsl,pwm-number = <8>;
1190				status = "disabled";
1191			};
1192
1193			timer: timrot@80068000 {
1194				compatible = "fsl,imx28-timrot", "fsl,timrot";
1195				reg = <0x80068000 0x2000>;
1196				interrupts = <48 49 50 51>;
1197				clocks = <&clks 26>;
1198			};
1199
1200			auart0: serial@8006a000 {
1201				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1202				reg = <0x8006a000 0x2000>;
1203				interrupts = <112>;
1204				dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1205				dma-names = "rx", "tx";
1206				clocks = <&clks 45>;
1207				status = "disabled";
1208			};
1209
1210			auart1: serial@8006c000 {
1211				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1212				reg = <0x8006c000 0x2000>;
1213				interrupts = <113>;
1214				dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1215				dma-names = "rx", "tx";
1216				clocks = <&clks 45>;
1217				status = "disabled";
1218			};
1219
1220			auart2: serial@8006e000 {
1221				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1222				reg = <0x8006e000 0x2000>;
1223				interrupts = <114>;
1224				dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1225				dma-names = "rx", "tx";
1226				clocks = <&clks 45>;
1227				status = "disabled";
1228			};
1229
1230			auart3: serial@80070000 {
1231				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1232				reg = <0x80070000 0x2000>;
1233				interrupts = <115>;
1234				dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1235				dma-names = "rx", "tx";
1236				clocks = <&clks 45>;
1237				status = "disabled";
1238			};
1239
1240			auart4: serial@80072000 {
1241				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1242				reg = <0x80072000 0x2000>;
1243				interrupts = <116>;
1244				dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1245				dma-names = "rx", "tx";
1246				clocks = <&clks 45>;
1247				status = "disabled";
1248			};
1249
1250			duart: serial@80074000 {
1251				compatible = "arm,pl011", "arm,primecell";
1252				reg = <0x80074000 0x1000>;
1253				interrupts = <47>;
1254				clocks = <&clks 45>, <&clks 26>;
1255				clock-names = "uart", "apb_pclk";
1256				status = "disabled";
1257			};
1258
1259			usbphy0: usbphy@8007c000 {
1260				compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1261				reg = <0x8007c000 0x2000>;
1262				clocks = <&clks 62>;
1263				status = "disabled";
1264			};
1265
1266			usbphy1: usbphy@8007e000 {
1267				compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1268				reg = <0x8007e000 0x2000>;
1269				clocks = <&clks 63>;
1270				status = "disabled";
1271			};
1272		};
1273	};
1274
1275	ahb@80080000 {
1276		compatible = "simple-bus";
1277		#address-cells = <1>;
1278		#size-cells = <1>;
1279		reg = <0x80080000 0x80000>;
1280		ranges;
1281
1282		usb0: usb@80080000 {
1283			compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1284			reg = <0x80080000 0x10000>;
1285			interrupts = <93>;
1286			clocks = <&clks 60>;
1287			fsl,usbphy = <&usbphy0>;
1288			status = "disabled";
1289		};
1290
1291		usb1: usb@80090000 {
1292			compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1293			reg = <0x80090000 0x10000>;
1294			interrupts = <92>;
1295			clocks = <&clks 61>;
1296			fsl,usbphy = <&usbphy1>;
1297			dr_mode = "host";
1298			status = "disabled";
1299		};
1300
1301		dflpt: dflpt@800c0000 {
1302			reg = <0x800c0000 0x10000>;
1303			status = "disabled";
1304		};
1305
1306		mac0: ethernet@800f0000 {
1307			compatible = "fsl,imx28-fec";
1308			reg = <0x800f0000 0x4000>;
1309			interrupts = <101>;
1310			clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1311			clock-names = "ipg", "ahb", "enet_out";
1312			status = "disabled";
1313		};
1314
1315		mac1: ethernet@800f4000 {
1316			compatible = "fsl,imx28-fec";
1317			reg = <0x800f4000 0x4000>;
1318			interrupts = <102>;
1319			clocks = <&clks 57>, <&clks 57>;
1320			clock-names = "ipg", "ahb";
1321			status = "disabled";
1322		};
1323
1324		eth_switch: switch@800f8000 {
1325			reg = <0x800f8000 0x8000>;
1326			status = "disabled";
1327		};
1328	};
1329
1330	iio-hwmon {
1331		compatible = "iio-hwmon";
1332		io-channels = <&lradc 8>;
1333	};
1334};
1335