1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright 2018-2022 TQ-Systems GmbH 4 * Author: Markus Niebel <Markus.Niebel@tq-group.com> 5 */ 6 7/ { 8 model = "TQ-Systems MBA6ULx Baseboard"; 9 10 aliases { 11 mmc0 = &usdhc2; 12 mmc1 = &usdhc1; 13 rtc0 = &rtc0; 14 rtc1 = &snvs_rtc; 15 }; 16 17 chosen { 18 stdout-path = &uart1; 19 }; 20 21 backlight: backlight { 22 compatible = "pwm-backlight"; 23 power-supply = <®_mba6ul_3v3>; 24 enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>; 25 status = "disabled"; 26 }; 27 28 beeper: beeper { 29 compatible = "gpio-beeper"; 30 gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>; 31 }; 32 33 gpio_buttons: gpio-keys { 34 compatible = "gpio-keys"; 35 pinctrl-names = "default"; 36 pinctrl-0 = <&pinctrl_buttons>; 37 38 button1 { 39 label = "s14"; 40 linux,code = <KEY_1>; 41 gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>; 42 }; 43 44 button2 { 45 label = "s6"; 46 linux,code = <KEY_2>; 47 gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>; 48 }; 49 50 button3 { 51 label = "s7"; 52 linux,code = <KEY_3>; 53 gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>; 54 }; 55 56 power-button { 57 label = "POWER"; 58 linux,code = <KEY_POWER>; 59 gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; 60 wakeup-source; 61 }; 62 }; 63 64 gpio-leds { 65 compatible = "gpio-leds"; 66 status = "okay"; 67 68 led1 { 69 label = "led1"; 70 gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>; 71 linux,default-trigger = "default-on"; 72 }; 73 74 led2 { 75 label = "led2"; 76 gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>; 77 linux,default-trigger = "heartbeat"; 78 }; 79 }; 80 81 reg_lcd_pwr: regulator-lcd-pwr { 82 compatible = "regulator-fixed"; 83 regulator-name = "lcd-pwr"; 84 gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>; 85 enable-active-high; 86 status = "disabled"; 87 }; 88 89 reg_mba6ul_3v3: regulator-mba6ul-3v3 { 90 compatible = "regulator-fixed"; 91 regulator-name = "supply-mba6ul-3v3"; 92 regulator-min-microvolt = <3300000>; 93 regulator-max-microvolt = <3300000>; 94 regulator-always-on; 95 }; 96 97 reg_mba6ul_5v0: regulator-mba6ul-5v0 { 98 compatible = "regulator-fixed"; 99 regulator-name = "supply-mba6ul-5v0"; 100 regulator-min-microvolt = <5000000>; 101 regulator-max-microvolt = <5000000>; 102 regulator-always-on; 103 }; 104 105 reg_mpcie: regulator-mpcie-3v3 { 106 compatible = "regulator-fixed"; 107 regulator-name = "mpcie-3v3"; 108 regulator-min-microvolt = <3300000>; 109 regulator-max-microvolt = <3300000>; 110 gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>; 111 enable-active-high; 112 regulator-always-on; 113 startup-delay-us = <500000>; 114 vin-supply = <®_mba6ul_3v3>; 115 }; 116 117 reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 { 118 compatible = "regulator-fixed"; 119 gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>; 120 enable-active-high; 121 regulator-name = "otg2-vbus-supply-5v0"; 122 regulator-min-microvolt = <5000000>; 123 regulator-max-microvolt = <5000000>; 124 vin-supply = <®_mpcie>; 125 }; 126 127 reserved-memory { 128 #address-cells = <1>; 129 #size-cells = <1>; 130 ranges; 131 132 linux,cma { 133 compatible = "shared-dma-pool"; 134 reusable; 135 size = <0x6000000>; 136 linux,cma-default; 137 }; 138 }; 139 140 sound { 141 compatible = "fsl,imx-audio-tlv320aic32x4"; 142 model = "imx-audio-tlv320aic32x4"; 143 ssi-controller = <&sai1>; 144 audio-codec = <&tlv320aic32x4>; 145 audio-asrc = <&asrc>; 146 }; 147}; 148 149&can1 { 150 pinctrl-names = "default"; 151 pinctrl-0 = <&pinctrl_flexcan1>; 152 xceiver-supply = <®_mba6ul_3v3>; 153 status = "okay"; 154}; 155 156&can2 { 157 pinctrl-names = "default"; 158 pinctrl-0 = <&pinctrl_flexcan2>; 159 xceiver-supply = <®_mba6ul_3v3>; 160 status = "okay"; 161}; 162 163&clks { 164 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 165 assigned-clock-rates = <768000000>; 166}; 167 168&ecspi2 { 169 pinctrl-names = "default"; 170 pinctrl-0 = <&pinctrl_ecspi2>; 171 num-cs = <1>; 172 status = "okay"; 173}; 174 175&fec1 { 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_enet1>; 178 phy-mode = "rmii"; 179 phy-handle = <ðphy0>; 180 phy-supply = <®_mba6ul_3v3>; 181 phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>; 182 phy-reset-duration = <25>; 183 phy-reset-post-delay = <1>; 184 status = "okay"; 185}; 186 187&fec2 { 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>; 190 phy-mode = "rmii"; 191 phy-handle = <ðphy1>; 192 phy-supply = <®_mba6ul_3v3>; 193 phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>; 194 phy-reset-duration = <25>; 195 phy-reset-post-delay = <1>; 196 status = "okay"; 197 198 mdio { 199 #address-cells = <1>; 200 #size-cells = <0>; 201 202 ethphy0: ethernet-phy@0 { 203 compatible = "ethernet-phy-ieee802.3-c22"; 204 clocks = <&clks IMX6UL_CLK_ENET_REF>; 205 reg = <0>; 206 max-speed = <100>; 207 }; 208 209 ethphy1: ethernet-phy@1 { 210 compatible = "ethernet-phy-ieee802.3-c22"; 211 clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; 212 reg = <1>; 213 max-speed = <100>; 214 }; 215 }; 216}; 217 218&i2c4 { 219 tlv320aic32x4: audio-codec@18 { 220 compatible = "ti,tlv320aic32x4"; 221 reg = <0x18>; 222 clocks = <&clks IMX6UL_CLK_SAI1>; 223 clock-names = "mclk"; 224 ldoin-supply = <®_mba6ul_3v3>; 225 iov-supply = <®_mba6ul_3v3>; 226 }; 227 228 jc42: temperature-sensor@19 { 229 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 230 reg = <0x19>; 231 }; 232 233 expander_out0: gpio-expander@20 { 234 compatible = "nxp,pca9554"; 235 reg = <0x20>; 236 gpio-controller; 237 #gpio-cells = <2>; 238 vcc-supply = <®_mba6ul_3v3>; 239 }; 240 241 expander_in0: gpio-expander@21 { 242 compatible = "nxp,pca9554"; 243 reg = <0x21>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_expander_in0>; 246 interrupt-parent = <&gpio4>; 247 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 248 interrupt-controller; 249 #interrupt-cells = <2>; 250 gpio-controller; 251 #gpio-cells = <2>; 252 vcc-supply = <®_mba6ul_3v3>; 253 254 enet1_int-hog { 255 gpio-hog; 256 gpios = <6 0>; 257 input; 258 }; 259 260 enet2_int-hog { 261 gpio-hog; 262 gpios = <7 0>; 263 input; 264 }; 265 }; 266 267 expander_out1: gpio-expander@22 { 268 compatible = "nxp,pca9554"; 269 reg = <0x22>; 270 gpio-controller; 271 #gpio-cells = <2>; 272 vcc-supply = <®_mba6ul_3v3>; 273 }; 274 275 analog_touch: touchscreen@41 { 276 compatible = "st,stmpe811"; 277 reg = <0x41>; 278 interrupts = <21 IRQ_TYPE_EDGE_FALLING>; 279 interrupt-parent = <&gpio4>; 280 status = "disabled"; 281 282 touchscreen { 283 compatible = "st,stmpe-ts"; 284 st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ 285 st,ave-ctrl = <3>; /* 8 sample average control */ 286 st,fraction-z = <7>; /* 7 length fractional part in z */ 287 /* 288 * 50 mA typical 80 mA max touchscreen drivers 289 * current limit value 290 */ 291 st,i-drive = <1>; 292 st,mod-12b = <1>; /* 12-bit ADC */ 293 st,ref-sel = <0>; /* internal ADC reference */ 294 st,sample-time = <4>; /* ADC converstion time: 80 clocks */ 295 st,settling = <3>; /* 1 ms panel driver settling time */ 296 st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */ 297 }; 298 }; 299 300 /* NXP SE97BTP with temperature sensor + eeprom */ 301 se97b: eeprom@51 { 302 compatible = "nxp,se97b", "atmel,24c02"; 303 reg = <0x51>; 304 pagesize = <16>; 305 vcc-supply = <®_mba6ul_3v3>; 306 }; 307}; 308 309&pwm2 { 310 pinctrl-names = "default"; 311 pinctrl-0 = <&pinctrl_pwm2>; 312 status = "okay"; 313}; 314 315&sai1 { 316 pinctrl-names = "default"; 317 pinctrl-0 = <&pinctrl_sai1>; 318 assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>, 319 <&clks IMX6UL_CLK_SAI1>; 320 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 321 assigned-clock-rates = <0>, <24000000>; 322 fsl,sai-mclk-direction-output; 323 status = "okay"; 324}; 325 326&uart1 { 327 pinctrl-names = "default"; 328 pinctrl-0 = <&pinctrl_uart1>; 329 status = "okay"; 330}; 331 332&uart3 { 333 pinctrl-names = "default"; 334 pinctrl-0 = <&pinctrl_uart3>; 335 status = "okay"; 336}; 337 338&uart6 { 339 pinctrl-names = "default"; 340 pinctrl-0 = <&pinctrl_uart6>; 341 /* for DTE mode, add below change */ 342 /* fsl,dte-mode; */ 343 /* pinctrl-0 = <&pinctrl_uart6dte>; */ 344 uart-has-rtscts; 345 linux,rs485-enabled-at-boot-time; 346 rs485-rts-active-low; 347 rs485-rx-during-tx; 348 status = "okay"; 349}; 350 351/* otg-port */ 352&usbotg1 { 353 pinctrl-names = "default"; 354 pinctrl-0 = <&pinctrl_usb_otg1>; 355 power-active-high; 356 over-current-active-low; 357 /* we implement only dual role but not a fully featured OTG */ 358 hnp-disable; 359 srp-disable; 360 adp-disable; 361 dr_mode = "otg"; 362 status = "okay"; 363}; 364 365/* 7-port usb hub */ 366/* id, pwr, oc pins not connected */ 367&usbotg2 { 368 disable-over-current; 369 vbus-supply = <®_otg2vbus_5v0>; 370 dr_mode = "host"; 371 status = "okay"; 372}; 373 374&usdhc1 { 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pinctrl_usdhc1>; 377 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 378 wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; 379 bus-width = <4>; 380 vmmc-supply = <®_mba6ul_3v3>; 381 vqmmc-supply = <®_vccsd>; 382 no-1-8-v; 383 no-mmc; 384 no-sdio; 385 status = "okay"; 386}; 387 388&wdog1 { 389 pinctrl-names = "default"; 390 pinctrl-0 = <&pinctrl_wdog1>; 391 fsl,ext-reset-output; 392 status = "okay"; 393}; 394 395&iomuxc { 396 pinctrl_buttons: buttonsgrp { 397 fsl,pins = < 398 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x100b0 399 >; 400 }; 401 402 pinctrl_ecspi2: ecspi2grp { 403 fsl,pins = < 404 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b020 405 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b020 406 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b020 407 MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x1b020 408 >; 409 }; 410 411 pinctrl_enet1: enet1grp { 412 fsl,pins = < 413 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 414 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 415 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 416 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 417 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 418 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 419 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 420 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 421 >; 422 }; 423 424 pinctrl_enet2: enet2grp { 425 fsl,pins = < 426 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 427 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 428 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 429 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 430 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0 431 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0 432 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 433 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 434 >; 435 }; 436 437 pinctrl_enet2_mdc: enet2mdcgrp { 438 fsl,pins = < 439 /* mdio */ 440 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 441 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 442 >; 443 }; 444 445 pinctrl_expander_in0: expanderin0grp { 446 fsl,pins = < 447 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b0b1 448 >; 449 }; 450 451 pinctrl_flexcan1: flexcan1grp { 452 fsl,pins = < 453 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 454 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 455 >; 456 }; 457 458 pinctrl_flexcan2: flexcan2grp { 459 fsl,pins = < 460 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 461 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 462 >; 463 }; 464 465 pinctrl_pwm2: pwm2grp { 466 fsl,pins = < 467 /* 100 k PD, DSE 120 OHM, SPPEED LO */ 468 MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050 469 >; 470 }; 471 472 pinctrl_sai1: sai1grp { 473 fsl,pins = < 474 MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b1 475 MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b1 476 MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 477 MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 478 MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b1 479 >; 480 }; 481 482 pinctrl_uart1: uart1grp { 483 fsl,pins = < 484 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 485 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 486 >; 487 }; 488 489 pinctrl_uart3: uart3grp { 490 fsl,pins = < 491 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 492 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 493 >; 494 }; 495 496 pinctrl_uart6: uart6grp { 497 fsl,pins = < 498 MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 499 MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 500 MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1 501 MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1 502 >; 503 }; 504 505 pinctrl_uart6dte: uart6dte { 506 fsl,pins = < 507 MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1 508 MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1 509 MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x1b0b1 510 MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x1b0b1 511 >; 512 }; 513 514 pinctrl_usb_otg1: usbotg1grp { 515 fsl,pins = < 516 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059 517 MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0 518 MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x0001b099 519 >; 520 }; 521 522 pinctrl_usdhc1: usdhc1grp { 523 fsl,pins = < 524 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 525 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059 526 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059 527 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059 528 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059 529 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059 530 /* WP */ 531 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 532 /* CD */ 533 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 534 >; 535 }; 536 537 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 538 fsl,pins = < 539 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 540 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9 541 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9 542 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9 543 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9 544 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9 545 /* WP */ 546 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 547 /* CD */ 548 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 549 >; 550 }; 551 552 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 553 fsl,pins = < 554 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 555 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9 556 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9 557 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9 558 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9 559 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9 560 /* WP */ 561 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 562 /* CD */ 563 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 564 >; 565 }; 566 567 pinctrl_wdog1: wdog1grp { 568 fsl,pins = < 569 MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099 570 >; 571 }; 572}; 573